Update the Rd-N2-Cfg1 platform specific ACPI tables to ACPI version
v6.4.

Signed-off-by: Pranav Madhu <pranav.madhu@...>
---
Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Madt.aslc | 112 ++++++++++------=
----
Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Pptt.aslc | 73 ++++++-------
2 files changed, 93 insertions(+), 92 deletions(-)

diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Madt.aslc b/Platform=
/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Madt.aslc
index c6bb29a25c61..65926027eadf 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Madt.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Madt.aslc
@@ -1,23 +1,22 @@
/** @file
-* Multiple APIC Description Table (MADT) for RD-N2-Cfg1 platform
-*
-* This file lists all the processors available on the platform that the =
OSPM
-* can enumerate and boot. It also lists all the interrupt controllers av=
ailable
-* in the system.
-*
-* Copyright (c) 2021, Arm Ltd. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
-* @par Specification Reference:
-* - ACPI 6.3, Chapter 5, Section 5.2.12, Multiple APIC Description Tab=
le
+ Multiple APIC Description Table (MADT) for RD-N2-Cfg1 platform
+
+ The MADT table provides OSPM with information necessary for operation =
on
+ systems with Generic interrupt controller (GIC). The information about=
the GIC
+ CPU interface, redistributor, distributor and ITS blocks on the Rd-N2-=
Cfg1
+ platform is included in this table.
+
+ Copyright (c) 2021 - 2022, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+ - ACPI 6.4, Chapter 5, Section 5.2.12, Multiple APIC Description Tab=
le
**/
=20
#include <Library/AcpiLib.h>
#include <Library/ArmLib.h>
#include <Library/PcdLib.h>
-#include <IndustryStandard/Acpi.h>
-
#include "SgiAcpiHeader.h"
#include "SgiPlatform.h"
=20
@@ -28,69 +27,70 @@
#pragma pack (1)
=20
typedef struct {
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
- EFI_ACPI_6_2_GIC_STRUCTURE GicInterfaces[CO=
RE_CNT];
- EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;
- EFI_ACPI_6_2_GICR_STRUCTURE GicRedistributor=
;
- EFI_ACPI_6_2_GIC_ITS_STRUCTURE GicIts[3];
-} EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE;
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
+ EFI_ACPI_6_4_GIC_STRUCTURE GicInterfaces[CO=
RE_CNT];
+ EFI_ACPI_6_4_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;
+ EFI_ACPI_6_4_GICR_STRUCTURE GicRedistributor=
;
+ EFI_ACPI_6_4_GIC_ITS_STRUCTURE GicIts[3];
+} EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE;
=20
#pragma pack ()
=20
-STATIC EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE Madt =3D {
+STATIC EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE Madt =3D {
{
ARM_ACPI_HEADER (
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE,
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE,
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
),
// MADT specific fields
0, // LocalApicAddress
0 // Flags
},
{
- // Format: EFI_ACPI_6_2_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr=
, Flags,
+ // Format: EFI_ACPI_6_4_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr=
, Flags,
// PmuIrq, GicBase, GicVBas=
e,
// GicHBase, GsivId, GicRBa=
se,
- // Efficiency)
+ // Efficiency,
+ // SpeOverflowInterrupt)
// Note: The GIC Structure of the primary CPU must be the first entr=
y
- // (see note in 5.2.12.14 GICC Structure of ACPI v6.2).
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core0
- 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
- 0, 0, 0, 25, 0, 0),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core1
- 0, 1, GET_MPID(0x100, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
- 0, 0, 0, 25, 0, 0),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core2
- 0, 2, GET_MPID(0x200, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
- 0, 0, 0, 25, 0, 0),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core3
- 0, 3, GET_MPID(0x300, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
- 0, 0, 0, 25, 0, 0),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core4
- 0, 4, GET_MPID(0x400, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
- 0, 0, 0, 25, 0, 0),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core5
- 0, 5, GET_MPID(0x500, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
- 0, 0, 0, 25, 0, 0),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core6
- 0, 6, GET_MPID(0x600, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
- 0, 0, 0, 25, 0, 0),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core7
- 0, 7, GET_MPID(0x700, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
- 0, 0, 0, 25, 0, 0),
+ // (see chapter 5.2.12.14 GICC Structure of ACPI v6.4).
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core0
+ 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
+ 0, 0, 0, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core1
+ 0, 1, GET_MPID(0x100, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
+ 0, 0, 0, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core2
+ 0, 2, GET_MPID(0x200, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
+ 0, 0, 0, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core3
+ 0, 3, GET_MPID(0x300, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
+ 0, 0, 0, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core4
+ 0, 4, GET_MPID(0x400, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
+ 0, 0, 0, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core5
+ 0, 5, GET_MPID(0x500, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
+ 0, 0, 0, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core6
+ 0, 6, GET_MPID(0x600, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
+ 0, 0, 0, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core7
+ 0, 7, GET_MPID(0x700, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
+ 0, 0, 0, 25, 0, 0, 0),
},
// GIC Distributor Entry
- EFI_ACPI_6_2_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorB=
ase),
+ EFI_ACPI_6_4_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorB=
ase),
0, 3),
// GIC Redistributor
- EFI_ACPI_6_2_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributor=
sBase),
+ EFI_ACPI_6_4_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributor=
sBase),
SIZE_16MB),
// GIC ITS
{
- EFI_ACPI_6_2_GIC_ITS_INIT(0, 0x30040000),
- EFI_ACPI_6_2_GIC_ITS_INIT(1, 0x30080000),
- EFI_ACPI_6_2_GIC_ITS_INIT(2, 0x300C0000),
+ EFI_ACPI_6_4_GIC_ITS_INIT(0, 0x30040000),
+ EFI_ACPI_6_4_GIC_ITS_INIT(1, 0x30080000),
+ EFI_ACPI_6_4_GIC_ITS_INIT(2, 0x300C0000),
},
};
=20
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Pptt.aslc b/Platform=
/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Pptt.aslc
index 54eb6d6c41b3..9db765c50059 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Pptt.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Pptt.aslc
@@ -1,24 +1,22 @@
/** @file
-* Processor Properties Topology Table (PPTT) for RD-N2-Cfg1 platform
-*
-* This file describes the topological structure of the processor block o=
n the
-* RD-N2-Cfg1 platform in the form as defined by ACPI PPTT table. The RD-=
N2-Cfg1
-* platform includes eight single-thread CPUS. Each of the CPUs include 6=
4KB
-* L1 Data cache, 64KB L1 Instruction cache and 1MB L2 cache. The platfor=
m also
-* includes system level cache of 8MB.
-*
-* Copyright (c) 2021 - 2022, Arm Limited. All rights reserved.
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
-* @par Specification Reference:
-* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology=
Table
+ Processor Properties Topology Table (PPTT) for RD-N2-Cfg1 platform
+
+ This file describes the topological structure of the processor block o=
n the
+ RD-N2-Cfg1 platform in the form as defined by ACPI PPTT table. The RD-=
N2-Cfg1
+ platform includes eight single-thread CPUS. Each of the CPUs include 6=
4KB
+ L1 Data cache, 64KB L1 Instruction cache and 1MB L2 cache. The platfor=
m also
+ includes system level cache of 8MB.
+
+ Copyright (c) 2021 - 2022, Arm Limited. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+ - ACPI 6.4, Chapter 5, Section 5.2.29, Processor Properties Topology=
Table
**/
=20
-#include <IndustryStandard/Acpi.h>
#include <Library/AcpiLib.h>
#include <Library/ArmLib.h>
#include <Library/PcdLib.h>
-
#include "SgiAcpiHeader.h"
#include "SgiPlatform.h"
=20
@@ -31,10 +29,10 @@
#define PPTT_CORE_INIT(PackageId, ClusterId, CpuId) =
\
{ =
\
/* Parameters for CPU Core */ =
\
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( =
\
+ EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( =
\
OFFSET_OF (RD_PPTT_CORE, DCache), /* Length */ =
\
PPTT_PROCESSOR_CORE_FLAGS, /* Flag */ =
\
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, =
\
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, =
\
Package.Cluster[ClusterId]), /* Parent */ =
\
((PackageId << 4) | ClusterId), /* ACPI Id */ =
\
2 /* Num of private resource *=
/ \
@@ -42,47 +40,50 @@
=
\
/* Offsets of the private resources */ =
\
{ =
\
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, =
\
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, =
\
Package.Cluster[ClusterId].Core[CpuId].DCache), =
\
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, =
\
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, =
\
Package.Cluster[ClusterId].Core[CpuId].ICache) =
\
}, =
\
=
\
/* L1 data cache parameters */ =
\
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( =
\
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( =
\
PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ =
\
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, =
\
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, =
\
Package.Cluster[ClusterId].Core[CpuId].L2Cache), =
\
/* Next level of cache */ =
\
SIZE_64KB, /* Size */ =
\
256, /* Num of sets */ =
\
4, /* Associativity */ =
\
PPTT_DATA_CACHE_ATTR, /* Attributes */ =
\
- 64 /* Line size */ =
\
+ 64, /* Line size */ =
\
+ (((PackageId << 4) | ClusterId) + 1) /* Cache id */ =
\
), =
\
=
\
/* L1 instruction cache parameters */ =
\
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( =
\
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( =
\
PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ =
\
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, =
\
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, =
\
Package.Cluster[ClusterId].Core[CpuId].L2Cache), =
\
/* Next level of cache */ =
\
SIZE_64KB, /* Size */ =
\
256, /* Num of sets */ =
\
4, /* Associativity */ =
\
PPTT_INST_CACHE_ATTR, /* Attributes */ =
\
- 64 /* Line size */ =
\
+ 64, /* Line size */ =
\
+ (((PackageId << 4) | ClusterId) + 1) /* Cache id */ =
\
), =
\
=
\
/* L2 cache parameters */ =
\
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( =
\
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( =
\
PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ =
\
0, /* Next level of cache */ =
\
SIZE_1MB, /* Size */ =
\
2048, /* Num of sets */ =
\
8, /* Associativity */ =
\
PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ =
\
- 64 /* Line size */ =
\
+ 64, /* Line size */ =
\
+ (((PackageId << 4) | ClusterId) + 1) /* Cache id */ =
\
), =
\
}
=20
@@ -94,10 +95,10 @@
#define PPTT_CLUSTER_INIT(PackageId, ClusterId) =
\
{ =
\
/* Parameters for Cluster */ =
\
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( =
\
+ EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( =
\
OFFSET_OF (RD_PPTT_MINIMAL_CLUSTER, Core), /* Length */ =
\
PPTT_PROCESSOR_CLUSTER_FLAGS, /* Flag */ =
\
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, =
\
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, =
\
Package), /* Parent */ =
\
((PackageId << 4) | ClusterId), /* ACPI Id */ =
\
0 /* Num of private resource *=
/ \
@@ -114,22 +115,22 @@
* Processor Properties Topology Table
*/
typedef struct {
- EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header;
+ EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header;
RD_PPTT_PACKAGE Package;
-} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE;
+} EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE;
#pragma pack ()
=20
-STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt =3D {
+STATIC EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt =3D {
{
ARM_ACPI_HEADER (
- EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATU=
RE,
- EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
- EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
+ EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATU=
RE,
+ EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
+ EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
)
},
=20
{
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT (
+ EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT (
OFFSET_OF (RD_PPTT_PACKAGE, Cluster[0]),
PPTT_PROCESSOR_PACKAGE_FLAGS, 0, 0, 0),
=20
--=20
2.17.1