[edk2-platforms][PATCH V2 2/9] Platform/Sgi: Update ACPI version to v6.4 for SGI-575 platform

Home Messages Hashtags Subgroups Calendar

#89001

[edk2-platforms][PATCH V2 2/9] Platform/Sgi: Update ACPI version to v6.4 for SGI-575 platform

Pranav Madhu #89001 Update the SGI-575 platform specific ACPI tables to ACPI version v6.4. Signed-off-by: Pranav Madhu <pranav.madhu@...> --- Platform/ARM/SgiPkg/AcpiTables/Sgi575/Madt.aslc \| 105 +++++++++++-------= -- Platform/ARM/SgiPkg/AcpiTables/Sgi575/Pptt.aslc \| 86 ++++++++-------- 2 files changed, 100 insertions(+), 91 deletions(-) diff --git a/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Madt.aslc b/Platform/A= RM/SgiPkg/AcpiTables/Sgi575/Madt.aslc index f04b77929d71..d3d7d946655f 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Madt.aslc +++ b/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Madt.aslc @@ -1,18 +1,24 @@ /** @file -* Multiple APIC Description Table (MADT) -* -* Copyright (c) 2018, ARM Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* + Multiple APIC Description Table (MADT) + + The MADT table provides OSPM with information necessary for operation = on + systems with Generic interrupt controller (GIC). The information about= the GIC + CPU interface, redistributor, distributor and ITS blocks on the SGI-57= 5 + platform is included in this table. + + Copyright (c) 2018 - 2022, Arm Limited. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Specification Reference: + - ACPI 6.4, Chapter 5, Section 5.2.12, Multiple APIC Description Tab= le */ =20 -#include "SgiPlatform.h" -#include "SgiAcpiHeader.h" #include <Library/AcpiLib.h> #include <Library/ArmLib.h> #include <Library/PcdLib.h> -#include <IndustryStandard/Acpi.h> +#include "SgiAcpiHeader.h" +#include "SgiPlatform.h" =20 #define CORES (FixedPcdGet32 (PcdClusterCount) \ FixedPcdGet32 (PcdCoreCount)) @@ -21,75 +27,76 @@ #pragma pack (1) =20 typedef struct { - EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; - EFI_ACPI_6_2_GIC_STRUCTURE GicInterfaces[CO= RES]; - EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTURE GicDistributor; - EFI_ACPI_6_2_GICR_STRUCTURE GicRedistributor= ; - EFI_ACPI_6_2_GIC_ITS_STRUCTURE GicIts; -} EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE; + EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; + EFI_ACPI_6_4_GIC_STRUCTURE GicInterfaces[CO= RES]; + EFI_ACPI_6_4_GIC_DISTRIBUTOR_STRUCTURE GicDistributor; + EFI_ACPI_6_4_GICR_STRUCTURE GicRedistributor= ; + EFI_ACPI_6_4_GIC_ITS_STRUCTURE GicIts; +} EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE; =20 #pragma pack () =20 -STATIC EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE Madt =3D { +STATIC EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE Madt =3D { { ARM_ACPI_HEADER ( - EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, - EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE, - EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION + EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE, + EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION ), // MADT specific fields 0, // LocalApicAddress 0, // Flags }, { - // Format: EFI_ACPI_6_2_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr= , Flags, + // Format: EFI_ACPI_6_4_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr= , Flags, // PmuIrq, GicBase, GicVBas= e, // GicHBase, GsivId, GicRBa= se, - // Efficiency) + // Efficiency, + // SpeOverflowInterrupt) // Note: The GIC Structure of the primary CPU must be the first entr= y - // (see note in 5.2.12.14 GICC Structure of ACPI v6.2). - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // A75-0 - 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23, + // (see note in 5.2.12.14 GICC Structure of ACPI v6.4). + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // A75-0 + 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 /* GicRBase /, 0 / Efficiency /), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // A75-1 - 0, 1, GET_MPID(0x0, 0x100), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // A75-1 + 0, 1, GET_MPID(0x0, 0x100), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 / GicRBase /, 0 / Efficiency /), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // A75-2 - 0, 2, GET_MPID(0x0, 0x200), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // A75-2 + 0, 2, GET_MPID(0x0, 0x200), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 / GicRBase /, 0 / Efficiency /), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // A75-3 - 0, 3, GET_MPID(0x0, 0x300), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // A75-3 + 0, 3, GET_MPID(0x0, 0x300), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 / GicRBase /, 0 / Efficiency /), + 0x2c020000, 0x2c010000, 25, 0, 0, 0), =20 - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // A75-4 - 0, 4, GET_MPID(0x100, 0x00), EFI_ACPI_6_2_GIC_ENABLED, 23, + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // A75-4 + 0, 4, GET_MPID(0x100, 0x00), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 / GicRBase /, 0 / Efficiency /), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // A75-5 - 0, 5, GET_MPID(0x100, 0x100), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // A75-5 + 0, 5, GET_MPID(0x100, 0x100), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 / GicRBase /, 0 / Efficiency /), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // A75-6 - 0, 6, GET_MPID(0x100, 0x200), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // A75-6 + 0, 6, GET_MPID(0x100, 0x200), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 / GicRBase /, 0 / Efficiency /), - EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // A75-7 - 0, 7, GET_MPID(0x100, 0x300), EFI_ACPI_6_2_GIC_ENABLED, 23, + 0x2c020000, 0x2c010000, 25, 0, 0, 0), + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // A75-7 + 0, 7, GET_MPID(0x100, 0x300), EFI_ACPI_6_4_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicDistributorBase), - 0x2c020000, 0x2c010000, 25, 0 / GicRBase /, 0 / Efficiency /), + 0x2c020000, 0x2c010000, 25, 0, 0, 0), }, // GIC Distributor Entry - EFI_ACPI_6_2_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorB= ase), + EFI_ACPI_6_4_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorB= ase), 0, 3), // GIC Redistributor - EFI_ACPI_6_2_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributor= sBase), + EFI_ACPI_6_4_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributor= sBase), SIZE_1MB), // GIC ITS - EFI_ACPI_6_2_GIC_ITS_INIT(0, 0x30040000), + EFI_ACPI_6_4_GIC_ITS_INIT(0, 0x30040000), }; =20 // diff --git a/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Pptt.aslc b/Platform/A= RM/SgiPkg/AcpiTables/Sgi575/Pptt.aslc index a1b351379c9e..a0e958ceea7d 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Pptt.aslc +++ b/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Pptt.aslc @@ -1,27 +1,25 @@ /* @file -* Processor Properties Topology Table (PPTT) for SGI-575 platform -* -* This file describes the topological structure of the processor block o= n the -* SGI-575 platform in the form as defined by ACPI PPTT table. The SGI-57= 5 -* platform includes two clusters with four single-thread CPUS. Each of t= he CPUs -* include 64KB L1 Data cache, 64KB L1 Instruction cache and 512KB L2 cac= he. -* Each cluster includes a 2MB L3 cache. -* -* Copyright (c) 2021, ARM Limited. All rights reserved. -* -* SPDX-License-Identifier: BSD-2-Clause-Patent -* -* @par Specification Reference: -* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology= Table + Processor Properties Topology Table (PPTT) for SGI-575 platform + + This file describes the topological structure of the processor block o= n the + SGI-575 platform in the form as defined by ACPI PPTT table. The SGI-57= 5 + platform includes two clusters with four single-thread CPUS. Each of t= he CPUs + include 64KB L1 Data cache, 64KB L1 Instruction cache and 512KB L2 cac= he. + Each cluster includes a 2MB L3 cache. + + Copyright (c) 2021 - 2022, Arm Limited. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Specification Reference: + - ACPI 6.4, Chapter 5, Section 5.2.29, Processor Properties Topology= Table / =20 -#include <IndustryStandard/Acpi.h> #include <Library/AcpiLib.h> #include <Library/ArmLib.h> #include <Library/PcdLib.h> - -#include "SgiPlatform.h" #include "SgiAcpiHeader.h" +#include "SgiPlatform.h" =20 / Define helper macro for populating processor core information. =20 @@ -32,10 +30,10 @@ #define PPTT_CORE_INIT(PackageId, ClusterId, CpuId) = \ { = \ /* Parameters for CPU Core / = \ - EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ + EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ OFFSET_OF (RD_PPTT_CORE, DCache), / Length / = \ PPTT_PROCESSOR_CORE_FLAGS, / Flag / = \ - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ Package.Cluster[ClusterId]), / Parent / = \ ((PackageId << 3) \| (ClusterId << 2) \| CpuId), / ACPI Id / = \ 2 / Num of private resource = / \ @@ -43,47 +41,50 @@ = \ / Offsets of the private resources / = \ { = \ - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ Package.Cluster[ClusterId].Core[CpuId].DCache), = \ - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ Package.Cluster[ClusterId].Core[CpuId].ICache) = \ }, = \ = \ / L1 data cache parameters / = \ - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( = \ PPTT_CACHE_STRUCTURE_FLAGS, / Flag / = \ - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ Package.Cluster[ClusterId].Core[CpuId].L2Cache), = \ / Next level of cache / = \ SIZE_64KB, / Size / = \ 64, / Num of sets / = \ 16, / Associativity / = \ PPTT_DATA_CACHE_ATTR, / Attributes / = \ - 64 / Line size / = \ + 64, / Line size / = \ + (((PackageId << 3) \| (ClusterId << 2) \| CpuId) + 1) / Cache id = / \ ), = \ = \ / L1 instruction cache parameters / = \ - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( = \ PPTT_CACHE_STRUCTURE_FLAGS, / Flag / = \ - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ Package.Cluster[ClusterId].Core[CpuId].L2Cache), = \ / Next level of cache / = \ SIZE_64KB, / Size / = \ 256, / Num of sets / = \ 4, / Associativity / = \ PPTT_INST_CACHE_ATTR, / Attributes / = \ - 64 / Line size / = \ + 64, / Line size / = \ + (((PackageId << 3) \| (ClusterId << 2) \| CpuId) + 1) / Cache id = / \ ), = \ = \ / L2 cache parameters / = \ - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( = \ PPTT_CACHE_STRUCTURE_FLAGS, / Flag / = \ 0, / Next level of cache / = \ SIZE_512KB, / Size / = \ 1024, / Num of sets / = \ 8, / Associativity / = \ PPTT_UNIFIED_CACHE_ATTR, / Attributes / = \ - 64 / Line size / = \ + 64, / Line size / = \ + (((PackageId << 3) \| (ClusterId << 2) \| CpuId) + 1) / Cache id = / \ ), = \ } =20 @@ -95,29 +96,30 @@ #define PPTT_CLUSTER_INIT(PackageId, ClusterId) = \ { = \ / Parameters for Cluster / = \ - EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ + EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ OFFSET_OF (RD_PPTT_CLUSTER, L3Cache), = \ / Length / = \ PPTT_PROCESSOR_CLUSTER_FLAGS, / Flag / = \ - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ Package), / Parent / = \ ((PackageId << 1) \| ClusterId), / ACPI Id / = \ 1 / Num of private resource = / \ ), = \ = \ / Offsets of the private resources / = \ - OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ Package.Cluster[ClusterId].L3Cache), = \ = \ / L3 cache parameters / = \ - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( = \ + EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( = \ PPTT_CACHE_STRUCTURE_FLAGS, / Flag / = \ 0, / Next level of cache / = \ SIZE_2MB, / Size / = \ 2048, / Num of sets / = \ 16, / Associativity / = \ PPTT_UNIFIED_CACHE_ATTR, / Attributes / = \ - 64 / Line size / = \ + 64, / Line size / = \ + (((PackageId << 1) \| ClusterId) + 1) / Cache id / = \ ), = \ = \ / Initialize child cores / = \ @@ -131,7 +133,7 @@ =20 #pragma pack(1) typedef struct { - EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Package; + EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR Package; RD_PPTT_CLUSTER Cluster[CLUSTER_COUNT]; } SGI575_PPTT_PACKAGE; =20 @@ -139,22 +141,22 @@ typedef struct { Processor Properties Topology Table */ typedef struct { - EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header; + EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header; SGI575_PPTT_PACKAGE Package; -} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE; +} EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE; #pragma pack () =20 -STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt =3D { +STATIC EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt =3D { { ARM_ACPI_HEADER ( - EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATU= RE, - EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, - EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION + EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATU= RE, + EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, + EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION ) }, =20 { - EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( + EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( OFFSET_OF (SGI575_PPTT_PACKAGE, Cluster[0]), PPTT_PROCESSOR_PACKAGE_FLAGS, 0, 0, 0 ), --=20 2.17.1
More All Messages By This Member

#89001

Join {devel@edk2.groups.io to automatically receive all group messages.

Home Hashtags Subgroups Calendar About Features Pricing Updates Terms Help Twitter