[PATCH v3] MdePkg: Add registers of boot partition feature


Maggie Chu
 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3757

Add registers of boot partition feature which defined in NVM Express 1.4 Sp=
ec

Cc: Liming Gao <gaoliming@...>
Cc: Michael D Kinney <michael.d.kinney@...>
Cc: Zhiguang Liu <zhiguang.liu@...>
Signed-off-by: Maggie Chu <maggie.chu@...>
---
MdePkg/Include/IndustryStandard/Nvme.h | 108 ++++++++++++++++++++-----
1 file changed, 89 insertions(+), 19 deletions(-)

diff --git a/MdePkg/Include/IndustryStandard/Nvme.h b/MdePkg/Include/Indust=
ryStandard/Nvme.h
index 7d4aee9dc8..4a1d92c45d 100644
--- a/MdePkg/Include/IndustryStandard/Nvme.h
+++ b/MdePkg/Include/IndustryStandard/Nvme.h
@@ -2,11 +2,12 @@
Definitions based on NVMe spec. version 1.1.=0D
=0D
(C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>=0D
- Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>=0D
+ Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.<BR>=0D
SPDX-License-Identifier: BSD-2-Clause-Patent=0D
=0D
@par Specification Reference:=0D
NVMe Specification 1.1=0D
+ NVMe Specification 1.4=0D
=0D
**/=0D
=0D
@@ -18,18 +19,21 @@
//=0D
// controller register offsets=0D
//=0D
-#define NVME_CAP_OFFSET 0x0000 // Controller Capabilities=0D
-#define NVME_VER_OFFSET 0x0008 // Version=0D
-#define NVME_INTMS_OFFSET 0x000c // Interrupt Mask Set=0D
-#define NVME_INTMC_OFFSET 0x0010 // Interrupt Mask Clear=0D
-#define NVME_CC_OFFSET 0x0014 // Controller Configuration=0D
-#define NVME_CSTS_OFFSET 0x001c // Controller Status=0D
-#define NVME_NSSR_OFFSET 0x0020 // NVM Subsystem Reset=0D
-#define NVME_AQA_OFFSET 0x0024 // Admin Queue Attributes=0D
-#define NVME_ASQ_OFFSET 0x0028 // Admin Submission Queue Base Ad=
dress=0D
-#define NVME_ACQ_OFFSET 0x0030 // Admin Completion Queue Base Ad=
dress=0D
-#define NVME_SQ0_OFFSET 0x1000 // Submission Queue 0 (admin) Tai=
l Doorbell=0D
-#define NVME_CQ0_OFFSET 0x1004 // Completion Queue 0 (admin) Hea=
d Doorbell=0D
+#define NVME_CAP_OFFSET 0x0000 // Controller Capabilities=0D
+#define NVME_VER_OFFSET 0x0008 // Version=0D
+#define NVME_INTMS_OFFSET 0x000c // Interrupt Mask Set=0D
+#define NVME_INTMC_OFFSET 0x0010 // Interrupt Mask Clear=0D
+#define NVME_CC_OFFSET 0x0014 // Controller Configuration=0D
+#define NVME_CSTS_OFFSET 0x001c // Controller Status=0D
+#define NVME_NSSR_OFFSET 0x0020 // NVM Subsystem Reset=0D
+#define NVME_AQA_OFFSET 0x0024 // Admin Queue Attributes=0D
+#define NVME_ASQ_OFFSET 0x0028 // Admin Submission Queue Base A=
ddress=0D
+#define NVME_ACQ_OFFSET 0x0030 // Admin Completion Queue Base A=
ddress=0D
+#define NVME_BPINFO_OFFSET 0x0040 // Boot Partition Information=0D
+#define NVME_BPRSEL_OFFSET 0x0044 // Boot Partition Read Select=0D
+#define NVME_BPMBL_OFFSET 0x0048 // Boot Partition Memory Buffer =
Location=0D
+#define NVME_SQ0_OFFSET 0x1000 // Submission Queue 0 (admin) Ta=
il Doorbell=0D
+#define NVME_CQ0_OFFSET 0x1004 // Completion Queue 0 (admin) He=
ad Doorbell=0D
=0D
//=0D
// These register offsets are defined as 0x1000 + (N * (4 << CAP.DSTRD))=0D
@@ -51,11 +55,14 @@ typedef struct {
UINT8 To; // Timeout=0D
UINT16 Dstrd : 4;=0D
UINT16 Nssrs : 1; // NVM Subsystem Reset Supported NSSRS=0D
- UINT16 Css : 4; // Command Sets Supported - Bit 37=0D
- UINT16 Rsvd3 : 7;=0D
+ UINT16 Css : 8; // Command Sets Supported - Bit 37=0D
+ UINT16 Bps : 1; // Boot Partition Support - Bit 45 in NVMe1.4=0D
+ UINT16 Rsvd3 : 2;=0D
UINT8 Mpsmin : 4;=0D
UINT8 Mpsmax : 4;=0D
- UINT8 Rsvd4;=0D
+ UINT8 Pmrs : 1;=0D
+ UINT8 Cmbs : 1;=0D
+ UINT8 Rsvd4 : 6;=0D
} NVME_CAP;=0D
=0D
//=0D
@@ -115,7 +122,36 @@ typedef struct {
#define NVME_ACQ UINT64=0D
=0D
//=0D
-// 3.1.11 Offset (1000h + ((2y) * (4 << CAP.DSTRD))): SQyTDBL - Submission=
Queue y Tail Doorbell=0D
+// 3.1.13 Offset 40h: BPINFO - Boot Partition Information=0D
+//=0D
+typedef struct {=0D
+ UINT32 Bpsz : 15; // Boot Partition Size=0D
+ UINT32 Rsvd1 : 9;=0D
+ UINT32 Brs : 2; // Boot Read Status=0D
+ UINT32 Rsvd2 : 5;=0D
+ UINT32 Abpid : 1; // Active Boot Partition ID=0D
+} NVME_BPINFO;=0D
+=0D
+//=0D
+// 3.1.14 Offset 44h: BPRSEL - Boot Partition Read Select=0D
+//=0D
+typedef struct {=0D
+ UINT32 Bprsz : 10; // Boot Partition Read Size=0D
+ UINT32 Bprof : 20; // Boot Partition Read Offset=0D
+ UINT32 Rsvd1 : 1;=0D
+ UINT32 Bpid : 1; // Boot Partition Identifier=0D
+} NVME_BPRSEL;=0D
+=0D
+//=0D
+// 3.1.15 Offset 48h: BPMBL - Boot Partition Memory Buffer Location (Optio=
nal)=0D
+//=0D
+typedef struct {=0D
+ UINT64 Rsvd1 : 12;=0D
+ UINT64 Bmbba : 52; // Boot Partition Memory Buffer Base Address=0D
+} NVME_BPMBL;=0D
+=0D
+//=0D
+// 3.1.25 Offset (1000h + ((2y) * (4 << CAP.DSTRD))): SQyTDBL - Submission=
Queue y Tail Doorbell=0D
//=0D
typedef struct {=0D
UINT16 Sqt;=0D
@@ -353,7 +389,7 @@ typedef struct {
UINT8 Avscc; /* Admin Vendor Specific Command Configurati=
on */=0D
UINT8 Apsta; /* Autonomous Power State Transition Attribu=
tes */=0D
//=0D
- // Below fields before Rsvd2 are defined in NVM Express 1.3 Spec=0D
+ // Below fields before Rsvd2 are defined in NVM Express 1.4 Spec=0D
//=0D
UINT16 Wctemp; /* Warning Composite Temperature Thres=
hold */=0D
UINT16 Cctemp; /* Critical Composite Temperature Thre=
shold */=0D
@@ -361,7 +397,12 @@ typedef struct {
UINT32 Hmpre; /* Host Memory Buffer Preferred Size *=
/=0D
UINT32 Hmmin; /* Host Memory Buffer Minimum Size */=
=0D
UINT8 Tnvmcap[16]; /* Total NVM Capacity */=0D
- UINT8 Rsvd2[216]; /* Reserved as of NVM Express */=0D
+ UINT8 Unvmcap[16]; /* Unallocated NVM Capacity */=0D
+ UINT32 Rpmbs; /* Replay Protected Memory Block Suppo=
rt */=0D
+ UINT16 Edstt; /* Extended Device Self-test Time */=0D
+ UINT8 Dsto; /* Device Self-test Options */=0D
+ UINT8 Fwug; /* Firmware Update Granularity */=0D
+ UINT8 Rsvd2[192]; /* Reserved as of Nvm Express 1.4 Spec=
*/=0D
//=0D
// NVM Command Set Attributes=0D
//=0D
@@ -433,6 +474,34 @@ typedef struct {
UINT8 VendorData[3712]; /* Vendor specific data */=0D
} NVME_ADMIN_NAMESPACE_DATA;=0D
=0D
+//=0D
+// RPMB Device Configuration Block Data Structure as of Nvm Express 1.4 Sp=
ec=0D
+//=0D
+typedef struct {=0D
+ UINT8 Bppe; /* Boot Partition Protection Enable */=0D
+ UINT8 Bpl; /* Boot Partition Lock */=0D
+ UINT8 Nwpac; /* Namespace Write Protection Authentication Contro=
l */=0D
+ UINT8 Rsvd1[509]; /* Reserved as of Nvm Express 1.4 Spec */=0D
+} NVME_RPMB_CONFIGURATION_DATA;=0D
+=0D
+#define RPMB_FRAME_STUFF_BYTES 223=0D
+=0D
+//=0D
+// RPMB Data Frame as of Nvm Express 1.4 Spec=0D
+//=0D
+typedef struct {=0D
+ UINT8 Sbakamc[RPMB_FRAME_STUFF_BYTES]; /* [222-N:00] Stuff Bytes */=
=0D
+ /* [222:222-(N-1)] Authentica=
tion Key or Message Authentication Code (MAC) */=0D
+ UINT8 Rpmbt; /* RPMB Target */=0D
+ UINT64 Nonce[2];=0D
+ UINT32 Wcounter; /* Write Counter */=0D
+ UINT32 Address; /* Starting address of data t=
o be programmed to or read from the RPMB. */=0D
+ UINT32 Scount; /* Sector Count */=0D
+ UINT16 Result;=0D
+ UINT16 Rpmessage; /* Request/Response Message *=
/=0D
+ // UINT8 *Data; /* Data to be written or read=
by signed access where M =3D 512 * Sector Count. */=0D
+} NVME_RPMB_DATA_FRAME;=0D
+=0D
//=0D
// NvmExpress Admin Identify Cmd=0D
//=0D
@@ -564,6 +633,7 @@ typedef struct {
#define LID_ERROR_INFO 0x1=0D
#define LID_SMART_INFO 0x2=0D
#define LID_FW_SLOT_INFO 0x3=0D
+ #define LID_BP_INFO 0x15=0D
UINT32 Rsvd1 : 8;=0D
UINT32 Numd : 12; /* Number of Dwords */=0D
UINT32 Rsvd2 : 4; /* Reserved as of Nvm Express 1.1 Spec */=0D
--=20
2.26.2.windows.1

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