[PATCH 1/5] OvmfPkg: Handle Cloud Hypervisor host bridge


Boeuf, Sebastien
 

From: Sebastien Boeuf <sebastien.boeuf@intel.com>

Handle things differently when the detected host bridge matches the
Cloud Hypervisor PCI host bridge identifier.

Signed-off-by: Rob Bradford <robert.bradford@intel.com>
Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com>
---
OvmfPkg/Csm/CsmSupportLib/LegacyInterrupt.c | 1 +
OvmfPkg/Csm/CsmSupportLib/LegacyRegion.c | 1 +
OvmfPkg/Csm/CsmSupportLib/LegacyRegion.h | 1 +
OvmfPkg/Include/IndustryStandard/CloudHv.h | 35 +++++++++++
OvmfPkg/Include/OvmfPlatforms.h | 1 +
.../Library/AcpiTimerLib/BaseAcpiTimerLib.c | 3 +
.../AcpiTimerLib/BaseRomAcpiTimerLib.c | 4 ++
.../Library/AcpiTimerLib/DxeAcpiTimerLib.c | 3 +
.../PlatformBootManagerLib/BdsPlatform.c | 1 +
.../ResetSystemLib/BaseResetShutdown.c | 3 +
.../Library/ResetSystemLib/DxeResetShutdown.c | 11 +++-
OvmfPkg/PlatformPei/MemDetect.c | 63 ++++++++++---------
OvmfPkg/PlatformPei/Platform.c | 11 +++-
13 files changed, 105 insertions(+), 33 deletions(-)
create mode 100644 OvmfPkg/Include/IndustryStandard/CloudHv.h

diff --git a/OvmfPkg/Csm/CsmSupportLib/LegacyInterrupt.c b/OvmfPkg/Csm/CsmSupportLib/LegacyInterrupt.c
index 97ca21945f..50c9322911 100644
--- a/OvmfPkg/Csm/CsmSupportLib/LegacyInterrupt.c
+++ b/OvmfPkg/Csm/CsmSupportLib/LegacyInterrupt.c
@@ -189,6 +189,7 @@ LegacyInterruptInstall (
mLegacyInterruptDevice = LEGACY_INT_DEV_PIIX4;
break;
case INTEL_Q35_MCH_DEVICE_ID:
+ case CLOUDHV_DEVICE_ID: // Cloud Hypervisor host bridge
mLegacyInterruptDevice = LEGACY_INT_DEV_Q35;
break;
default:
diff --git a/OvmfPkg/Csm/CsmSupportLib/LegacyRegion.c b/OvmfPkg/Csm/CsmSupportLib/LegacyRegion.c
index fe9ae27c9d..9d6d6faf48 100644
--- a/OvmfPkg/Csm/CsmSupportLib/LegacyRegion.c
+++ b/OvmfPkg/Csm/CsmSupportLib/LegacyRegion.c
@@ -474,6 +474,7 @@ LegacyRegionInit (
mRegisterValues = mRegisterValues440;
break;
case INTEL_Q35_MCH_DEVICE_ID:
+ case CLOUDHV_DEVICE_ID: // Cloud Hypervisor host bridge
mRegisterValues = mRegisterValuesQ35;
break;
default:
diff --git a/OvmfPkg/Csm/CsmSupportLib/LegacyRegion.h b/OvmfPkg/Csm/CsmSupportLib/LegacyRegion.h
index e18cb97949..71df8f5fb2 100644
--- a/OvmfPkg/Csm/CsmSupportLib/LegacyRegion.h
+++ b/OvmfPkg/Csm/CsmSupportLib/LegacyRegion.h
@@ -17,6 +17,7 @@
#include <IndustryStandard/Pci.h>
#include <IndustryStandard/Q35MchIch9.h>
#include <IndustryStandard/I440FxPiix4.h>
+#include <IndustryStandard/CloudHv.h>

#include <Library/PciLib.h>
#include <Library/PcdLib.h>
diff --git a/OvmfPkg/Include/IndustryStandard/CloudHv.h b/OvmfPkg/Include/IndustryStandard/CloudHv.h
new file mode 100644
index 0000000000..6ab18ad50d
--- /dev/null
+++ b/OvmfPkg/Include/IndustryStandard/CloudHv.h
@@ -0,0 +1,35 @@
+/** @file
+ Various defines related to Cloud Hypervisor
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef __CLOUDHV_H__
+#define __CLOUDHV_H__
+
+//
+// Host Bridge Device ID
+//
+#define CLOUDHV_DEVICE_ID 0x0d57
+
+//
+// ACPI timer address
+//
+#define CLOUDHV_ACPI_TIMER_IO_ADDRESS 0xb008
+
+//
+// ACPI shutdown device address
+//
+#define CLOUDHV_ACPI_SHUTDOWN_IO_ADDRESS 0x03c0
+
+//
+// 32-bit MMIO memory hole base address
+//
+#define CLOUDHV_MMIO_HOLE_ADDRESS 0xc0000000
+
+//
+// 32-bit MMIO memory hole size
+//
+#define CLOUDHV_MMIO_HOLE_SIZE 0x38000000
+
+#endif // __CLOUDHV_H__
diff --git a/OvmfPkg/Include/OvmfPlatforms.h b/OvmfPkg/Include/OvmfPlatforms.h
index 3b85593b70..ad0b0d2803 100644
--- a/OvmfPkg/Include/OvmfPlatforms.h
+++ b/OvmfPkg/Include/OvmfPlatforms.h
@@ -16,6 +16,7 @@
#include <IndustryStandard/I440FxPiix4.h>
#include <IndustryStandard/Bhyve.h>
#include <IndustryStandard/Microvm.h>
+#include <IndustryStandard/CloudHv.h>

//
// OVMF Host Bridge DID Address
diff --git a/OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c b/OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c
index 7c593e8be1..e182ac2b7d 100644
--- a/OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c
+++ b/OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c
@@ -55,6 +55,9 @@ AcpiTimerLibConstructor (
AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);
AcpiEnBit = ICH9_ACPI_CNTL_ACPI_EN;
break;
+ case CLOUDHV_DEVICE_ID:
+ mAcpiTimerIoAddr = CLOUDHV_ACPI_TIMER_IO_ADDRESS;
+ return RETURN_SUCCESS;
default:
DEBUG ((DEBUG_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",
__FUNCTION__, HostBridgeDevId));
diff --git a/OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c b/OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c
index 52f3ea2dbf..a223153b2b 100644
--- a/OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c
+++ b/OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c
@@ -53,6 +53,8 @@ AcpiTimerLibConstructor (
AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);
AcpiEnBit = ICH9_ACPI_CNTL_ACPI_EN;
break;
+ case CLOUDHV_DEVICE_ID:
+ return RETURN_SUCCESS;
default:
DEBUG ((DEBUG_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",
__FUNCTION__, HostBridgeDevId));
@@ -107,6 +109,8 @@ InternalAcpiGetTimerTick (
case INTEL_Q35_MCH_DEVICE_ID:
Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);
break;
+ case CLOUDHV_DEVICE_ID:
+ return IoRead32 (CLOUDHV_ACPI_TIMER_IO_ADDRESS);
default:
DEBUG ((DEBUG_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",
__FUNCTION__, HostBridgeDevId));
diff --git a/OvmfPkg/Library/AcpiTimerLib/DxeAcpiTimerLib.c b/OvmfPkg/Library/AcpiTimerLib/DxeAcpiTimerLib.c
index 09076c0ade..3c9efb926f 100644
--- a/OvmfPkg/Library/AcpiTimerLib/DxeAcpiTimerLib.c
+++ b/OvmfPkg/Library/AcpiTimerLib/DxeAcpiTimerLib.c
@@ -50,6 +50,9 @@ AcpiTimerLibConstructor (
case INTEL_Q35_MCH_DEVICE_ID:
Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);
break;
+ case CLOUDHV_DEVICE_ID:
+ mAcpiTimerIoAddr = CLOUDHV_ACPI_TIMER_IO_ADDRESS;
+ return RETURN_SUCCESS;
default:
DEBUG ((DEBUG_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",
__FUNCTION__, HostBridgeDevId));
diff --git a/OvmfPkg/Library/PlatformBootManagerLib/BdsPlatform.c b/OvmfPkg/Library/PlatformBootManagerLib/BdsPlatform.c
index 186401296a..50bfb45351 100644
--- a/OvmfPkg/Library/PlatformBootManagerLib/BdsPlatform.c
+++ b/OvmfPkg/Library/PlatformBootManagerLib/BdsPlatform.c
@@ -1282,6 +1282,7 @@ PciAcpiInitialization (
PciWrite8 (PCI_LIB_ADDRESS (0, 0x1f, 0, 0x6b), PciHostIrqs[3]); // H
break;
case MICROVM_PSEUDO_DEVICE_ID:
+ case CLOUDHV_DEVICE_ID:
return;
default:
if (XenDetected ()) {
diff --git a/OvmfPkg/Library/ResetSystemLib/BaseResetShutdown.c b/OvmfPkg/Library/ResetSystemLib/BaseResetShutdown.c
index 21c80e4323..ba92299a3c 100644
--- a/OvmfPkg/Library/ResetSystemLib/BaseResetShutdown.c
+++ b/OvmfPkg/Library/ResetSystemLib/BaseResetShutdown.c
@@ -40,6 +40,9 @@ ResetShutdown (
case INTEL_Q35_MCH_DEVICE_ID:
AcpiPmBaseAddress = ICH9_PMBASE_VALUE;
break;
+ case CLOUDHV_DEVICE_ID:
+ IoWrite8 (CLOUDHV_ACPI_SHUTDOWN_IO_ADDRESS, 5 << 2 | 1 << 5);
+ CpuDeadLoop ();
default:
ASSERT (FALSE);
CpuDeadLoop ();
diff --git a/OvmfPkg/Library/ResetSystemLib/DxeResetShutdown.c b/OvmfPkg/Library/ResetSystemLib/DxeResetShutdown.c
index 5a75c32df3..a1c59ad042 100644
--- a/OvmfPkg/Library/ResetSystemLib/DxeResetShutdown.c
+++ b/OvmfPkg/Library/ResetSystemLib/DxeResetShutdown.c
@@ -34,6 +34,9 @@ DxeResetInit (
case INTEL_Q35_MCH_DEVICE_ID:
mAcpiPmBaseAddress = ICH9_PMBASE_VALUE;
break;
+ case CLOUDHV_DEVICE_ID:
+ mAcpiPmBaseAddress = 0;
+ break;
default:
ASSERT (FALSE);
CpuDeadLoop ();
@@ -56,7 +59,11 @@ ResetShutdown (
VOID
)
{
- IoBitFieldWrite16 (mAcpiPmBaseAddress + 4, 10, 13, 0);
- IoOr16 (mAcpiPmBaseAddress + 4, BIT13);
+ if (mAcpiPmBaseAddress == 0) {
+ IoWrite8 (CLOUDHV_ACPI_SHUTDOWN_IO_ADDRESS, 5 << 2 | 1 << 5);
+ } else {
+ IoBitFieldWrite16 (mAcpiPmBaseAddress + 4, 10, 13, 0);
+ IoOr16 (mAcpiPmBaseAddress + 4, BIT13);
+ }
CpuDeadLoop ();
}
diff --git a/OvmfPkg/PlatformPei/MemDetect.c b/OvmfPkg/PlatformPei/MemDetect.c
index d736b85e0d..a534d7845d 100644
--- a/OvmfPkg/PlatformPei/MemDetect.c
+++ b/OvmfPkg/PlatformPei/MemDetect.c
@@ -16,6 +16,7 @@ Module Name:
#include <IndustryStandard/E820.h>
#include <IndustryStandard/I440FxPiix4.h>
#include <IndustryStandard/Q35MchIch9.h>
+#include <IndustryStandard/CloudHv.h>
#include <PiPei.h>
#include <Register/Intel/SmramSaveStateMap.h>

@@ -135,21 +136,24 @@ QemuUc32BaseInitialization (
UINT32 LowerMemorySize;
UINT32 Uc32Size;

- if (mHostBridgeDevId == 0xffff /* microvm */) {
- return;
- }
-
- if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
- //
- // On q35, the 32-bit area that we'll mark as UC, through variable MTRRs,
- // starts at PcdPciExpressBaseAddress. The platform DSC is responsible for
- // setting PcdPciExpressBaseAddress such that describing the
- // [PcdPciExpressBaseAddress, 4GB) range require a very small number of
- // variable MTRRs (preferably 1 or 2).
- //
- ASSERT (FixedPcdGet64 (PcdPciExpressBaseAddress) <= MAX_UINT32);
- mQemuUc32Base = (UINT32)FixedPcdGet64 (PcdPciExpressBaseAddress);
- return;
+ switch (mHostBridgeDevId) {
+ case INTEL_Q35_MCH_DEVICE_ID:
+ //
+ // On q35, the 32-bit area that we'll mark as UC, through variable MTRRs,
+ // starts at PcdPciExpressBaseAddress. The platform DSC is responsible for
+ // setting PcdPciExpressBaseAddress such that describing the
+ // [PcdPciExpressBaseAddress, 4GB) range require a very small number of
+ // variable MTRRs (preferably 1 or 2).
+ //
+ ASSERT (FixedPcdGet64 (PcdPciExpressBaseAddress) <= MAX_UINT32);
+ mQemuUc32Base = (UINT32)FixedPcdGet64 (PcdPciExpressBaseAddress);
+ return;
+ case 0xffff: /* microvm */
+ return;
+ case CLOUDHV_DEVICE_ID:
+ Uc32Size = CLOUDHV_MMIO_HOLE_SIZE;
+ mQemuUc32Base = CLOUDHV_MMIO_HOLE_ADDRESS;
+ return;
}

ASSERT (mHostBridgeDevId == INTEL_82441_DEVICE_ID);
@@ -778,21 +782,22 @@ QemuInitializeRam (
if (IsMtrrSupported ()) {
MtrrGetAllMtrrs (&MtrrSettings);

- //
- // MTRRs disabled, fixed MTRRs disabled, default type is uncached
- //
- ASSERT ((MtrrSettings.MtrrDefType & BIT11) == 0);
- ASSERT ((MtrrSettings.MtrrDefType & BIT10) == 0);
- ASSERT ((MtrrSettings.MtrrDefType & 0xFF) == 0);
-
- //
- // flip default type to writeback
- //
- SetMem (&MtrrSettings.Fixed, sizeof MtrrSettings.Fixed, 0x06);
- ZeroMem (&MtrrSettings.Variables, sizeof MtrrSettings.Variables);
- MtrrSettings.MtrrDefType |= BIT11 | BIT10 | 6;
- MtrrSetAllMtrrs (&MtrrSettings);
+ if (mHostBridgeDevId != CLOUDHV_DEVICE_ID) {
+ //
+ // MTRRs disabled, fixed MTRRs disabled, default type is uncached
+ //
+ ASSERT ((MtrrSettings.MtrrDefType & BIT11) == 0);
+ ASSERT ((MtrrSettings.MtrrDefType & BIT10) == 0);
+ ASSERT ((MtrrSettings.MtrrDefType & 0xFF) == 0);

+ //
+ // flip default type to writeback
+ //
+ SetMem (&MtrrSettings.Fixed, sizeof MtrrSettings.Fixed, 0x06);
+ ZeroMem (&MtrrSettings.Variables, sizeof MtrrSettings.Variables);
+ MtrrSettings.MtrrDefType |= BIT11 | BIT10 | 6;
+ MtrrSetAllMtrrs (&MtrrSettings);
+ }
//
// Set memory range from 640KB to 1MB to uncacheable
//
diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c
index df2d9ad015..cad6a49680 100644
--- a/OvmfPkg/PlatformPei/Platform.c
+++ b/OvmfPkg/PlatformPei/Platform.c
@@ -346,6 +346,9 @@ MiscInitialization (
//
BuildCpuHob (mPhysMemAddressWidth, 16);

+ PcdStatus = PcdSet16S (PcdOvmfHostBridgePciDevId, mHostBridgeDevId);
+ ASSERT_RETURN_ERROR (PcdStatus);
+
//
// Determine platform type and save Host Bridge DID to PCD
//
@@ -372,14 +375,18 @@ MiscInitialization (
MICROVM_PSEUDO_DEVICE_ID);
ASSERT_RETURN_ERROR (PcdStatus);
return;
+ case CLOUDHV_DEVICE_ID:
+ DEBUG ((DEBUG_INFO, "%a: Cloud Hypervisor host bridge\n", __FUNCTION__));
+ PcdStatus = PcdSet16S (PcdOvmfHostBridgePciDevId,
+ CLOUDHV_DEVICE_ID);
+ ASSERT_RETURN_ERROR (PcdStatus);
+ return;
default:
DEBUG ((DEBUG_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",
__FUNCTION__, mHostBridgeDevId));
ASSERT (FALSE);
return;
}
- PcdStatus = PcdSet16S (PcdOvmfHostBridgePciDevId, mHostBridgeDevId);
- ASSERT_RETURN_ERROR (PcdStatus);

//
// If the appropriate IOspace enable bit is set, assume the ACPI PMBA has
--
2.30.2

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