This patch follows new Intel SDM to define CPUID.(EAX=3D7,ECX=3D0):EDX[30].
Signed-off-by: Star Zeng <star.zeng@...>
Cc: Michael D Kinney <michael.d.kinney@...>
Cc: Liming Gao <gaoliming@...>
Cc: Zhiguang Liu <zhiguang.liu@...>
Cc: Ray Ni <ray.ni@...>
---
MdePkg/Include/Register/Intel/Cpuid.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/MdePkg/Include/Register/Intel/Cpuid.h b/MdePkg/Include/Registe=
r/Intel/Cpuid.h
index 6f77e174c115..5ec85ba561ac 100644
--- a/MdePkg/Include/Register/Intel/Cpuid.h
+++ b/MdePkg/Include/Register/Intel/Cpuid.h
@@ -1587,9 +1587,9 @@ typedef union {
///=0D
UINT32 EnumeratesSupportForCapability:1;=0D
///=0D
- /// [Bit 30] Reserved.=0D
+ /// [Bit 30] Enumerates support for the IA32_CORE_CAPABILITIES MSR.=0D
///=0D
- UINT32 Reserved3:1;=0D
+ UINT32 EnumeratesSupportForCoreCapabilitiesMsr:1;=0D
///=0D
/// [Bit 31] Enumerates support for Speculative Store Bypass Disable (=
SSBD).=0D
/// Processors that set this bit sup-port the IA32_SPEC_CTRL MSR. They=
allow=0D
--=20
2.27.0.windows.1
