[PATCH v2] MinPlatformPkg/PciHostBridgeLibSimple: Fix Mem.Limit assignment


Benjamin Doron
 

In the case where the root bridge's Mem.Limit is the base address of
PCIe MMIO, subtract one to make a valid end address.

This fixes an issue where CpuDxe returns "Length(0x50000001) is not
aligned!" when PciHostBridgeDxe attempts to make this range uncacheable.

Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Eric Dong <eric.dong@intel.com>
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
---
Platform/Intel/MinPlatformPkg/Pci/Library/PciHostBridgeLibSimple/PciHostBr=
idgeLibSimple.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Platform/Intel/MinPlatformPkg/Pci/Library/PciHostBridgeLibSimp=
le/PciHostBridgeLibSimple.c b/Platform/Intel/MinPlatformPkg/Pci/Library/Pci=
HostBridgeLibSimple/PciHostBridgeLibSimple.c
index e231f747019e..0e3fee28b5d1 100644
--- a/Platform/Intel/MinPlatformPkg/Pci/Library/PciHostBridgeLibSimple/PciH=
ostBridgeLibSimple.c
+++ b/Platform/Intel/MinPlatformPkg/Pci/Library/PciHostBridgeLibSimple/PciH=
ostBridgeLibSimple.c
@@ -90,7 +90,7 @@ PciHostBridgeGetRootBridges (
if (PcdGet32(PcdPciReservedMemLimit) !=3D 0) {=0D
mRootBridgeTemplate.Mem.Limit =3D PcdGet32 (PcdPciReservedMemLimit);=0D
} else {=0D
- mRootBridgeTemplate.Mem.Limit =3D (UINT32) PcdGet64 (PcdPciExpressBase=
Address);=0D
+ mRootBridgeTemplate.Mem.Limit =3D (UINT32) PcdGet64 (PcdPciExpressBase=
Address) - 1;=0D
}=0D
=0D
mRootBridgeTemplate.MemAbove4G.Base =3D PcdGet64 (PcdPciReservedMemAbove=
4GBBase);=0D
--=20
2.31.1

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