Re: [PATCH] UefiCpuPkg VTF0 X64: Build page tables using 1-GByte Page Granularity


Dov Murik
 

On 19/07/2021 10:09, Ard Biesheuvel wrote:
On Mon, 19 Jul 2021 at 05:14, Ni, Ray <ray.ni@intel.com> wrote:

This change generates the reset vector binary which only contains 1G page table. If a platform doesn't support 1G page table, this will cause system hang.

To Ard and Jordan,
Can you evaluate whether this change impacts OVMF?
I don't have a clue, sorry, and I wouldn't know where to begin looking.

Brijesh, Dov, James, Erdem: after Laszlo's sudden departure, I will be
needing help reviewing OVMF patches that are highly specific to
SEV/SNP or x86 in general.
Adding Tom too - I think he modified the OVMF reset vector lately and
might know.


Please take a look.

I'm not an expert, but I think that OVMF has its own reset vector in
OvmfPkg/ResetVector, and therefore the changes in uefiCpuPkg will not
affect OVMF.


Regarding the patch itself:

(1) I suggest separating the python tooling changes to one patch,
verifying that the new python scripts generate the same binary files as
the original python scripts. Then add another patch which introduces
the reset vector changes.

(2) Do all x64 CPUs support 1 GB pages? Is it always enabled? Do we need
to check this capability somewhere?


-Dov




To Prince,
Can you evaluate whether this change impacts SimicsOpenBoardPkg?

Thanks,
Ray

-----Original Message-----
From: S, Ashraf Ali <ashraf.ali.s@intel.com>
Sent: Friday, July 2, 2021 8:25 PM
To: devel@edk2.groups.io
Cc: S, Ashraf Ali <ashraf.ali.s@intel.com>; Ni, Ray <ray.ni@intel.com>; Kumar, Rahul1 <rahul1.kumar@intel.com>; De, Debkumar <debkumar.de@intel.com>; Han, Harry <harry.han@intel.com>; West, Catharine <catharine.west@intel.com>; V, Sangeetha <sangeetha.v@intel.com>
Subject: [PATCH] UefiCpuPkg VTF0 X64: Build page tables using 1-GByte Page Granularity

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3473

X64 Reset Vector Code can access the memory range till 4GB using the Linear-Address Translation to a 2-MByte Page, when user wants to use more than 4G using 2M Page it will leads to use more number of Page table entries. using the 1-GByte Page table user can use more than 4G Memory by reducing the page table entries using 1-GByte Page, this patch attached can access memory range till 512GByte.
Build Scrips for Reset Vector currently based on Python 2 which is already EOL, needs to modify the build script based on Python 3, update the Binary accordingly.

Cc: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Debkumar De <debkumar.de@intel.com>
Cc: Harry Han <harry.han@intel.com>
Cc: Catharine West <catharine.west@intel.com>
Cc: Sangeetha V <sangeetha.v@intel.com>
Signed-off-by: Ashraf Ali S <ashraf.ali.s@intel.com>
---
.../Vtf0/Bin/ResetVector.ia32.port80.raw | Bin 516 -> 484 bytes
.../ResetVector/Vtf0/Bin/ResetVector.ia32.raw | Bin 484 -> 468 bytes
.../Vtf0/Bin/ResetVector.ia32.serial.raw | Bin 884 -> 868 bytes
.../Vtf0/Bin/ResetVector.x64.port80.raw | Bin 28676 -> 12292 bytes
.../ResetVector/Vtf0/Bin/ResetVector.x64.raw | Bin 28676 -> 12292 bytes
.../Vtf0/Bin/ResetVector.x64.serial.raw | Bin 28676 -> 12292 bytes
UefiCpuPkg/ResetVector/Vtf0/Build.py | 11 +--
.../ResetVector/Vtf0/Ia32/PageTables64.asm | 2 +-
UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt | 2 +-
.../Vtf0/Tools/FixupForRawSection.py | 4 +-
UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb | 4 +-
.../ResetVector/Vtf0/X64/1GPageTables.asm | 64 ++++++++++++++++++
.../X64/{PageTables.asm => 2MPageTables.asm} | 0
13 files changed, 77 insertions(+), 10 deletions(-) create mode 100644 UefiCpuPkg/ResetVector/Vtf0/X64/1GPageTables.asm
rename UefiCpuPkg/ResetVector/Vtf0/X64/{PageTables.asm => 2MPageTables.asm} (100%)

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diff --git a/UefiCpuPkg/ResetVector/Vtf0/Build.py b/UefiCpuPkg/ResetVector/Vtf0/Build.py
index 343c53b5ff..29f29ff0c2 100644
--- a/UefiCpuPkg/ResetVector/Vtf0/Build.py
+++ b/UefiCpuPkg/ResetVector/Vtf0/Build.py
@@ -1,7 +1,7 @@
## @file
# Automate the process of building the various reset vector types # -# Copyright (c) 2009, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2009 - 2021, Intel Corporation. All rights
+reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -32,16 +32,19 @@ for arch in ('ia32', 'x64'):
'-o', output,
'Vtf0.nasmb',
)
+ print(f"Command : {' '.join(commandLine)}")
ret = RunCommand(commandLine)
- print '\tASM\t' + output
- if ret != 0: sys.exit(ret)
+ if ret != 0:
+ print(f"something went wrong while executing the {commandLine[-1]}")
+ sys.exit()
+ print('\tASM\t' + output)

commandLine = (
'python',
'Tools/FixupForRawSection.py',
output,
)
- print '\tFIXUP\t' + output
+ print('\tFIXUP\t' + output)
ret = RunCommand(commandLine)
if ret != 0: sys.exit(ret)

diff --git a/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm b/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm
index 87a4125d4b..9cc6f56c17 100644
--- a/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm
+++ b/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm
@@ -15,7 +15,7 @@ BITS 32
SetCr3ForPageTables64:

;
- ; These pages are built into the ROM image in X64/PageTables.asm
+ ; These pages are built into the ROM image in X64/1GPageTables.asm
;
mov eax, ADDR_OF(TopLevelPageDirectory)
mov cr3, eax
diff --git a/UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt b/UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt
index e6e5b54243..eb9dd24ee2 100644
--- a/UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt
+++ b/UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt
@@ -29,7 +29,7 @@ EBP/RBP - Pointer to the start of the Boot Firmware Volume === HOW TO BUILD VTF0 ===

Dependencies:
-* Python 2.5~2.7
+* Python 3.0 or newer
* Nasm 2.03 or newer

To rebuild the VTF0 binaries:
diff --git a/UefiCpuPkg/ResetVector/Vtf0/Tools/FixupForRawSection.py b/UefiCpuPkg/ResetVector/Vtf0/Tools/FixupForRawSection.py
index c77438a0ce..de771eba22 100644
--- a/UefiCpuPkg/ResetVector/Vtf0/Tools/FixupForRawSection.py
+++ b/UefiCpuPkg/ResetVector/Vtf0/Tools/FixupForRawSection.py
@@ -1,7 +1,7 @@
## @file
# Apply fixup to VTF binary image for FFS Raw section # -# Copyright (c) 2008, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2008 - 2021, Intel Corporation. All rights
+reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -15,6 +15,6 @@ c = ((len(d) + 4 + 7) & ~7) - 4 if c > len(d):
c -= len(d)
f = open(sys.argv[1], 'wb')
- f.write('\x90' * c)
+ f.write(b'\x90' * c)
f.write(d)
f.close()
diff --git a/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb b/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb
index 493738c79c..0625efc456 100644
--- a/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb
+++ b/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb
@@ -2,7 +2,7 @@
; @file
; This file includes all other code files to assemble the reset vector code ; -; Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2008 - 2021, Intel Corporation. All rights
+reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent ;
;------------------------------------------------------------------------------
@@ -36,7 +36,7 @@
%include "PostCodes.inc"

%ifdef ARCH_X64
-%include "X64/PageTables.asm"
+%include "X64/1GPageTables.asm"
%endif

%ifdef DEBUG_PORT80
diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/1GPageTables.asm b/UefiCpuPkg/ResetVector/Vtf0/X64/1GPageTables.asm
new file mode 100644
index 0000000000..8ae6c4c98c
--- /dev/null
+++ b/UefiCpuPkg/ResetVector/Vtf0/X64/1GPageTables.asm
@@ -0,0 +1,64 @@
+;----------------------------------------------------------------------
+--------
+; @file
+; Emits Page Tables for 1:1 mapping of the addresses 0 - 0x8000000000
+(512GB) ; ; Copyright (c) 2021, Intel Corporation. All rights
+reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ;
+Linear-Address Translation to a 1-GByte Page ;
+;----------------------------------------------------------------------
+--------
+
+BITS 64
+
+%define ALIGN_TOP_TO_4K_FOR_PAGING
+
+%define PAGE_PRESENT 0x01
+%define PAGE_READ_WRITE 0x02
+%define PAGE_USER_SUPERVISOR 0x04
+%define PAGE_WRITE_THROUGH 0x08
+%define PAGE_CACHE_DISABLE 0x010
+%define PAGE_ACCESSED 0x020
+%define PAGE_DIRTY 0x040
+%define PAGE_PAT 0x080
+%define PAGE_GLOBAL 0x0100
+%define PAGE_1G 0x80
+
+%define PAGE_PDP_ATTR (PAGE_ACCESSED + \
+ PAGE_READ_WRITE + \
+ PAGE_PRESENT)
+
+%define PAGE_PDP_1G_ATTR (PAGE_ACCESSED + \
+ PAGE_READ_WRITE + \
+ PAGE_PRESENT + \
+ PAGE_1G)
+
+%define PGTBLS_OFFSET(x) ((x) - TopLevelPageDirectory) %define
+PGTBLS_ADDR(x) (ADDR_OF(TopLevelPageDirectory) + (x))
+
+%define PDP(offset) (ADDR_OF(TopLevelPageDirectory) + (offset) + \
+ PAGE_PDP_ATTR)
+
+%define PDP_1G(x) ((x << 30) + PAGE_PDP_1G_ATTR)
+
+ALIGN 16
+
+TopLevelPageDirectory:
+
+ ;
+ ; Top level Page Directory Pointers (1 * 512GB entry)
+ ;
+ DQ PDP(0x1000)
+
+
+ TIMES 0x1000-PGTBLS_OFFSET($) DB 0
+ ;
+ ; Next level Page Directory Pointers (512 * 1GB entries => 512GB)
+ ;
+%assign i 0
+%rep 512
+ DQ PDP_1G(i)
+ %assign i i+1
+%endrep
+
+
+EndOfPageTables:
diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm b/UefiCpuPkg/ResetVector/Vtf0/X64/2MPageTables.asm
similarity index 100%
rename from UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm
rename to UefiCpuPkg/ResetVector/Vtf0/X64/2MPageTables.asm
--
2.32.0.windows.1

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