Re: [RESEND PATCH v2] BaseTools: Add support for RISCV GOT/PLT relocations


Sunil V L <sunilvl@...>
 

Hi,
I just edited the commit message to indicate the module and CC the
maintainers. Could I get the feedback please?
Thanks
Sunil

On Fri, Jun 11, 2021 at 07:35:03PM +0530, Sunil V L wrote:
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3096

This patch adds support for R_RISCV_CALL_PLT and R_RISCV_GOT_HI20
relocations generated by PIE enabled compiler. This also needed
changes to R_RISCV_32 and R_RISCV_64 relocations as explained in
https://github.com/riscv/riscv-gnu-toolchain/issues/905#issuecomment-846682710

Changes in v2:
- Addressed Daniel's comment on formatting

Testing:
1) Debian GCC 8.3.0 and booted sifive_u and QMEU virt models.
2) Debian 10.2.0 and booted QEMU virt model.
3) riscv-gnu-tool chain 9.2 and booted QEMU virt model.

Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>

Acked-by: Abner Chang <abner.chang@hpe.com>
Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Tested-by: <daniel.schaefer@hpe.com>

Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Yuwei Chen <yuwei.chen@intel.com>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
---
BaseTools/Source/C/GenFw/Elf64Convert.c | 44 +++++++++++++++++++++----
1 file changed, 38 insertions(+), 6 deletions(-)

diff --git a/BaseTools/Source/C/GenFw/Elf64Convert.c b/BaseTools/Source/C/GenFw/Elf64Convert.c
index d097db8632..d684318269 100644
--- a/BaseTools/Source/C/GenFw/Elf64Convert.c
+++ b/BaseTools/Source/C/GenFw/Elf64Convert.c
@@ -129,6 +129,8 @@ STATIC UINT32 mDebugOffset;
STATIC UINT8 *mRiscVPass1Targ = NULL;
STATIC Elf_Shdr *mRiscVPass1Sym = NULL;
STATIC Elf64_Half mRiscVPass1SymSecIndex = 0;
+STATIC INT32 mRiscVPass1Offset;
+STATIC INT32 mRiscVPass1GotFixup;

//
// Initialization Function
@@ -479,11 +481,11 @@ WriteSectionRiscV64 (
break;

case R_RISCV_32:
- *(UINT32 *)Targ = (UINT32)((UINT64)(*(UINT32 *)Targ) - SymShdr->sh_addr + mCoffSectionsOffset[Sym->st_shndx]);
+ *(UINT64 *)Targ = Sym->st_value + Rel->r_addend;
break;

case R_RISCV_64:
- *(UINT64 *)Targ = *(UINT64 *)Targ - SymShdr->sh_addr + mCoffSectionsOffset[Sym->st_shndx];
+ *(UINT64 *)Targ = Sym->st_value + Rel->r_addend;
break;

case R_RISCV_HI20:
@@ -533,6 +535,18 @@ WriteSectionRiscV64 (
mRiscVPass1SymSecIndex = 0;
break;

+ case R_RISCV_GOT_HI20:
+ Value = (Sym->st_value - Rel->r_offset);
+ mRiscVPass1Offset = RV_X(Value, 0, 12);
+ Value = RV_X(Value, 12, 20);
+ *(UINT32 *)Targ = (Value << 12) | (RV_X(*(UINT32*)Targ, 0, 12));
+
+ mRiscVPass1Targ = Targ;
+ mRiscVPass1Sym = SymShdr;
+ mRiscVPass1SymSecIndex = Sym->st_shndx;
+ mRiscVPass1GotFixup = 1;
+ break;
+
case R_RISCV_PCREL_HI20:
mRiscVPass1Targ = Targ;
mRiscVPass1Sym = SymShdr;
@@ -545,11 +559,17 @@ WriteSectionRiscV64 (
if (mRiscVPass1Targ != NULL && mRiscVPass1Sym != NULL && mRiscVPass1SymSecIndex != 0) {
int i;
Value2 = (UINT32)(RV_X(*(UINT32 *)mRiscVPass1Targ, 12, 20));
- Value = (UINT32)(RV_X(*(UINT32 *)Targ, 20, 12));
- if(Value & (RISCV_IMM_REACH/2)) {
- Value |= ~(RISCV_IMM_REACH-1);
+
+ if(mRiscVPass1GotFixup) {
+ Value = (UINT32)(mRiscVPass1Offset);
+ } else {
+ Value = (UINT32)(RV_X(*(UINT32 *)Targ, 20, 12));
+ if(Value & (RISCV_IMM_REACH/2)) {
+ Value |= ~(RISCV_IMM_REACH-1);
+ }
}
Value = Value - (UINT32)mRiscVPass1Sym->sh_addr + mCoffSectionsOffset[mRiscVPass1SymSecIndex];
+
if(-2048 > (INT32)Value) {
i = (((INT32)Value * -1) / 4096);
Value2 -= i;
@@ -569,12 +589,21 @@ WriteSectionRiscV64 (
}
}

- *(UINT32 *)Targ = (RV_X(Value, 0, 12) << 20) | (RV_X(*(UINT32*)Targ, 0, 20));
+ if(mRiscVPass1GotFixup) {
+ *(UINT32 *)Targ = (RV_X((UINT32)Value, 0, 12) << 20)
+ | (RV_X(*(UINT32*)Targ, 0, 20));
+ /* Convert LD instruction to ADDI */
+ *(UINT32 *)Targ = ((*(UINT32 *)Targ & ~0x707f) | 0x13);
+ } else {
+ *(UINT32 *)Targ = (RV_X(Value, 0, 12) << 20) | (RV_X(*(UINT32*)Targ, 0, 20));
+ }
*(UINT32 *)mRiscVPass1Targ = (RV_X(Value2, 0, 20)<<12) | (RV_X(*(UINT32 *)mRiscVPass1Targ, 0, 12));
}
mRiscVPass1Sym = NULL;
mRiscVPass1Targ = NULL;
mRiscVPass1SymSecIndex = 0;
+ mRiscVPass1Offset = 0;
+ mRiscVPass1GotFixup = 0;
break;

case R_RISCV_ADD64:
@@ -586,6 +615,7 @@ WriteSectionRiscV64 (
case R_RISCV_GPREL_I:
case R_RISCV_GPREL_S:
case R_RISCV_CALL:
+ case R_RISCV_CALL_PLT:
case R_RISCV_RVC_BRANCH:
case R_RISCV_RVC_JUMP:
case R_RISCV_RELAX:
@@ -1528,6 +1558,7 @@ WriteRelocations64 (
case R_RISCV_GPREL_I:
case R_RISCV_GPREL_S:
case R_RISCV_CALL:
+ case R_RISCV_CALL_PLT:
case R_RISCV_RVC_BRANCH:
case R_RISCV_RVC_JUMP:
case R_RISCV_RELAX:
@@ -1537,6 +1568,7 @@ WriteRelocations64 (
case R_RISCV_SET16:
case R_RISCV_SET32:
case R_RISCV_PCREL_HI20:
+ case R_RISCV_GOT_HI20:
case R_RISCV_PCREL_LO12_I:
break;

--
2.25.1

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