REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3309

Define new element(Hybird) in CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS
(07h) data structure.

Signed-off-by: Jason Lou <yun.lou@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
---
MdePkg/Include/Register/Intel/Cpuid.h | 16 ++++++++++++----
1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/MdePkg/Include/Register/Intel/Cpuid.h b/MdePkg/Include/Registe=
r/Intel/Cpuid.h
index 19af99b6af..25ec65a746 100644
--- a/MdePkg/Include/Register/Intel/Cpuid.h
+++ b/MdePkg/Include/Register/Intel/Cpuid.h
@@ -6,7 +6,7 @@
If a register returned is a single 32-bit value, then a data structure i=
s=0D
not provided for that register.=0D
=0D
- Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>=0D
+ Copyright (c) 2015 - 2021, Intel Corporation. All rights reserved.<BR>=0D
SPDX-License-Identifier: BSD-2-Clause-Patent=0D
=0D
@par Specification Reference:=0D
@@ -1550,9 +1550,17 @@ typedef union {
///=0D
UINT32 AVX512_4FMAPS:1;=0D
///=0D
- /// [Bit 25:4] Reserved.=0D
+ /// [Bit 14:4] Reserved.=0D
///=0D
- UINT32 Reserved2:22;=0D
+ UINT32 Reserved4:11;=0D
+ ///=0D
+ /// [Bit 15] Hybrid. If 1, the processor is identified as a hybrid par=
t.=0D
+ ///=0D
+ UINT32 Hybrid:1;=0D
+ ///=0D
+ /// [Bit 25:16] Reserved.=0D
+ ///=0D
+ UINT32 Reserved5:10;=0D
///=0D
/// [Bit 26] Enumerates support for indirect branch restricted specula=
tion=0D
/// (IBRS) and the indirect branch pre-dictor barrier (IBPB). Processo=
rs=0D
@@ -1581,7 +1589,7 @@ typedef union {
///=0D
/// [Bit 30] Reserved.=0D
///=0D
- UINT32 Reserved3:1;=0D
+ UINT32 Reserved6:1;=0D
///=0D
/// [Bit 31] Enumerates support for Speculative Store Bypass Disable (=
SSBD).=0D
/// Processors that set this bit sup-port the IA32_SPEC_CTRL MSR. They=
allow=0D
--=20
2.28.0.windows.1