[PATCH v2] MinPlatformPkg: Add PcdMicrocodeOffsetInFv


Ni, Ray
 

Add PcdMicrocodeOffsetInFv in MinPlatformPkg.dec and update
SecFspWrapperPlatformSecLib library to use the microcode location
PCDs defined in MinPlatformPkg.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Eric Dong <eric.dong@intel.com>
---
.../SecFspWrapperPlatformSecLib.inf | 8 ++++----
.../SecFspWrapperPlatformSecLib/SecRamInitData.c | 6 +++---
Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec | 10 +++++++++-
3 files changed, 16 insertions(+), 8 deletions(-)

diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapper=
PlatformSecLib/SecFspWrapperPlatformSecLib.inf b/Platform/Intel/MinPlatform=
Pkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSec=
Lib.inf
index 4f3fa9fa34..2e0d67eae4 100644
--- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor=
mSecLib/SecFspWrapperPlatformSecLib.inf
+++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor=
mSecLib/SecFspWrapperPlatformSecLib.inf
@@ -1,7 +1,7 @@
## @file=0D
# Provide FSP wrapper platform sec related function.=0D
#=0D
-# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>=
=0D
+# Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.<BR>=
=0D
#=0D
# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
#=0D
@@ -88,9 +88,9 @@
gMinPlatformPkgTokenSpaceGuid.PcdSecSerialPortDebugEnable ## C=
ONSUMES=0D
=0D
[FixedPcd]=0D
- gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress ## C=
ONSUMES=0D
- gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize ## C=
ONSUMES=0D
- gIntelFsp2WrapperTokenSpaceGuid.PcdFlashMicrocodeOffset ## C=
ONSUMES=0D
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase ## C=
ONSUMES=0D
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize ## C=
ONSUMES=0D
+ gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv ## C=
ONSUMES=0D
gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress ## C=
ONSUMES=0D
gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize ## C=
ONSUMES=0D
gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress ## C=
ONSUMES=0D
diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapper=
PlatformSecLib/SecRamInitData.c b/Platform/Intel/MinPlatformPkg/FspWrapper/=
Library/SecFspWrapperPlatformSecLib/SecRamInitData.c
index b356327b4c..355d1e6509 100644
--- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor=
mSecLib/SecRamInitData.c
+++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor=
mSecLib/SecRamInitData.c
@@ -1,7 +1,7 @@
/** @file=0D
Provide TempRamInitParams data.=0D
=0D
-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>=0D
+Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.<BR>=0D
SPDX-License-Identifier: BSD-2-Clause-Patent=0D
=0D
**/=0D
@@ -24,8 +24,8 @@ GLOBAL_REMOVE_IF_UNREFERENCED CONST FSPT_UPD_CORE_DATA Fs=
ptUpdDataPtr =3D {
}=0D
},=0D
{=0D
- ((UINT32)FixedPcdGet64 (PcdCpuMicrocodePatchAddress) + FixedPcdGet32 (=
PcdFlashMicrocodeOffset)),=0D
- ((UINT32)FixedPcdGet64 (PcdCpuMicrocodePatchRegionSize) - FixedPcdGet3=
2 (PcdFlashMicrocodeOffset)),=0D
+ FixedPcdGet32 (PcdFlashFvMicrocodeBase) + FixedPcdGet32 (PcdMicrocodeO=
ffsetInFv),=0D
+ FixedPcdGet32 (PcdFlashFvMicrocodeSize) - FixedPcdGet32 (PcdMicrocodeO=
ffsetInFv),=0D
0, // Set CodeRegionBase as 0, so that caching will be 4GB-(C=
odeRegionSize > LLCSize ? LLCSize : CodeRegionSize) will be used.=0D
FixedPcdGet32 (PcdFlashCodeCacheSize),=0D
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,=0D
diff --git a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec b/Platform/In=
tel/MinPlatformPkg/MinPlatformPkg.dec
index 2b246cf0ac..28d2b1965e 100644
--- a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec
+++ b/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec
@@ -6,7 +6,7 @@
# INF files to generate AutoGen.c and AutoGen.h files=0D
# for the build infrastructure.=0D
#=0D
-# Copyright (c) 2017 - 2020, Intel Corporation. All rights reserved.<BR>=0D
+# Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.<BR>=0D
#=0D
# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
#=0D
@@ -162,10 +162,18 @@
gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress|0xFF800000|UINT32|=
0x10000001=0D
gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize|0x00800000|UINT32|0x10000=
002=0D
=0D
+ ## Indicates the MMIO base address of the microcode FV in flash.=0D
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase|0xFFE60000|UINT32|=
0x30000004=0D
+=0D
+ ## Indicates the size of the microcode FV in flash.=0D
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize|0x000A0000|UINT32|=
0x30000005=0D
+=0D
+ ## Indicates the offset of the microcode FV relative to the beginning of=
flash.=0D
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset|0x00660000|UINT3=
2|0x30000006=0D
=0D
+ ## Indicates the offset of the actual microcode content relative to the =
beginning of the microcode FV.=0D
+ gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv|0x90|UINT32|0x30000=
007=0D
+=0D
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase|0x00000000|UINT32|=
0x20000004=0D
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize|0x00000000|UINT32|=
0x20000005=0D
gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset|0x00000000|UINT3=
2|0x20000006=0D
--=20
2.27.0.windows.1

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