UefiPayload parse gPldPciRootBridgeInfoGuid Guid Hob to retrieve PCI root b=
ridges
information. gPldPciRootBridgeInfoGuid Guid Hob should be created by Bootlo=
ader.
Cc: Guo Dong <guo.dong@...>
Cc: Benjamin You <benjamin.you@...>
Signed-off-by: Aiden Park <aiden.park@...>
Signed-off-by: Maurice Ma <maurice.ma@...>
Signed-off-by: Zhiguang Liu <zhiguang.liu@...>
---
UefiPayloadPkg/Include/Guid/PldPciRootBridgeInfoHob.h | 54 ++++++=
++++++++++++++++++++++++++++++++++++++++++++++++
UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridge.h | 40 ++++++=
++++++++++++++++++++++++++++++++--
UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c | 41 ++++++=
++++++++++++++++++++++++++++++++---
UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf | 9 ++++++=
++-
UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c | 81 ++++++=
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-
UefiPayloadPkg/UefiPayloadPkg.dec | 11 ++++++=
-----
6 files changed, 224 insertions(+), 12 deletions(-)
diff --git a/UefiPayloadPkg/Include/Guid/PldPciRootBridgeInfoHob.h b/UefiPa=
yloadPkg/Include/Guid/PldPciRootBridgeInfoHob.h
new file mode 100644
index 0000000000..47a9a7aeb2
--- /dev/null
+++ b/UefiPayloadPkg/Include/Guid/PldPciRootBridgeInfoHob.h
@@ -0,0 +1,54 @@
+/** @file=0D
+ This file defines the hob structure for the PCI Root Bridge Info.=0D
+=0D
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>=0D
+ SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+=0D
+**/=0D
+=0D
+#ifndef __PLD_PCI_ROOT_BRIDGE_INFO_HOB_H__=0D
+#define __PLD_PCI_ROOT_BRIDGE_INFO_HOB_H__=0D
+=0D
+#include <IndustryStandard/Pci.h>=0D
+#include <Library/PciHostBridgeLib.h>=0D
+=0D
+///=0D
+/// Payload PCI Root Bridge Information HOB=0D
+///=0D
+typedef struct {=0D
+ UINT32 Segment; ///< Segment number.=0D
+ UINT64 Supports; ///< Supported attribute=
s.=0D
+ ///< Refer to EFI_PCI_AT=
TRIBUTE_xxx used by GetAttributes()=0D
+ ///< and SetAttributes()=
in EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.=0D
+ UINT64 Attributes; ///< Initial attributes.=
=0D
+ ///< Refer to EFI_PCI_AT=
TRIBUTE_xxx used by GetAttributes()=0D
+ ///< and SetAttributes()=
in EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.=0D
+ BOOLEAN DmaAbove4G; ///< DMA above 4GB memor=
y.=0D
+ ///< Set to TRUE when ro=
ot bridge supports DMA above 4GB memory.=0D
+ BOOLEAN NoExtendedConfigSpace; ///< When FALSE, the roo=
t bridge supports=0D
+ ///< Extended (4096-byte=
) Configuration Space.=0D
+ ///< When TRUE, the root=
bridge supports=0D
+ ///< 256-byte Configurat=
ion Space only.=0D
+ BOOLEAN ResourceAssigned; ///< Resource assignment=
status of the root bridge.=0D
+ ///< Set to TRUE if Bus/=
IO/MMIO resources for root bridge have been assigned.=0D
+ UINT64 AllocationAttributes; ///< Allocation attribut=
es.=0D
+ ///< Refer to EFI_PCI_HO=
ST_BRIDGE_COMBINE_MEM_PMEM and=0D
+ ///< EFI_PCI_HOST_BRIDGE=
_MEM64_DECODE used by GetAllocAttributes()=0D
+ ///< in EFI_PCI_HOST_BRI=
DGE_RESOURCE_ALLOCATION_PROTOCOL.=0D
+ PCI_ROOT_BRIDGE_APERTURE Bus; ///< Bus aperture which =
can be used by the root bridge.=0D
+ PCI_ROOT_BRIDGE_APERTURE Io; ///< IO aperture which c=
an be used by the root bridge.=0D
+ PCI_ROOT_BRIDGE_APERTURE Mem; ///< MMIO aperture below=
4GB which can be used by the root bridge.=0D
+ PCI_ROOT_BRIDGE_APERTURE MemAbove4G; ///< MMIO aperture above=
4GB which can be used by the root bridge.=0D
+ PCI_ROOT_BRIDGE_APERTURE PMem; ///< Prefetchable MMIO a=
perture below 4GB which can be used by the root bridge.=0D
+ PCI_ROOT_BRIDGE_APERTURE PMemAbove4G; ///< Prefetchable MMIO a=
perture above 4GB which can be used by the root bridge.=0D
+ UINT32 HID;=0D
+ UINT32 UID;=0D
+} PLD_PCI_ROOT_BRIDGE;=0D
+=0D
+typedef struct {=0D
+ UINT8 Revision;=0D
+ UINT8 Count;=0D
+ PLD_PCI_ROOT_BRIDGE RootBridge[0];=0D
+} PLD_PCI_ROOT_BRIDGE_INFO_HOB;=0D
+=0D
+#endif // __PLD_PCI_ROOT_BRIDGE_INFO_HOB_H__=0D
diff --git a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridge.h b/Uefi=
PayloadPkg/Library/PciHostBridgeLib/PciHostBridge.h
index c2961b3bee..f6cb2a25d9 100644
--- a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridge.h
+++ b/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridge.h
@@ -2,7 +2,7 @@
Header file of PciHostBridgeLib.=0D
=0D
Copyright (C) 2016, Red Hat, Inc.=0D
- Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>=0D
+ Copyright (c) 2016 - 2021, Intel Corporation. All rights reserved.<BR>=0D
=0D
SPDX-License-Identifier: BSD-2-Clause-Patent=0D
=0D
@@ -11,14 +11,38 @@
#ifndef _PCI_HOST_BRIDGE_H=0D
#define _PCI_HOST_BRIDGE_H=0D
=0D
+#include <Guid/PldPciRootBridgeInfoHob.h>=0D
+=0D
typedef struct {=0D
ACPI_HID_DEVICE_PATH AcpiDevicePath;=0D
EFI_DEVICE_PATH_PROTOCOL EndDevicePath;=0D
} CB_PCI_ROOT_BRIDGE_DEVICE_PATH;=0D
=0D
+/**=0D
+ Scan for all root bridges in platform.=0D
+=0D
+ @param[out] NumberOfRootBridges Number of root bridges detected=0D
+=0D
+ @retval Pointer to the allocated PCI_ROOT_BRIDGE structure array.=0D
+**/=0D
PCI_ROOT_BRIDGE *=0D
ScanForRootBridges (=0D
- UINTN *NumberOfRootBridges=0D
+ OUT UINTN *NumberOfRootBridges=0D
+);=0D
+=0D
+/**=0D
+ Scan for all root bridges from PldPciRootBridgeInfoHob=0D
+=0D
+ @param[in] PciRootBridgeInfo Pointer of PLD PCI Root Bridge Info Hob=
=0D
+ @param[out] NumberOfRootBridges Number of root bridges detected=0D
+=0D
+ @retval Pointer to the allocated PCI_ROOT_BRIDGE structure array.=0D
+=0D
+**/=0D
+PCI_ROOT_BRIDGE *=0D
+RetrieveRootBridgeInfoFromHob (=0D
+ IN PLD_PCI_ROOT_BRIDGE_INFO_HOB *PciRootBridgeInfo,=0D
+ OUT UINTN *NumberOfRootBridges=0D
);=0D
=0D
/**=0D
@@ -77,4 +101,16 @@ InitRootBridge (
OUT PCI_ROOT_BRIDGE *RootBus=0D
);=0D
=0D
+/**=0D
+ Initialize DevicePath for a PCI_ROOT_BRIDGE.=0D
+ @param[in] HID HID for device path=0D
+ @param[in] UID UID for device path=0D
+=0D
+ @retval A pointer to the new created device patch.=0D
+**/=0D
+EFI_DEVICE_PATH_PROTOCOL *=0D
+CreateRootBridgeDevicePath (=0D
+ IN UINT32 HID,=0D
+ IN UINT32 UID=0D
+);=0D
#endif=0D
diff --git a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c b/U=
efiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c
index 512c3127cc..8af98dc16a 100644
--- a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c
+++ b/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c
@@ -2,7 +2,7 @@
Library instance of PciHostBridgeLib library class for coreboot.=0D
=0D
Copyright (C) 2016, Red Hat, Inc.=0D
- Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>=0D
+ Copyright (c) 2016 - 2021, Intel Corporation. All rights reserved.<BR>=0D
=0D
SPDX-License-Identifier: BSD-2-Clause-Patent=0D
=0D
@@ -19,6 +19,7 @@
#include <Library/MemoryAllocationLib.h>=0D
#include <Library/PciHostBridgeLib.h>=0D
#include <Library/PciLib.h>=0D
+#include <Library/HobLib.h>=0D
=0D
#include "PciHostBridge.h"=0D
=0D
@@ -48,7 +49,6 @@ CB_PCI_ROOT_BRIDGE_DEVICE_PATH mRootBridgeDevicePathTempl=
ate =3D {
}=0D
};=0D
=0D
-=0D
/**=0D
Initialize a PCI_ROOT_BRIDGE structure.=0D
=0D
@@ -145,6 +145,27 @@ InitRootBridge (
return EFI_SUCCESS;=0D
}=0D
=0D
+/**=0D
+ Initialize DevicePath for a PCI_ROOT_BRIDGE.=0D
+ @param[in] HID HID for device path=0D
+ @param[in] UID UID for device path=0D
+=0D
+ @retval A pointer to the new created device patch.=0D
+**/=0D
+EFI_DEVICE_PATH_PROTOCOL *=0D
+CreateRootBridgeDevicePath (=0D
+ IN UINT32 HID,=0D
+ IN UINT32 UID=0D
+)=0D
+{=0D
+ CB_PCI_ROOT_BRIDGE_DEVICE_PATH *DevicePath;=0D
+ DevicePath =3D AllocateCopyPool (sizeof (mRootBridgeDevicePathTemplate),=
=0D
+ &mRootBridgeDevicePathTemplate);=0D
+ ASSERT (DevicePath !=3D NULL);=0D
+ DevicePath->AcpiDevicePath.HID =3D HID;=0D
+ DevicePath->AcpiDevicePath.UID =3D UID;=0D
+ return (EFI_DEVICE_PATH_PROTOCOL *)DevicePath;=0D
+}=0D
=0D
/**=0D
Return all the root bridge instances in an array.=0D
@@ -161,10 +182,24 @@ PciHostBridgeGetRootBridges (
UINTN *Count=0D
)=0D
{=0D
+ PLD_PCI_ROOT_BRIDGE_INFO_HOB *PciRootBridgeInfo;=0D
+ EFI_HOB_GUID_TYPE *GuidHob;=0D
+ //=0D
+ // Find PLD PCI Root Bridge Info hob=0D
+ //=0D
+ GuidHob =3D GetFirstGuidHob (&gPldPciRootBridgeInfoGuid);=0D
+ if (GuidHob !=3D NULL) {=0D
+ PciRootBridgeInfo =3D (PLD_PCI_ROOT_BRIDGE_INFO_HOB *) GET_GUID_HOB_DA=
TA (GuidHob);=0D
+ //=0D
+ // The count of Root Bridge must be not large than the maximum Root Br=
idge number that the Hob can carry=0D
+ //=0D
+ if (PciRootBridgeInfo->Count <=3D (GuidHob->Header.HobLength - sizeof(=
PLD_PCI_ROOT_BRIDGE_INFO_HOB)) / sizeof(PLD_PCI_ROOT_BRIDGE)) {=0D
+ return RetrieveRootBridgeInfoFromHob (PciRootBridgeInfo, Count);=0D
+ }=0D
+ }=0D
return ScanForRootBridges (Count);=0D
}=0D
=0D
-=0D
/**=0D
Free the root bridge instances array returned from=0D
PciHostBridgeGetRootBridges().=0D
diff --git a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf b=
/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf
index 7896df2416..ba31d718b8 100644
--- a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf
+++ b/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf
@@ -2,7 +2,7 @@
# Library instance of PciHostBridgeLib library class for coreboot.=0D
#=0D
# Copyright (C) 2016, Red Hat, Inc.=0D
-# Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>=
=0D
+# Copyright (c) 2016 - 2021, Intel Corporation. All rights reserved.<BR>=
=0D
#=0D
# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
#=0D
@@ -32,6 +32,7 @@
[Packages]=0D
MdeModulePkg/MdeModulePkg.dec=0D
MdePkg/MdePkg.dec=0D
+ UefiPayloadPkg/UefiPayloadPkg.dec=0D
=0D
[LibraryClasses]=0D
BaseMemoryLib=0D
@@ -39,3 +40,9 @@
DevicePathLib=0D
MemoryAllocationLib=0D
PciLib=0D
+=0D
+[Guids]=0D
+ gPldPciRootBridgeInfoGuid=0D
+=0D
+[Pcd]=0D
+ gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration=0D
diff --git a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c=
b/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c
index fffbf04cad..eb2d54fedc 100644
--- a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c
+++ b/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c
@@ -1,7 +1,7 @@
/** @file=0D
Scan the entire PCI bus for root bridges to support coreboot UEFI payloa=
d.=0D
=0D
- Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>=0D
+ Copyright (c) 2016 - 2021, Intel Corporation. All rights reserved.<BR>=0D
=0D
SPDX-License-Identifier: BSD-2-Clause-Patent=0D
=0D
@@ -582,3 +582,82 @@ ScanForRootBridges (
=0D
return RootBridges;=0D
}=0D
+=0D
+/**=0D
+ Scan for all root bridges from PldPciRootBridgeInfoHob=0D
+=0D
+ @param[in] PciRootBridgeInfo Pointer of PLD PCI Root Bridge Info Hob=
=0D
+ @param[out] NumberOfRootBridges Number of root bridges detected=0D
+=0D
+ @retval Pointer to the allocated PCI_ROOT_BRIDGE structure array.=0D
+=0D
+**/=0D
+PCI_ROOT_BRIDGE *=0D
+RetrieveRootBridgeInfoFromHob (=0D
+ IN PLD_PCI_ROOT_BRIDGE_INFO_HOB *PciRootBridgeInfo,=0D
+ OUT UINTN *NumberOfRootBridges=0D
+)=0D
+{=0D
+ PCI_ROOT_BRIDGE *PciRootBridges;=0D
+ UINTN Size;=0D
+ UINT8 Index;=0D
+ BOOLEAN ResourceAssigned;=0D
+=0D
+ ASSERT (PciRootBridgeInfo !=3D NULL);=0D
+ ASSERT (NumberOfRootBridges !=3D NULL);=0D
+ if (PciRootBridgeInfo =3D=3D NULL) {=0D
+ return NULL;=0D
+ }=0D
+ if (PciRootBridgeInfo->Count =3D=3D 0) {=0D
+ return NULL;=0D
+ }=0D
+ Size =3D PciRootBridgeInfo->Count * sizeof (PCI_ROOT_BRIDGE);=0D
+ PciRootBridges =3D (PCI_ROOT_BRIDGE *) AllocatePool (Size);=0D
+ ASSERT (PciRootBridges !=3D NULL);=0D
+ if (PciRootBridges =3D=3D NULL) {=0D
+ return NULL;=0D
+ }=0D
+ ZeroMem (PciRootBridges, PciRootBridgeInfo->Count * sizeof (PCI_ROOT_BRI=
DGE));=0D
+=0D
+ //=0D
+ // Create all root bridges with PciRootBridgeInfoHob=0D
+ //=0D
+ for (Index =3D 0; Index < PciRootBridgeInfo->Count; Index++) {=0D
+ PciRootBridges[Index].Segment =3D PciRootBridgeInfo->Roo=
tBridge[Index].Segment;=0D
+ PciRootBridges[Index].Supports =3D PciRootBridgeInfo->Roo=
tBridge[Index].Supports;=0D
+ PciRootBridges[Index].Attributes =3D PciRootBridgeInfo->Roo=
tBridge[Index].Attributes;=0D
+ PciRootBridges[Index].DmaAbove4G =3D PciRootBridgeInfo->Roo=
tBridge[Index].DmaAbove4G;=0D
+ PciRootBridges[Index].NoExtendedConfigSpace =3D PciRootBridgeInfo->Roo=
tBridge[Index].NoExtendedConfigSpace;=0D
+ PciRootBridges[Index].ResourceAssigned =3D PciRootBridgeInfo->Roo=
tBridge[Index].ResourceAssigned;=0D
+ PciRootBridges[Index].AllocationAttributes =3D PciRootBridgeInfo->Roo=
tBridge[Index].AllocationAttributes;=0D
+ PciRootBridges[Index].DevicePath =3D CreateRootBridgeDevice=
Path(PciRootBridgeInfo->RootBridge[Index].HID, PciRootBridgeInfo->RootBridg=
e[Index].UID);=0D
+ CopyMem(&PciRootBridges[Index].Bus, &PciRootBridgeInfo->RootBr=
idge[Index].Bus, sizeof(PCI_ROOT_BRIDGE_APERTURE));=0D
+ CopyMem(&PciRootBridges[Index].Io, &PciRootBridgeInfo->RootBr=
idge[Index].Io, sizeof(PCI_ROOT_BRIDGE_APERTURE));=0D
+ CopyMem(&PciRootBridges[Index].Mem, &PciRootBridgeInfo->RootBr=
idge[Index].Mem, sizeof(PCI_ROOT_BRIDGE_APERTURE));=0D
+ CopyMem(&PciRootBridges[Index].MemAbove4G, &PciRootBridgeInfo->RootBr=
idge[Index].MemAbove4G, sizeof(PCI_ROOT_BRIDGE_APERTURE));=0D
+ CopyMem(&PciRootBridges[Index].PMem, &PciRootBridgeInfo->RootBr=
idge[Index].PMem, sizeof(PCI_ROOT_BRIDGE_APERTURE));=0D
+ CopyMem(&PciRootBridges[Index].PMemAbove4G, &PciRootBridgeInfo->RootBr=
idge[Index].PMemAbove4G, sizeof(PCI_ROOT_BRIDGE_APERTURE));=0D
+ }=0D
+=0D
+ *NumberOfRootBridges =3D PciRootBridgeInfo->Count;=0D
+ ResourceAssigned =3D PciRootBridges[0].ResourceAssigned;=0D
+ for (Index =3D 1; Index < PciRootBridgeInfo->Count; Index++) {=0D
+ if (PciRootBridges[Index].ResourceAssigned !=3D ResourceAssigned) {=0D
+ DEBUG ((DEBUG_ERROR, "All root birdges' field ResourceAssigned shoul=
d be the same\n"));=0D
+ return NULL;=0D
+ }=0D
+ }=0D
+=0D
+ //=0D
+ // Now, this library only supports RootBridge that ResourceAssigned is T=
rue=0D
+ //=0D
+ if (ResourceAssigned) {=0D
+ PcdSetBoolS (PcdPciDisableBusEnumeration, TRUE);=0D
+ } else {=0D
+ DEBUG ((DEBUG_ERROR, "There is root bridge whose ResourceAssigned is F=
ALSE\n"));=0D
+ PcdSetBoolS (PcdPciDisableBusEnumeration, FALSE);=0D
+ return NULL;=0D
+ }=0D
+=0D
+ return PciRootBridges;=0D
+}=0D
diff --git a/UefiPayloadPkg/UefiPayloadPkg.dec b/UefiPayloadPkg/UefiPayload=
Pkg.dec
index 99cb3311a6..a655a374e1 100644
--- a/UefiPayloadPkg/UefiPayloadPkg.dec
+++ b/UefiPayloadPkg/UefiPayloadPkg.dec
@@ -3,7 +3,7 @@
#=0D
# Provides drivers and definitions to create uefi payload for bootloaders.=
=0D
#=0D
-# Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.<BR>=0D
+# Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.<BR>=0D
# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
#=0D
##=0D
@@ -29,10 +29,11 @@
#=0D
gBmpImageGuid =3D { 0x878AC2CC, 0x5343, 0x46F2=
, { 0xB5, 0x63, 0x51, 0xF8, 0x9D, 0xAF, 0x56, 0xBA } }=0D
=0D
- gUefiSystemTableInfoGuid =3D {0x16c8a6d0, 0xfe8a, 0x4082, {0xa2, 0x8, 0x=
cf, 0x89, 0xc4, 0x29, 0x4, 0x33}}=0D
- gUefiAcpiBoardInfoGuid =3D {0xad3d31b, 0xb3d8, 0x4506, {0xae, 0x71, 0x=
2e, 0xf1, 0x10, 0x6, 0xd9, 0xf}}=0D
- gUefiSerialPortInfoGuid =3D { 0x6c6872fe, 0x56a9, 0x4403, { 0xbb, 0x98,=
0x95, 0x8d, 0x62, 0xde, 0x87, 0xf1 } }=0D
- gLoaderMemoryMapInfoGuid =3D { 0xa1ff7424, 0x7a1a, 0x478e, { 0xa9, 0xe4,=
0x92, 0xf3, 0x57, 0xd1, 0x28, 0x32 } }=0D
+ gUefiSystemTableInfoGuid =3D { 0x16c8a6d0, 0xfe8a, 0x4082, { 0xa2, 0x08=
, 0xcf, 0x89, 0xc4, 0x29, 0x04, 0x33 }}=0D
+ gUefiAcpiBoardInfoGuid =3D { 0x0ad3d31b, 0xb3d8, 0x4506, { 0xae, 0x71=
, 0x2e, 0xf1, 0x10, 0x06, 0xd9, 0x0f }}=0D
+ gUefiSerialPortInfoGuid =3D { 0x6c6872fe, 0x56a9, 0x4403, { 0xbb, 0x98=
, 0x95, 0x8d, 0x62, 0xde, 0x87, 0xf1 }}=0D
+ gLoaderMemoryMapInfoGuid =3D { 0xa1ff7424, 0x7a1a, 0x478e, { 0xa9, 0xe4=
, 0x92, 0xf3, 0x57, 0xd1, 0x28, 0x32 }}=0D
+ gPldPciRootBridgeInfoGuid =3D { 0xec4ebacb, 0x2638, 0x416e, { 0xbe, 0x80=
, 0xe5, 0xfa, 0x4b, 0x51, 0x19, 0x01 }}=0D
=0D
[Ppis]=0D
gEfiPayLoadHobBasePpiGuid =3D { 0xdbe23aa1, 0xa342, 0x4b97, {0x85, 0xb6,=
0xb2, 0x26, 0xf1, 0x61, 0x73, 0x89} }=0D
--=20
2.30.0.windows.2
