[edk2-platform][PATCH 3/3] Silicon/Qemu: Use PCDs to AcpiTables lib


Tomas Pilar (tpilar)
 

The ACPI Tables providing library AcpiTables.inf uses
a lot of information that is available in the form of PCDs
for differnt platforms.

This patch replaces hardcoded values describing the PCIe,
AHCI, EHCI, and Serial with the appropriate PCDs.

Cc: Leif Lindholm <leif@...>
Cc: Ard Biesheuvel <ard.biesheuvel@...>
Cc: Tanmay Jagdale <tanmay.jagdale@...>
Signed-off-by: Tomas Pilar <tomas@...>
---
.../Qemu/SbsaQemu/AcpiTables/AcpiTables.inf | 29 ++++++++++
Silicon/Qemu/SbsaQemu/AcpiTables/Dbg2.aslc | 6 +-
Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl | 58 ++++++++++---------
Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc | 6 +-
Silicon/Qemu/SbsaQemu/AcpiTables/Spcr.aslc | 2 +-
.../Include/IndustryStandard/SbsaQemuAcpi.h | 6 --
6 files changed, 68 insertions(+), 39 deletions(-)

diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf b/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
index 766e448836..9be34488eb 100644
--- a/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
+++ b/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
@@ -45,3 +45,32 @@
gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId
gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId
gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision
+
+ gArmTokenSpaceGuid.PcdPciBusMin
+ gArmTokenSpaceGuid.PcdPciBusMax
+
+ gArmTokenSpaceGuid.PcdPciIoBase
+ gArmTokenSpaceGuid.PcdPciIoSize
+ gArmTokenSpaceGuid.PcdPciIoTranslation
+ gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciIoLimit
+
+ gArmTokenSpaceGuid.PcdPciMmio32Base
+ gArmTokenSpaceGuid.PcdPciMmio32Size
+ gArmTokenSpaceGuid.PcdPciMmio32Translation
+ gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciMmio32Limit
+
+ gArmTokenSpaceGuid.PcdPciMmio64Base
+ gArmTokenSpaceGuid.PcdPciMmio64Size
+ gArmTokenSpaceGuid.PcdPciMmio64Translation
+ gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciMmio64Limit
+
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
+ gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciExpressBarSize
+ gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciExpressBarLimit
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
+
+ gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformAhciBase
+ gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformAhciSize
+ gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformEhciBase
+ gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformEhciSize
diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Dbg2.aslc b/Silicon/Qemu/SbsaQemu/AcpiTables/Dbg2.aslc
index d74332d359..42777fc554 100644
--- a/Silicon/Qemu/SbsaQemu/AcpiTables/Dbg2.aslc
+++ b/Silicon/Qemu/SbsaQemu/AcpiTables/Dbg2.aslc
@@ -54,9 +54,9 @@ STATIC DBG2_TABLE Dbg2 = {
OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, BaseAddressRegister),
OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, AddressSize)
},
- ARM_GAS32 (SBSAQEMU_UART0_BASE), /* BaseAddressRegister */
- 0x1000, /* AddressSize */
- SBSAQEMU_UART_STR, /* NameSpaceString */
+ ARM_GAS32 (FixedPcdGet32(PcdSerialRegisterBase)), /* BaseAddressRegister */
+ 0x1000, /* AddressSize */
+ SBSAQEMU_UART_STR, /* NameSpaceString */
}
};

diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl b/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl
index f320077c81..e056d6cdb0 100644
--- a/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl
+++ b/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl
@@ -33,7 +33,9 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 1, "LINARO", "SBSAQEMU",
Name (_HID, "ARMH0011")
Name (_UID, Zero)
Name (_CRS, ResourceTemplate () {
- Memory32Fixed (ReadWrite, 0x60000000, 0x00001000)
+ Memory32Fixed (ReadWrite,
+ FixedPcdGet32 (PcdSerialRegisterBase),
+ 0x00001000)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 33 }
})
}
@@ -48,7 +50,9 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 1, "LINARO", "SBSAQEMU",
})
Name (_CCA, 1)
Name (_CRS, ResourceTemplate() {
- Memory32Fixed (ReadWrite, 0x60100000, 0x1000)
+ Memory32Fixed (ReadWrite,
+ FixedPcdGet32 (PcdPlatformAhciBase),
+ FixedPcdGet32 (PcdPlatformAhciSize))
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 42 }
})
}
@@ -60,7 +64,9 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 1, "LINARO", "SBSAQEMU",

Method (_CRS, 0x0, Serialized) {
Name (RBUF, ResourceTemplate() {
- Memory32Fixed (ReadWrite, 0x60110000, 0x00010000)
+ Memory32Fixed (ReadWrite,
+ FixedPcdGet32 (PcdPlatformEhciBase),
+ FixedPcdGet32 (PcdPlatformEhciSize))
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 43 }
})
Return (RBUF)
@@ -157,7 +163,7 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 1, "LINARO", "SBSAQEMU",
Name (_CCA, One) // Initially mark the PCI coherent (for JunoR1)

Method (_CBA, 0, NotSerialized) {
- return (0xf0000000)
+ return (FixedPcdGet32 (PcdPciExpressBaseAddress))
}

LINK_DEVICE(0, GSI0, 0x23)
@@ -335,8 +341,8 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 1, "LINARO", "SBSAQEMU",
ResourceProducer,
MinFixed, MaxFixed, PosDecode,
0, // AddressGranularity
- 0, // AddressMinimum - Minimum Bus Number
- 255, // AddressMaximum - Maximum Bus Number
+ FixedPcdGet32 (PcdPciBusMin), // AddressMinimum - Minimum Bus Number
+ FixedPcdGet32 (PcdPciBusMax), // AddressMaximum - Maximum Bus Number
0, // AddressTranslation - Set to 0
256 // RangeLength - Number of Busses
)
@@ -345,22 +351,22 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 1, "LINARO", "SBSAQEMU",
ResourceProducer, PosDecode,
MinFixed, MaxFixed,
Cacheable, ReadWrite,
- 0x00000000, // Granularity
- 0x80000000, // Min Base Address
- 0xEFFFFFFF, // Max Base Address
- 0x00000000, // Translate
- 0x70000000 // Length
+ 0x00000000, // Granularity
+ FixedPcdGet32 (PcdPciMmio32Base), // Min Base Address
+ FixedPcdGet32 (PcdPciMmio32Limit), // Max Base Address
+ FixedPcdGet32 (PcdPciMmio32Translation), // Translate
+ FixedPcdGet32 (PcdPciMmio32Size) // Length
)

QWordMemory ( // 64-bit BAR Windows
ResourceProducer, PosDecode,
MinFixed, MaxFixed,
Cacheable, ReadWrite,
- 0x00000000, // Granularity
- 0x100000000, // Min Base Address
- 0xFFFFFFFFFF, // Max Base Address
- 0x00000000, // Translate
- 0xFF00000000 // Length
+ 0x00000000, // Granularity
+ FixedPcdGet64 (PcdPciMmio64Base), // Min Base Address
+ FixedPcdGet64 (PcdPciMmio64Limit), // Max Base Address
+ FixedPcdGet64 (PcdPciMmio64Translation), // Translate
+ FixedPcdGet64 (PcdPciMmio64Size) // Length
)

DWordIo ( // IO window
@@ -369,11 +375,11 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 1, "LINARO", "SBSAQEMU",
MaxFixed,
PosDecode,
EntireRange,
- 0x00000000, // Granularity
- 0x00000000, // Min Base Address
- 0x0000ffff, // Max Base Address
- 0x7fff0000, // Translate
- 0x00010000, // Length
+ 0x00000000, // Granularity
+ FixedPcdGet32 (PcdPciIoBase), // Min Base Address
+ FixedPcdGet32 (PcdPciIoLimit), // Max Base Address
+ FixedPcdGet32 (PcdPciIoTranslation), // Translate
+ FixedPcdGet32 (PcdPciIoSize), // Length
,,,TypeTranslation
)
}) // Name(RBUF)
@@ -387,11 +393,11 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 1, "LINARO", "SBSAQEMU",
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
- 0x0000000000000000, // Granularity
- 0x00000000F0000000, // Range Minimum
- 0x00000000FFFFFFFF, // Range Maximum
- 0x0000000000000000, // Translation Offset
- 0x0000000010000000, // Length
+ 0x0000000000000000, // Granularity
+ FixedPcdGet64 (PcdPciExpressBaseAddress), // Range Minimum
+ FixedPcdGet64 (PcdPciExpressBarLimit), // Range Maximum
+ 0x0000000000000000, // Translation Offset
+ FixedPcdGet64 (PcdPciExpressBarSize), // Length
,, , AddressRangeMemory, TypeStatic)
})
}
diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc b/Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc
index 3b617d7036..7a53569faa 100644
--- a/Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc
+++ b/Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc
@@ -27,10 +27,10 @@ EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE Mcfg = {
},
{
{
- SBSAQEMU_PCI_SEG0_CONFIG_BASE,
+ FixedPcdGet32 (PcdPciExpressBaseAddress),
0,
- SBSAQEMU_PCI_SEG0_BUSNUM_MIN,
- SBSAQEMU_PCI_SEG0_BUSNUM_MAX,
+ FixedPcdGet32 (PcdPciBusMin),
+ FixedPcdGet32 (PcdPciBusMax),
EFI_ACPI_RESERVED_DWORD
}
}
diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Spcr.aslc b/Silicon/Qemu/SbsaQemu/AcpiTables/Spcr.aslc
index 6340a401c3..432097307f 100644
--- a/Silicon/Qemu/SbsaQemu/AcpiTables/Spcr.aslc
+++ b/Silicon/Qemu/SbsaQemu/AcpiTables/Spcr.aslc
@@ -25,7 +25,7 @@ STATIC EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spcr = {
32,
0,
EFI_ACPI_6_0_DWORD,
- SBSAQEMU_UART0_BASE
+ FixedPcdGet32 (PcdSerialRegisterBase)
},
EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_GIC,
0, /* Irq */
diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
index f085765d26..4d5b05ba17 100644
--- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
+++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
@@ -37,12 +37,6 @@
SBSAQEMU_MADT_GICR_SIZE /* DiscoveryRangeLength */ \
}

-#define SBSAQEMU_UART0_BASE 0x60000000
-
-#define SBSAQEMU_PCI_SEG0_CONFIG_BASE 0xf0000000
-#define SBSAQEMU_PCI_SEG0_BUSNUM_MIN 0x00
-#define SBSAQEMU_PCI_SEG0_BUSNUM_MAX 0xFF
-
#define SBSAQEMU_ACPI_SCOPE_OP_MAX_LENGTH 5

#define SBSAQEMU_ACPI_SCOPE_NAME { '_', 'S', 'B', '_' }
--
2.25.1

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