[PATCH v2 2/2] UefiPayloadPkg: Scan for Option ROMs


Marcello Sylvester Bauer <marcello.bauer@...>
 

From: Patrick Rudolph <patrick.rudolph@9elements.com>

Install the gPciPlatformProtocol to scan for Option ROMs.

For every device we probe the Option ROM and provide a pointer
to the activated BAR if found.

It's safe to assume that all ROM bars have been enumerated,
reserved in the bridge resources and are disabled by default.

Enabling them and leaving them enabled will do no harm.

Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Marcello Sylvester Bauer <marcello.bauer@9elements.com>
Cc: Patrick Rudolph <patrick.rudolph@9elements.com>
Cc: Christian Walter <christian.walter@9elements.com>
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
---
UefiPayloadPkg/UefiPayloadPkgIa32.dsc | 1 +
UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc | 1 +
UefiPayloadPkg/UefiPayloadPkg.fdf | 1 +
UefiPayloadPkg/PciPlatformDxe/PciPlatformDxe.inf | 46 +++
UefiPayloadPkg/PciPlatformDxe/PciPlatformDxe.h | 19 +
UefiPayloadPkg/PciPlatformDxe/PciPlatformDxe.c | 426 ++++++++++++++++++++
6 files changed, 494 insertions(+)

diff --git a/UefiPayloadPkg/UefiPayloadPkgIa32.dsc b/UefiPayloadPkg/UefiPay=
loadPkgIa32.dsc
index 12d7ffe81416..9f42d2cd6b74 100644
--- a/UefiPayloadPkg/UefiPayloadPkgIa32.dsc
+++ b/UefiPayloadPkg/UefiPayloadPkgIa32.dsc
@@ -513,6 +513,7 @@ [Components.IA32]
MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf=0D
!endif=0D
UefiPayloadPkg/GraphicsOutputDxe/GraphicsOutputDxe.inf=0D
+ UefiPayloadPkg/PciPlatformDxe/PciPlatformDxe.inf=0D
=0D
#------------------------------=0D
# Build the shell=0D
diff --git a/UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc b/UefiPayloadPkg/Uefi=
PayloadPkgIa32X64.dsc
index 9bae1daa09bb..59fc1b79457b 100644
--- a/UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc
+++ b/UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc
@@ -514,6 +514,7 @@ [Components.X64]
MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf=0D
!endif=0D
UefiPayloadPkg/GraphicsOutputDxe/GraphicsOutputDxe.inf=0D
+ UefiPayloadPkg/PciPlatformDxe/PciPlatformDxe.inf=0D
=0D
#------------------------------=0D
# Build the shell=0D
diff --git a/UefiPayloadPkg/UefiPayloadPkg.fdf b/UefiPayloadPkg/UefiPayload=
Pkg.fdf
index 570a8ee7fdc1..9b188724221d 100644
--- a/UefiPayloadPkg/UefiPayloadPkg.fdf
+++ b/UefiPayloadPkg/UefiPayloadPkg.fdf
@@ -151,6 +151,7 @@ [FV.DXEFV]
INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf=0D
!endif=0D
INF UefiPayloadPkg/GraphicsOutputDxe/GraphicsOutputDxe.inf=0D
+INF UefiPayloadPkg/PciPlatformDxe/PciPlatformDxe.inf=0D
=0D
#=0D
# SCSI/ATA/IDE/DISK Support=0D
diff --git a/UefiPayloadPkg/PciPlatformDxe/PciPlatformDxe.inf b/UefiPayload=
Pkg/PciPlatformDxe/PciPlatformDxe.inf
new file mode 100644
index 000000000000..96cedad5afc3
--- /dev/null
+++ b/UefiPayloadPkg/PciPlatformDxe/PciPlatformDxe.inf
@@ -0,0 +1,46 @@
+## @file=0D
+# This driver produces gEfiPciPlatform protocol to load PCI Option ROMs=0D
+#=0D
+# Copyright (c) 2020, 9elements Agency GmbH=0D
+#=0D
+# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+#=0D
+#=0D
+##=0D
+=0D
+[Defines]=0D
+ INF_VERSION =3D 0x00010005=0D
+ BASE_NAME =3D PciPlatformDxe=0D
+ FILE_GUID =3D 86D58F7B-6E7C-401F-BDD4-E32E6D582AAD=
=0D
+ MODULE_TYPE =3D UEFI_DRIVER=0D
+ VERSION_STRING =3D 1.0=0D
+ ENTRY_POINT =3D InstallPciPlatformProtocol=0D
+=0D
+#=0D
+# The following information is for reference only and not required by the =
build tools.=0D
+#=0D
+# VALID_ARCHITECTURES =3D IA32 X64=0D
+#=0D
+=0D
+[Sources.common]=0D
+ PciPlatformDxe.h=0D
+ PciPlatformDxe.c=0D
+=0D
+[Packages]=0D
+ MdePkg/MdePkg.dec=0D
+ MdeModulePkg/MdeModulePkg.dec=0D
+=0D
+[LibraryClasses]=0D
+ UefiDriverEntryPoint=0D
+ UefiBootServicesTableLib=0D
+ DxeServicesTableLib=0D
+ DebugLib=0D
+ MemoryAllocationLib=0D
+ BaseMemoryLib=0D
+ DevicePathLib=0D
+ UefiLib=0D
+ HobLib=0D
+=0D
+[Protocols]=0D
+ gEfiPciPlatformProtocolGuid ## PRODUCES=0D
+ gEfiPciIoProtocolGuid ## COMSUMES=0D
diff --git a/UefiPayloadPkg/PciPlatformDxe/PciPlatformDxe.h b/UefiPayloadPk=
g/PciPlatformDxe/PciPlatformDxe.h
new file mode 100644
index 000000000000..c40518c703f8
--- /dev/null
+++ b/UefiPayloadPkg/PciPlatformDxe/PciPlatformDxe.h
@@ -0,0 +1,19 @@
+/** @file=0D
+ Header file for a PCI platform driver.=0D
+=0D
+Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>=0D
+SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+=0D
+=0D
+**/=0D
+#ifndef _PCI_PLATFORM_DXE_H_=0D
+#define _PCI_PLATFORM_DXE_H_=0D
+#include <PiDxe.h>=0D
+=0D
+#include <IndustryStandard/Pci.h>=0D
+#include <IndustryStandard/Acpi.h>=0D
+#include <IndustryStandard/Pci22.h>=0D
+#include <Protocol/PciIo.h>=0D
+#include <Protocol/PciPlatform.h>=0D
+=0D
+#endif=0D
diff --git a/UefiPayloadPkg/PciPlatformDxe/PciPlatformDxe.c b/UefiPayloadPk=
g/PciPlatformDxe/PciPlatformDxe.c
new file mode 100644
index 000000000000..65a1ba967314
--- /dev/null
+++ b/UefiPayloadPkg/PciPlatformDxe/PciPlatformDxe.c
@@ -0,0 +1,426 @@
+/** @file=0D
+ This driver will probe for the Option Rom and provide a pointer to=0D
+ the activated BAR if found.=0D
+=0D
+Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>=0D
+SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+=0D
+=0D
+**/=0D
+=0D
+#include "PciPlatformDxe.h"=0D
+#include <Bus/Pci/PciBusDxe/PciBus.h>=0D
+#include <Bus/Pci/PciBusDxe/PciOptionRomSupport.h>=0D
+=0D
+//=0D
+// The driver should only start on one graphics controller.=0D
+// So a global flag is used to remember that the driver is already started=
.=0D
+//=0D
+EFI_HANDLE mDriverHandle =3D NULL;=0D
+=0D
+/**=0D
+ The notification from the PCI bus enumerator to the platform that it is=
=0D
+ about to enter a certain phase during the enumeration process.=0D
+=0D
+ @param[in] This The pointer to the EFI_PCI_PLATFORM_PROTOCOL i=
nstance.=0D
+ @param[in] HostBridge The handle of the host bridge controller.=0D
+ @param[in] Phase The phase of the PCI bus enumeration.=0D
+ @param[in] ExecPhase Defines the execution phase of the PCI chipset=
driver.=0D
+=0D
+ @retval EFI_SUCCESS The function completed successfully.=0D
+=0D
+**/=0D
+EFI_STATUS=0D
+EFIAPI=0D
+PciPlatformNotify(=0D
+ IN EFI_PCI_PLATFORM_PROTOCOL *This,=0D
+ IN EFI_HANDLE HostBridge,=0D
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase,=0D
+ IN EFI_PCI_EXECUTION_PHASE ExecPhase=0D
+ )=0D
+{=0D
+ return EFI_SUCCESS;=0D
+}=0D
+=0D
+=0D
+/**=0D
+ The notification from the PCI bus enumerator to the platform for each PC=
I=0D
+ controller at several predefined points during PCI controller initializa=
tion.=0D
+=0D
+ @param[in] This The pointer to the EFI_PCI_PLATFORM_PROTOCOL i=
nstance.=0D
+ @param[in] HostBridge The associated PCI host bridge handle.=0D
+ @param[in] RootBridge The associated PCI root bridge handle.=0D
+ @param[in] PciAddress The address of the PCI device on the PCI bus.=
=0D
+ @param[in] Phase The phase of the PCI controller enumeration.=0D
+ @param[in] ExecPhase Defines the execution phase of the PCI chipset=
driver.=0D
+=0D
+ @retval EFI_SUCCESS The function completed successfully.=0D
+=0D
+**/=0D
+EFI_STATUS=0D
+EFIAPI=0D
+PciPlatformPrepController(=0D
+ IN EFI_PCI_PLATFORM_PROTOCOL *This,=0D
+ IN EFI_HANDLE HostBridge,=0D
+ IN EFI_HANDLE RootBridge,=0D
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress,=0D
+ IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase,=0D
+ IN EFI_PCI_EXECUTION_PHASE ExecPhase=0D
+ )=0D
+{=0D
+ return EFI_SUCCESS;=0D
+}=0D
+=0D
+/**=0D
+ Gets the PCI device's option ROM.=0D
+=0D
+ @param[in] This The pointer to the EFI_PCI_PLATFORM_PROTOCOL ins=
tance.=0D
+ @param[in] PciHandle The handle of the PCI device.=0D
+ @param[out] RomImage If the call succeeds, the pointer to the pointer=
to the option ROM image.=0D
+ Otherwise, this field is undefined. The memory f=
or RomImage is allocated=0D
+ by EFI_PCI_PLATFORM_PROTOCOL.GetPciRom() using t=
he EFI Boot Service AllocatePool().=0D
+ It is the caller's responsibility to free the me=
mory using the EFI Boot Service=0D
+ FreePool(), when the caller is done with the opt=
ion ROM.=0D
+ @param[out] RomSize If the call succeeds, a pointer to the size of t=
he option ROM size. Otherwise,=0D
+ this field is undefined.=0D
+=0D
+ @retval EFI_SUCCESS The option ROM was available for this dev=
ice and loaded into memory.=0D
+ @retval EFI_NOT_FOUND No option ROM was available for this devi=
ce.=0D
+ @retval EFI_OUT_OF_RESOURCES No memory was available to load the optio=
n ROM.=0D
+ @retval EFI_DEVICE_ERROR An error occurred in obtaining the option=
ROM.=0D
+=0D
+**/=0D
+EFI_STATUS=0D
+EFIAPI=0D
+PciGetPciRom (=0D
+ IN CONST EFI_PCI_PLATFORM_PROTOCOL *This,=0D
+ IN EFI_HANDLE PciHandle,=0D
+ OUT VOID **RomImage,=0D
+ OUT UINTN *RomSize=0D
+ )=0D
+{=0D
+ EFI_STATUS Status;=0D
+ IN EFI_PCI_IO_PROTOCOL *PciIo;=0D
+ UINTN PciSegment;=0D
+ UINTN PciBus;=0D
+ UINTN PciDevice;=0D
+ UINTN PciFunction;=0D
+ UINTN RomBarIndex;=0D
+ UINT32 Buffer;=0D
+ UINT32 AllOnes;=0D
+ PCI_IO_DEVICE *PciIoDevice;=0D
+ UINT8 Indicator;=0D
+ UINT16 OffsetPcir;=0D
+ UINT32 RomBarOffset;=0D
+ UINT32 RomBar;=0D
+ BOOLEAN FirstCheck;=0D
+ PCI_EXPANSION_ROM_HEADER *RomHeader;=0D
+ PCI_DATA_STRUCTURE *RomPcir;=0D
+ UINT64 RomImageSize;=0D
+ UINT32 LegacyImageLength;=0D
+ UINT8 *RomInMemory;=0D
+ UINT8 CodeType;=0D
+=0D
+ if (!RomImage || !RomSize) {=0D
+ return EFI_INVALID_PARAMETER;=0D
+ }=0D
+=0D
+ *RomImage =3D NULL;=0D
+ *RomSize =3D 0;=0D
+=0D
+ Status =3D gBS->HandleProtocol (=0D
+ PciHandle,=0D
+ &gEfiPciIoProtocolGuid,=0D
+ (VOID **) &PciIo=0D
+ );=0D
+ if (EFI_ERROR (Status)) {=0D
+ DEBUG ((DEBUG_INFO, "%a: Failed to open gEfiPciIoProtocolGuid\n", __=
FUNCTION__));=0D
+=0D
+ return EFI_UNSUPPORTED;=0D
+ }=0D
+ PciIoDevice =3D PCI_IO_DEVICE_FROM_PCI_IO_THIS (PciIo);=0D
+=0D
+ //=0D
+ // Get the location of the PCI device=0D
+ //=0D
+ PciIo->GetLocation (=0D
+ PciIo,=0D
+ &PciSegment,=0D
+ &PciBus,=0D
+ &PciDevice,=0D
+ &PciFunction=0D
+ );=0D
+=0D
+ DEBUG ((DEBUG_INFO, "%a: Searching Option ROM on device:\n", __FUNCTION_=
_));=0D
+ DEBUG ((DEBUG_INFO, " PciSegment - %02x\n", PciSegment));=0D
+ DEBUG ((DEBUG_INFO, " PciBus - %02x\n", PciBus));=0D
+ DEBUG ((DEBUG_INFO, " PciDevice - %02x\n", PciDevice));=0D
+ DEBUG ((DEBUG_INFO, " PciFunction - %02x\n", PciFunction));=0D
+=0D
+ //=0D
+ // Offset is 0x30 if is not ppb=0D
+ //=0D
+ RomBarIndex =3D PCI_EXPANSION_ROM_BASE;=0D
+=0D
+ if (IS_PCI_BRIDGE (&PciIoDevice->Pci)) {=0D
+ //=0D
+ // If is ppb, 0x38=0D
+ //=0D
+ RomBarIndex =3D PCI_BRIDGE_ROMBAR;=0D
+ }=0D
+=0D
+ //=0D
+ // Backup BAR=0D
+ //=0D
+ Status =3D PciIo->Pci.Read (=0D
+ PciIo,=0D
+ EfiPciWidthUint32,=0D
+ RomBarIndex,=0D
+ 1,=0D
+ &Buffer=0D
+ );=0D
+ if (EFI_ERROR (Status)) {=0D
+ goto CloseAndReturn;=0D
+ return Status;=0D
+ }=0D
+=0D
+ //=0D
+ // The bit0 is 0 to prevent the enabling of the Rom address decoder=0D
+ //=0D
+ AllOnes =3D 0xfffffffe;=0D
+=0D
+ Status =3D PciIo->Pci.Write (=0D
+ PciIo,=0D
+ EfiPciWidthUint32,=0D
+ RomBarIndex,=0D
+ 1,=0D
+ &AllOnes=0D
+ );=0D
+ if (EFI_ERROR (Status)) {=0D
+ goto CloseAndReturn;=0D
+ }=0D
+=0D
+ //=0D
+ // Read back=0D
+ //=0D
+ Status =3D PciIo->Pci.Read(=0D
+ PciIo,=0D
+ EfiPciWidthUint32,=0D
+ RomBarIndex,=0D
+ 1,=0D
+ &AllOnes=0D
+ );=0D
+ if (EFI_ERROR (Status)) {=0D
+ goto CloseAndReturn;=0D
+ }=0D
+=0D
+ //=0D
+ // Bits [1, 10] are reserved=0D
+ //=0D
+ AllOnes &=3D 0xFFFFF800;=0D
+ if ((AllOnes =3D=3D 0) || (AllOnes =3D=3D 0xFFFFF800)) {=0D
+ DEBUG ((DEBUG_INFO, "%a: No Option ROM found\n", __FUNCTION__));=0D
+ return EFI_NOT_FOUND;=0D
+ }=0D
+=0D
+ *RomSize =3D (~AllOnes) + 1;=0D
+=0D
+ DEBUG ((DEBUG_INFO, "%a: Option ROM with size %d\n", __FUNCTION__, *RomS=
ize));=0D
+=0D
+ //=0D
+ // Restore BAR and enable it=0D
+ //=0D
+ Buffer |=3D 1;=0D
+ Status =3D PciIo->Pci.Write (=0D
+ PciIo,=0D
+ EfiPciWidthUint32,=0D
+ RomBarIndex,=0D
+ 1,=0D
+ &Buffer=0D
+ );=0D
+ if (EFI_ERROR (Status)) {=0D
+ goto CloseAndReturn;=0D
+ }=0D
+=0D
+ //=0D
+ // Allocate memory for Rom header and PCIR=0D
+ //=0D
+ RomHeader =3D AllocatePool (sizeof (PCI_EXPANSION_ROM_HEADER));=0D
+ if (RomHeader =3D=3D NULL) {=0D
+ Status =3D EFI_OUT_OF_RESOURCES;=0D
+ goto CloseAndReturn;=0D
+ }=0D
+=0D
+ RomPcir =3D AllocatePool (sizeof (PCI_DATA_STRUCTURE));=0D
+ if (RomPcir =3D=3D NULL) {=0D
+ FreePool (RomHeader);=0D
+ Status =3D EFI_OUT_OF_RESOURCES;=0D
+ goto CloseAndReturn;=0D
+ }=0D
+=0D
+ // FIXME: Use gEfiPciRootBridgeIoProtocolGuid=0D
+ RomBar =3D (UINT32) Buffer &~1;=0D
+=0D
+ RomBarOffset =3D RomBar;=0D
+ FirstCheck =3D TRUE;=0D
+ LegacyImageLength =3D 0;=0D
+ RomImageSize =3D 0;=0D
+=0D
+ do {=0D
+ // FIXME: Use gEfiPciRootBridgeIoProtocolGuid=0D
+ CopyMem(RomHeader, (VOID *)(UINTN)RomBarOffset, sizeof (PCI_EXPANSION_=
ROM_HEADER));=0D
+=0D
+ DEBUG ((DEBUG_INFO, "%a: RomHeader->Signature %x\n", __FUNCTION__, Rom=
Header->Signature));=0D
+=0D
+ if (RomHeader->Signature !=3D PCI_EXPANSION_ROM_HEADER_SIGNATURE) {=0D
+=0D
+ RomBarOffset =3D RomBarOffset + 512;=0D
+ if (FirstCheck) {=0D
+ break;=0D
+ } else {=0D
+ RomImageSize =3D RomImageSize + 512;=0D
+ continue;=0D
+ }=0D
+ }=0D
+=0D
+ FirstCheck =3D FALSE;=0D
+ OffsetPcir =3D RomHeader->PcirOffset;=0D
+ //=0D
+ // If the pointer to the PCI Data Structure is invalid, no further ima=
ges can be located.=0D
+ // The PCI Data Structure must be DWORD aligned.=0D
+ //=0D
+ if (OffsetPcir =3D=3D 0 ||=0D
+ (OffsetPcir & 3) !=3D 0 ||=0D
+ RomImageSize + OffsetPcir + sizeof (PCI_DATA_STRUCTURE) > *RomSize=
) {=0D
+ break;=0D
+ }=0D
+ // FIXME: Use gEfiPciRootBridgeIoProtocolGuid=0D
+ CopyMem(RomPcir, (VOID *)(UINTN)RomBarOffset + OffsetPcir, sizeof (PCI=
_DATA_STRUCTURE));=0D
+=0D
+ DEBUG ((DEBUG_INFO, "%a: RomPcir->Signature %x\n", __FUNCTION__, RomPc=
ir->Signature));=0D
+=0D
+ //=0D
+ // If a valid signature is not present in the PCI Data Structure, no f=
urther images can be located.=0D
+ //=0D
+ if (RomPcir->Signature !=3D PCI_DATA_STRUCTURE_SIGNATURE) {=0D
+ break;=0D
+ }=0D
+ if (RomImageSize + RomPcir->ImageLength * 512 > *RomSize) {=0D
+ break;=0D
+ }=0D
+ if (RomPcir->CodeType =3D=3D PCI_CODE_TYPE_PCAT_IMAGE) {=0D
+ CodeType =3D PCI_CODE_TYPE_PCAT_IMAGE;=0D
+ LegacyImageLength =3D ((UINT32)((EFI_LEGACY_EXPANSION_ROM_HEADER *)R=
omHeader)->Size512) * 512;=0D
+ }=0D
+ Indicator =3D RomPcir->Indicator;=0D
+ RomImageSize =3D RomImageSize + RomPcir->ImageLength * 512;=0D
+ RomBarOffset =3D RomBarOffset + RomPcir->ImageLength * 512;=0D
+ } while (((Indicator & 0x80) =3D=3D 0x00) && ((RomBarOffset - RomBar) < =
*RomSize));=0D
+=0D
+ //=0D
+ // Some Legacy Cards do not report the correct ImageLength so used the m=
aximum=0D
+ // of the legacy length and the PCIR Image Length=0D
+ //=0D
+ if (CodeType =3D=3D PCI_CODE_TYPE_PCAT_IMAGE) {=0D
+ RomImageSize =3D MAX (RomImageSize, LegacyImageLength);=0D
+ }=0D
+=0D
+ if (RomImageSize > 0) {=0D
+ // FIXME: Use gEfiPciRootBridgeIoProtocolGuid=0D
+ RomInMemory =3D (VOID *)(UINTN)RomBar;=0D
+ }=0D
+=0D
+ //=0D
+ // Free allocated memory=0D
+ //=0D
+ FreePool (RomHeader);=0D
+ FreePool (RomPcir);=0D
+=0D
+ if (RomImageSize > 0) {=0D
+ *RomImage =3D RomInMemory;=0D
+ *RomSize =3D RomImageSize;=0D
+ DEBUG ((DEBUG_INFO, "%a: Found Option ROM at %p, length 0x%x\n", __FUN=
CTION__,=0D
+ RomInMemory, RomImageSize));=0D
+=0D
+ Status =3D EFI_SUCCESS;=0D
+ } else {=0D
+ Status =3D EFI_NOT_FOUND;=0D
+ }=0D
+=0D
+CloseAndReturn:=0D
+ //=0D
+ // Close the I/O Abstraction(s) used to perform the supported test=0D
+ //=0D
+ gBS->CloseProtocol (=0D
+ PciHandle,=0D
+ &gEfiPciIoProtocolGuid,=0D
+ PciIo,=0D
+ PciHandle=0D
+ );=0D
+=0D
+ return Status;=0D
+}=0D
+=0D
+/**=0D
+ Retrieves the platform policy regarding enumeration.=0D
+=0D
+ The GetPlatformPolicy() function retrieves the platform policy regarding=
PCI=0D
+ enumeration. The PCI bus driver and the PCI Host Bridge Resource Allocat=
ion Protocol=0D
+ driver can call this member function to retrieve the policy.=0D
+=0D
+ @param[in] This The pointer to the EFI_PCI_PLATFORM_PROTOCOL ins=
tance.=0D
+ @param[out] PciPolicy The platform policy with respect to VGA and ISA =
aliasing.=0D
+=0D
+ @retval EFI_SUCCESS The function completed successfully.=0D
+ @retval EFI_INVALID_PARAMETER PciPolicy is NULL.=0D
+=0D
+**/=0D
+EFI_STATUS=0D
+EFIAPI=0D
+PciGetPlatformPolicy (=0D
+ IN CONST EFI_PCI_PLATFORM_PROTOCOL *This,=0D
+ OUT EFI_PCI_PLATFORM_POLICY *PciPolicy=0D
+ )=0D
+{=0D
+ if (PciPolicy =3D=3D NULL)=0D
+ return EFI_INVALID_PARAMETER;=0D
+=0D
+ *PciPolicy =3D 0;=0D
+=0D
+ return EFI_SUCCESS;=0D
+}=0D
+=0D
+EFI_PCI_PLATFORM_PROTOCOL mPciPlatformProtocol =3D {=0D
+ PciPlatformNotify,=0D
+ PciPlatformPrepController,=0D
+ PciGetPlatformPolicy,=0D
+ PciGetPciRom,=0D
+};=0D
+=0D
+/**=0D
+ The Entry Point for Option ROM driver.=0D
+=0D
+ It installs DriverBinding.=0D
+=0D
+ @retval EFI_SUCCESS The entry point is executed successfully.=0D
+ @retval other Some error occurs when executing this entry po=
int.=0D
+=0D
+**/=0D
+EFI_STATUS=0D
+EFIAPI=0D
+InstallPciPlatformProtocol (=0D
+ IN EFI_HANDLE ImageHandle,=0D
+ IN EFI_SYSTEM_TABLE *SystemTable=0D
+ )=0D
+{=0D
+ EFI_STATUS Status;=0D
+=0D
+ Status =3D gBS->InstallProtocolInterface (=0D
+ &mDriverHandle,=0D
+ &gEfiPciPlatformProtocolGuid,=0D
+ EFI_NATIVE_INTERFACE,=0D
+ &mPciPlatformProtocol=0D
+ );=0D
+=0D
+ return Status;=0D
+}=0D
--=20
2.28.0

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