[PATCH 1/1] Add BhyvePkg, to support the bhyve hypervisor
|
Rebecca Cran
BhyvePkg supports the bhyve hypervisor, which is a hypervisor/virtual
machine manager available on FreeBSD, macOS and Illumos. Signed-off-by: Rebecca Cran <rebecca@...> --- OvmfPkg/Bhyve/AcpiPlatformDxe/AcpiPlatform.c | 251 +++ OvmfPkg/Bhyve/AcpiPlatformDxe/AcpiPlatform.h | 77 + .../Bhyve/AcpiPlatformDxe/AcpiPlatformDxe.inf | 65 + OvmfPkg/Bhyve/AcpiPlatformDxe/Bhyve.c | 132 ++ OvmfPkg/Bhyve/AcpiPlatformDxe/EntryPoint.c | 90 + OvmfPkg/Bhyve/AcpiPlatformDxe/PciDecoding.c | 192 ++ OvmfPkg/Bhyve/AcpiTables/AcpiTables.inf | 39 + OvmfPkg/Bhyve/AcpiTables/Dsdt.asl | 1140 +++++++++++ OvmfPkg/Bhyve/AcpiTables/Facp.aslc | 76 + OvmfPkg/Bhyve/AcpiTables/Facs.aslc | 80 + OvmfPkg/Bhyve/AcpiTables/Hpet.aslc | 72 + OvmfPkg/Bhyve/AcpiTables/Madt.aslc | 145 ++ OvmfPkg/Bhyve/AcpiTables/Mcfg.aslc | 57 + OvmfPkg/Bhyve/AcpiTables/Platform.h | 72 + OvmfPkg/Bhyve/AcpiTables/Spcr.aslc | 63 + OvmfPkg/Bhyve/AcpiTables/Ssdt.asl | 15 + OvmfPkg/Bhyve/BhyvePkg.dec | 171 ++ OvmfPkg/Bhyve/BhyvePkgDefines.fdf.inc | 85 + OvmfPkg/Bhyve/BhyvePkgX64.dsc | 847 +++++++++ OvmfPkg/Bhyve/BhyvePkgX64.fdf | 490 +++++ OvmfPkg/Bhyve/BhyveRfbDxe/BhyveRfbDxe.inf | 68 + OvmfPkg/Bhyve/BhyveRfbDxe/ComponentName.c | 201 ++ OvmfPkg/Bhyve/BhyveRfbDxe/Gop.h | 149 ++ OvmfPkg/Bhyve/BhyveRfbDxe/GopDriver.c | 543 ++++++ OvmfPkg/Bhyve/BhyveRfbDxe/GopScreen.c | 393 ++++ OvmfPkg/Bhyve/BhyveRfbDxe/VbeShim.asm | 342 ++++ OvmfPkg/Bhyve/BhyveRfbDxe/VbeShim.c | 259 +++ OvmfPkg/Bhyve/BhyveRfbDxe/VbeShim.h | 912 +++++++++ OvmfPkg/Bhyve/BhyveRfbDxe/VbeShim.sh | 80 + OvmfPkg/Bhyve/FvmainCompactScratchEnd.fdf.inc | 65 + OvmfPkg/Bhyve/Include/Library/BhyveFwCtlLib.h | 47 + .../Library/BhyveFwCtlLib/BhyveFwCtlLib.c | 426 +++++ .../Library/BhyveFwCtlLib/BhyveFwCtlLib.inf | 41 + .../PlatformBootManagerLib/BdsPlatform.c | 1660 +++++++++++++++++ .../PlatformBootManagerLib/BdsPlatform.h | 190 ++ .../PlatformBootManagerLib.inf | 75 + .../PlatformBootManagerLib/PlatformData.c | 171 ++ OvmfPkg/Bhyve/License.txt | 68 + OvmfPkg/Bhyve/PlatformPei/AmdSev.c | 106 ++ OvmfPkg/Bhyve/PlatformPei/ClearCache.c | 111 ++ OvmfPkg/Bhyve/PlatformPei/Cmos.c | 58 + OvmfPkg/Bhyve/PlatformPei/Cmos.h | 50 + OvmfPkg/Bhyve/PlatformPei/FeatureControl.c | 21 + OvmfPkg/Bhyve/PlatformPei/Fv.c | 94 + OvmfPkg/Bhyve/PlatformPei/MemDetect.c | 627 +++++++ OvmfPkg/Bhyve/PlatformPei/Platform.c | 607 ++++++ OvmfPkg/Bhyve/PlatformPei/Platform.h | 137 ++ OvmfPkg/Bhyve/PlatformPei/PlatformPei.inf | 113 ++ OvmfPkg/Bhyve/SmbiosPlatformDxe/Bhyve.c | 43 + .../SmbiosPlatformDxe/SmbiosPlatformDxe.c | 245 +++ .../SmbiosPlatformDxe/SmbiosPlatformDxe.h | 52 + .../SmbiosPlatformDxe/SmbiosPlatformDxe.inf | 55 + OvmfPkg/Bhyve/VarStore.fdf.inc | 115 ++ 53 files changed, 12283 insertions(+) create mode 100644 OvmfPkg/Bhyve/AcpiPlatformDxe/AcpiPlatform.c create mode 100644 OvmfPkg/Bhyve/AcpiPlatformDxe/AcpiPlatform.h create mode 100644 OvmfPkg/Bhyve/AcpiPlatformDxe/AcpiPlatformDxe.inf create mode 100644 OvmfPkg/Bhyve/AcpiPlatformDxe/Bhyve.c create mode 100644 OvmfPkg/Bhyve/AcpiPlatformDxe/EntryPoint.c create mode 100644 OvmfPkg/Bhyve/AcpiPlatformDxe/PciDecoding.c create mode 100644 OvmfPkg/Bhyve/AcpiTables/AcpiTables.inf create mode 100644 OvmfPkg/Bhyve/AcpiTables/Dsdt.asl create mode 100644 OvmfPkg/Bhyve/AcpiTables/Facp.aslc create mode 100644 OvmfPkg/Bhyve/AcpiTables/Facs.aslc create mode 100644 OvmfPkg/Bhyve/AcpiTables/Hpet.aslc create mode 100644 OvmfPkg/Bhyve/AcpiTables/Madt.aslc create mode 100644 OvmfPkg/Bhyve/AcpiTables/Mcfg.aslc create mode 100644 OvmfPkg/Bhyve/AcpiTables/Platform.h create mode 100644 OvmfPkg/Bhyve/AcpiTables/Spcr.aslc create mode 100644 OvmfPkg/Bhyve/AcpiTables/Ssdt.asl create mode 100644 OvmfPkg/Bhyve/BhyvePkg.dec create mode 100644 OvmfPkg/Bhyve/BhyvePkgDefines.fdf.inc create mode 100644 OvmfPkg/Bhyve/BhyvePkgX64.dsc create mode 100644 OvmfPkg/Bhyve/BhyvePkgX64.fdf create mode 100644 OvmfPkg/Bhyve/BhyveRfbDxe/BhyveRfbDxe.inf create mode 100644 OvmfPkg/Bhyve/BhyveRfbDxe/ComponentName.c create mode 100644 OvmfPkg/Bhyve/BhyveRfbDxe/Gop.h create mode 100644 OvmfPkg/Bhyve/BhyveRfbDxe/GopDriver.c create mode 100644 OvmfPkg/Bhyve/BhyveRfbDxe/GopScreen.c create mode 100644 OvmfPkg/Bhyve/BhyveRfbDxe/VbeShim.asm create mode 100644 OvmfPkg/Bhyve/BhyveRfbDxe/VbeShim.c create mode 100644 OvmfPkg/Bhyve/BhyveRfbDxe/VbeShim.h create mode 100644 OvmfPkg/Bhyve/BhyveRfbDxe/VbeShim.sh create mode 100644 OvmfPkg/Bhyve/FvmainCompactScratchEnd.fdf.inc create mode 100644 OvmfPkg/Bhyve/Include/Library/BhyveFwCtlLib.h create mode 100644 OvmfPkg/Bhyve/Library/BhyveFwCtlLib/BhyveFwCtlLib.c create mode 100644 OvmfPkg/Bhyve/Library/BhyveFwCtlLib/BhyveFwCtlLib.inf create mode 100644 OvmfPkg/Bhyve/Library/PlatformBootManagerLib/BdsPlatfor= m.c create mode 100644 OvmfPkg/Bhyve/Library/PlatformBootManagerLib/BdsPlatfor= m.h create mode 100644 OvmfPkg/Bhyve/Library/PlatformBootManagerLib/PlatformBo= otManagerLib.inf create mode 100644 OvmfPkg/Bhyve/Library/PlatformBootManagerLib/PlatformDa= ta.c create mode 100644 OvmfPkg/Bhyve/License.txt create mode 100644 OvmfPkg/Bhyve/PlatformPei/AmdSev.c create mode 100644 OvmfPkg/Bhyve/PlatformPei/ClearCache.c create mode 100644 OvmfPkg/Bhyve/PlatformPei/Cmos.c create mode 100644 OvmfPkg/Bhyve/PlatformPei/Cmos.h create mode 100644 OvmfPkg/Bhyve/PlatformPei/FeatureControl.c create mode 100644 OvmfPkg/Bhyve/PlatformPei/Fv.c create mode 100644 OvmfPkg/Bhyve/PlatformPei/MemDetect.c create mode 100644 OvmfPkg/Bhyve/PlatformPei/Platform.c create mode 100644 OvmfPkg/Bhyve/PlatformPei/Platform.h create mode 100644 OvmfPkg/Bhyve/PlatformPei/PlatformPei.inf create mode 100644 OvmfPkg/Bhyve/SmbiosPlatformDxe/Bhyve.c create mode 100644 OvmfPkg/Bhyve/SmbiosPlatformDxe/SmbiosPlatformDxe.c create mode 100644 OvmfPkg/Bhyve/SmbiosPlatformDxe/SmbiosPlatformDxe.h create mode 100644 OvmfPkg/Bhyve/SmbiosPlatformDxe/SmbiosPlatformDxe.inf create mode 100644 OvmfPkg/Bhyve/VarStore.fdf.inc diff --git a/OvmfPkg/Bhyve/AcpiPlatformDxe/AcpiPlatform.c b/OvmfPkg/Bhyve/A= cpiPlatformDxe/AcpiPlatform.c new file mode 100644 index 0000000000..31bbf6c474 --- /dev/null +++ b/OvmfPkg/Bhyve/AcpiPlatformDxe/AcpiPlatform.c @@ -0,0 +1,251 @@ +/** @file=0D + OVMF ACPI Platform Driver=0D +=0D + Copyright (c) 2020, Rebecca Cran <rebecca@...>=0D + Copyright (c) 2008 - 2012, Intel Corporation. All rights reserved.<BR>=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include "AcpiPlatform.h"=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +InstallAcpiTable (=0D + IN EFI_ACPI_TABLE_PROTOCOL *AcpiProtocol,=0D + IN VOID *AcpiTableBuffer,=0D + IN UINTN AcpiTableBufferSize,=0D + OUT UINTN *TableKey=0D + )=0D +{=0D + return AcpiProtocol->InstallAcpiTable (=0D + AcpiProtocol,=0D + AcpiTableBuffer,=0D + AcpiTableBufferSize,=0D + TableKey=0D + );=0D +}=0D +=0D +=0D +/**=0D + Locate the first instance of a protocol. If the protocol requested is a= n=0D + FV protocol, then it will return the first FV that contains the ACPI tab= le=0D + storage file.=0D +=0D + @param Instance Return pointer to the first instance of the protoc= ol=0D +=0D + @return EFI_SUCCESS The function completed successfully.=0D + @return EFI_NOT_FOUND The protocol could not be located.=0D + @return EFI_OUT_OF_RESOURCES There are not enough resources to find the= protocol.=0D +=0D +**/=0D +EFI_STATUS=0D +LocateFvInstanceWithTables (=0D + OUT EFI_FIRMWARE_VOLUME2_PROTOCOL **Instance=0D + )=0D +{=0D + EFI_STATUS Status;=0D + EFI_HANDLE *HandleBuffer;=0D + UINTN NumberOfHandles;=0D + EFI_FV_FILETYPE FileType;=0D + UINT32 FvStatus;=0D + EFI_FV_FILE_ATTRIBUTES Attributes;=0D + UINTN Size;=0D + UINTN Index;=0D + EFI_FIRMWARE_VOLUME2_PROTOCOL *FvInstance;=0D +=0D + FvStatus =3D 0;=0D +=0D + //=0D + // Locate protocol.=0D + //=0D + Status =3D gBS->LocateHandleBuffer (=0D + ByProtocol,=0D + &gEfiFirmwareVolume2ProtocolGuid,=0D + NULL,=0D + &NumberOfHandles,=0D + &HandleBuffer=0D + );=0D + if (EFI_ERROR (Status)) {=0D + //=0D + // Defined errors at this time are not found and out of resources.=0D + //=0D + return Status;=0D + }=0D +=0D + //=0D + // Looking for FV with ACPI storage file=0D + //=0D + for (Index =3D 0; Index < NumberOfHandles; Index++) {=0D + //=0D + // Get the protocol on this handle=0D + // This should not fail because of LocateHandleBuffer=0D + //=0D + Status =3D gBS->HandleProtocol (=0D + HandleBuffer[Index],=0D + &gEfiFirmwareVolume2ProtocolGuid,=0D + (VOID**) &FvInstance=0D + );=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + //=0D + // See if it has the ACPI storage file=0D + //=0D + Status =3D FvInstance->ReadFile (=0D + FvInstance,=0D + (EFI_GUID*)PcdGetPtr (PcdAcpiTableStorageFile),= =0D + NULL,=0D + &Size,=0D + &FileType,=0D + &Attributes,=0D + &FvStatus=0D + );=0D +=0D + //=0D + // If we found it, then we are done=0D + //=0D + if (Status =3D=3D EFI_SUCCESS) {=0D + *Instance =3D FvInstance;=0D + break;=0D + }=0D + }=0D +=0D + //=0D + // Our exit status is determined by the success of the previous operatio= ns=0D + // If the protocol was found, Instance already points to it.=0D + //=0D +=0D + //=0D + // Free any allocated buffers=0D + //=0D + gBS->FreePool (HandleBuffer);=0D +=0D + return Status;=0D +}=0D +=0D +=0D +/**=0D + Find ACPI tables in an FV and install them.=0D +=0D + This is now a fall-back path. Normally, we will search for tables provid= ed=0D + by the VMM first.=0D +=0D + If that fails, we use this function to load the ACPI tables from an FV. = The=0D + sources for the FV based tables is located under OvmfPkg/AcpiTables.=0D +=0D + @param AcpiTable Protocol instance pointer=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +InstallOvmfFvTables (=0D + IN EFI_ACPI_TABLE_PROTOCOL *AcpiTable=0D + )=0D +{=0D + EFI_STATUS Status;=0D + EFI_FIRMWARE_VOLUME2_PROTOCOL *FwVol;=0D + INTN Instance;=0D + EFI_ACPI_COMMON_HEADER *CurrentTable;=0D + UINTN TableHandle;=0D + UINT32 FvStatus;=0D + UINTN TableSize;=0D + UINTN Size;=0D + EFI_ACPI_TABLE_INSTALL_ACPI_TABLE TableInstallFunction;=0D +=0D + Instance =3D 0;=0D + CurrentTable =3D NULL;=0D + TableHandle =3D 0;=0D +=0D + TableInstallFunction =3D BhyveInstallAcpiTable;=0D +=0D + //=0D + // set FwVol (and use an ASSERT() below) to suppress incorrect=0D + // compiler/analyzer warnings=0D + //=0D + FwVol =3D NULL;=0D + //=0D + // Locate the firmware volume protocol=0D + //=0D + Status =3D LocateFvInstanceWithTables (&FwVol);=0D + if (EFI_ERROR (Status)) {=0D + return EFI_ABORTED;=0D + }=0D + ASSERT (FwVol !=3D NULL);=0D +=0D + //=0D + // Read tables from the storage file.=0D + //=0D + while (Status =3D=3D EFI_SUCCESS) {=0D +=0D + Status =3D FwVol->ReadSection (=0D + FwVol,=0D + (EFI_GUID*)PcdGetPtr (PcdAcpiTableStorageFile),=0D + EFI_SECTION_RAW,=0D + Instance,=0D + (VOID**) &CurrentTable,=0D + &Size,=0D + &FvStatus=0D + );=0D + if (!EFI_ERROR (Status)) {=0D + //=0D + // Add the table=0D + //=0D + TableHandle =3D 0;=0D +=0D + TableSize =3D ((EFI_ACPI_DESCRIPTION_HEADER *) CurrentTable)->Length= ;=0D + ASSERT (Size >=3D TableSize);=0D +=0D + //=0D + // Install ACPI table=0D + //=0D + Status =3D TableInstallFunction (=0D + AcpiTable,=0D + CurrentTable,=0D + TableSize,=0D + &TableHandle=0D + );=0D +=0D + //=0D + // Free memory allocated by ReadSection=0D + //=0D + gBS->FreePool (CurrentTable);=0D +=0D + if (EFI_ERROR (Status)) {=0D + return EFI_ABORTED;=0D + }=0D +=0D + //=0D + // Increment the instance=0D + //=0D + Instance++;=0D + CurrentTable =3D NULL;=0D + }=0D + }=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D +/**=0D + Effective entrypoint of Acpi Platform driver.=0D +=0D + @param ImageHandle=0D + @param SystemTable=0D +=0D + @return EFI_SUCCESS=0D + @return EFI_LOAD_ERROR=0D + @return EFI_OUT_OF_RESOURCES=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +InstallAcpiTables (=0D + IN EFI_ACPI_TABLE_PROTOCOL *AcpiTable=0D + )=0D +{=0D + EFI_STATUS Status;=0D +=0D + Status =3D InstallOvmfFvTables (AcpiTable);=0D +=0D + return Status;=0D +}=0D +=0D diff --git a/OvmfPkg/Bhyve/AcpiPlatformDxe/AcpiPlatform.h b/OvmfPkg/Bhyve/A= cpiPlatformDxe/AcpiPlatform.h new file mode 100644 index 0000000000..d30cd11a1d --- /dev/null +++ b/OvmfPkg/Bhyve/AcpiPlatformDxe/AcpiPlatform.h @@ -0,0 +1,77 @@ +/** @file=0D + Sample ACPI Platform Driver=0D +=0D + Copyright (c) 2020, Rebecca Cran <rebecca@...>=0D + Copyright (c) 2008 - 2012, Intel Corporation. All rights reserved.<BR>=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#ifndef _ACPI_PLATFORM_H_INCLUDED_=0D +#define _ACPI_PLATFORM_H_INCLUDED_=0D +=0D +#include <PiDxe.h>=0D +=0D +#include <Protocol/AcpiTable.h>=0D +#include <Protocol/FirmwareVolume2.h>=0D +#include <Protocol/PciIo.h>=0D +=0D +#include <Library/BaseLib.h>=0D +#include <Library/UefiBootServicesTableLib.h>=0D +#include <Library/DebugLib.h>=0D +#include <Library/PcdLib.h>=0D +#include <Library/XenPlatformLib.h>=0D +=0D +#include <IndustryStandard/Acpi.h>=0D +=0D +typedef struct {=0D + EFI_PCI_IO_PROTOCOL *PciIo;=0D + UINT64 PciAttributes;=0D +} ORIGINAL_ATTRIBUTES;=0D +=0D +typedef struct S3_CONTEXT S3_CONTEXT;=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +InstallAcpiTable (=0D + IN EFI_ACPI_TABLE_PROTOCOL *AcpiProtocol,=0D + IN VOID *AcpiTableBuffer,=0D + IN UINTN AcpiTableBufferSize,=0D + OUT UINTN *TableKey=0D + );=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +BhyveInstallAcpiTable(=0D + IN EFI_ACPI_TABLE_PROTOCOL *AcpiProtocol,=0D + IN VOID *AcpiTableBuffer,=0D + IN UINTN AcpiTableBufferSize,=0D + OUT UINTN *TableKey=0D + );=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +InstallXenTables (=0D + IN EFI_ACPI_TABLE_PROTOCOL *AcpiProtocol=0D + );=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +InstallAcpiTables (=0D + IN EFI_ACPI_TABLE_PROTOCOL *AcpiTable=0D + );=0D +=0D +VOID=0D +EnablePciDecoding (=0D + OUT ORIGINAL_ATTRIBUTES **OriginalAttributes,=0D + OUT UINTN *Count=0D + );=0D +=0D +VOID=0D +RestorePciDecoding (=0D + IN ORIGINAL_ATTRIBUTES *OriginalAttributes,=0D + IN UINTN Count=0D + );=0D +=0D +#endif=0D +=0D diff --git a/OvmfPkg/Bhyve/AcpiPlatformDxe/AcpiPlatformDxe.inf b/OvmfPkg/Bh= yve/AcpiPlatformDxe/AcpiPlatformDxe.inf new file mode 100644 index 0000000000..bf0f4877f0 --- /dev/null +++ b/OvmfPkg/Bhyve/AcpiPlatformDxe/AcpiPlatformDxe.inf @@ -0,0 +1,65 @@ +## @file=0D +# OVMF ACPI Platform Driver=0D +#=0D +# Copyright (c) 2020, Rebecca Cran <rebecca@...>=0D +# Copyright (c) 2008 - 2018, Intel Corporation. All rights reserved.<BR>= =0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +##=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010005=0D + BASE_NAME =3D AcpiPlatform=0D + FILE_GUID =3D D5F92408-BAB5-44CA-8A60-C212F01D7E9D= =0D + MODULE_TYPE =3D DXE_DRIVER=0D + VERSION_STRING =3D 1.0=0D + ENTRY_POINT =3D AcpiPlatformEntryPoint=0D +=0D +#=0D +# The following information is for reference only and not required by the = build tools.=0D +#=0D +# VALID_ARCHITECTURES =3D IA32 X64 EBC=0D +#=0D +=0D +[Sources]=0D + AcpiPlatform.c=0D + AcpiPlatform.h=0D + EntryPoint.c=0D + PciDecoding.c=0D + Bhyve.c=0D +=0D +[Packages]=0D + MdePkg/MdePkg.dec=0D + MdeModulePkg/MdeModulePkg.dec=0D + OvmfPkg/Bhyve/BhyvePkg.dec=0D + UefiCpuPkg/UefiCpuPkg.dec=0D +=0D +[LibraryClasses]=0D + UefiLib=0D + PcdLib=0D + BaseMemoryLib=0D + DebugLib=0D + UefiBootServicesTableLib=0D + UefiDriverEntryPoint=0D + BhyveFwCtlLib=0D + MemoryAllocationLib=0D + BaseLib=0D + DxeServicesTableLib=0D + OrderedCollectionLib=0D +=0D +[Protocols]=0D + gEfiAcpiTableProtocolGuid # PROTOCOL ALWAYS_CONSUMED= =0D + gEfiFirmwareVolume2ProtocolGuid # PROTOCOL SOMETIMES_CONSU= MED=0D + gEfiPciIoProtocolGuid # PROTOCOL SOMETIMES_CONSU= MED=0D +=0D +[Guids]=0D + gRootBridgesConnectedEventGroupGuid=0D +=0D +[Pcd]=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiTableStorageFile=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration=0D + gUefiCpuPkgTokenSpaceGuid.PcdCpuLocalApicBaseAddress=0D + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFdBaseAddress=0D +=0D +[Depex]=0D + gEfiAcpiTableProtocolGuid=0D diff --git a/OvmfPkg/Bhyve/AcpiPlatformDxe/Bhyve.c b/OvmfPkg/Bhyve/AcpiPlat= formDxe/Bhyve.c new file mode 100644 index 0000000000..6d42264b65 --- /dev/null +++ b/OvmfPkg/Bhyve/AcpiPlatformDxe/Bhyve.c @@ -0,0 +1,132 @@ +/*=0D + * Copyright (c) 2020, Rebecca Cran <rebecca@...>=0D + * Copyright (c) 2008 - 2012, Intel Corporation. All rights reserved.<BR>= =0D + * Copyright (C) 2012, Red Hat, Inc.=0D + * Copyright (c) 2014, Pluribus Networks, Inc.=0D + *=0D + * SPDX-License-Identifier: BSD-2-Clause-Patent=0D + */=0D +#include "AcpiPlatform.h"=0D +=0D +#include <Library/BaseMemoryLib.h>=0D +#include <Library/MemoryAllocationLib.h>=0D +#include <Library/BhyveFwCtlLib.h>=0D +=0D +STATIC=0D +EFI_STATUS=0D +EFIAPI=0D +BhyveInstallAcpiMadtTable (=0D + IN EFI_ACPI_TABLE_PROTOCOL *AcpiProtocol,=0D + IN VOID *AcpiTableBuffer,=0D + IN UINTN AcpiTableBufferSize,=0D + OUT UINTN *TableKey=0D + )=0D +{=0D + UINT32 CpuCount;=0D + UINTN cSize;=0D + UINTN NewBufferSize;=0D + EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER *Madt;=0D + EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC_STRUCTURE *LocalApic;=0D + EFI_ACPI_1_0_IO_APIC_STRUCTURE *IoApic;=0D + EFI_ACPI_1_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE *Iso;=0D + VOID *Ptr;=0D + UINTN Loop;=0D + EFI_STATUS Status;=0D +=0D + ASSERT (AcpiTableBufferSize >=3D sizeof (EFI_ACPI_DESCRIPTION_HEADER));= =0D +=0D + // Query the host for the number of vCPUs=0D + CpuCount =3D 0;=0D + cSize =3D sizeof(CpuCount);=0D + if (BhyveFwCtlGet ("hw.ncpu", &CpuCount, &cSize) =3D=3D RETURN_SUCCESS) = {=0D + DEBUG ((DEBUG_INFO, "Retrieved CpuCount %d\n", CpuCount));=0D + ASSERT (CpuCount >=3D 1);=0D + } else {=0D + DEBUG ((DEBUG_INFO, "CpuCount retrieval error\n"));=0D + CpuCount =3D 1;=0D + }=0D +=0D + NewBufferSize =3D 1 * sizeof (*Madt) +=0D + CpuCount * sizeof (*LocalApic) +=0D + 1 * sizeof (*IoApic) +=0D + 1 * sizeof (*Iso);=0D +=0D + Madt =3D AllocatePool (NewBufferSize);=0D + if (Madt =3D=3D NULL) {=0D + return EFI_OUT_OF_RESOURCES;=0D + }=0D +=0D + CopyMem (&(Madt->Header), AcpiTableBuffer, sizeof (EFI_ACPI_DESCRIPTION_= HEADER));=0D + Madt->Header.Length =3D (UINT32) NewBufferSize;=0D + Madt->LocalApicAddress =3D 0xFEE00000;=0D + Madt->Flags =3D EFI_ACPI_1_0_PCAT_COMPAT;=0D + Ptr =3D Madt + 1;=0D +=0D + LocalApic =3D Ptr;=0D + for (Loop =3D 0; Loop < CpuCount; ++Loop) {=0D + LocalApic->Type =3D EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC;=0D + LocalApic->Length =3D sizeof (*LocalApic);=0D + LocalApic->AcpiProcessorId =3D (UINT8) Loop;=0D + LocalApic->ApicId =3D (UINT8) Loop;=0D + LocalApic->Flags =3D 1; // enabled=0D + ++LocalApic;=0D + }=0D + Ptr =3D LocalApic;=0D +=0D + IoApic =3D Ptr;=0D + IoApic->Type =3D EFI_ACPI_1_0_IO_APIC;=0D + IoApic->Length =3D sizeof (*IoApic);=0D + IoApic->IoApicId =3D (UINT8) CpuCount;=0D + IoApic->Reserved =3D EFI_ACPI_RESERVED_BYTE;=0D + IoApic->IoApicAddress =3D 0xFEC00000;=0D + IoApic->SystemVectorBase =3D 0x00000000;=0D + Ptr =3D IoApic + 1;=0D +=0D + //=0D + // IRQ0 (8254 Timer) =3D> IRQ2 (PIC) Interrupt Source Override Structure= =0D + //=0D + Iso =3D Ptr;=0D + Iso->Type =3D EFI_ACPI_1_0_INTERRUPT_SOURCE_OVERR= IDE;=0D + Iso->Length =3D sizeof (*Iso);=0D + Iso->Bus =3D 0x00; // ISA=0D + Iso->Source =3D 0x00; // IRQ0=0D + Iso->GlobalSystemInterruptVector =3D 0x00000002;=0D + Iso->Flags =3D 0x0000; // Conforms to specs of the= bus=0D + Ptr =3D Iso + 1;=0D +=0D + ASSERT ((UINTN) ((UINT8 *)Ptr - (UINT8 *)Madt) =3D=3D NewBufferSize);=0D + Status =3D InstallAcpiTable (AcpiProtocol, Madt, NewBufferSize, TableKey= );=0D +=0D + FreePool (Madt);=0D +=0D + return Status;=0D +}=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +BhyveInstallAcpiTable (=0D + IN EFI_ACPI_TABLE_PROTOCOL *AcpiProtocol,=0D + IN VOID *AcpiTableBuffer,=0D + IN UINTN AcpiTableBufferSize,=0D + OUT UINTN *TableKey=0D + )=0D +{=0D + EFI_ACPI_DESCRIPTION_HEADER *Hdr;=0D + EFI_ACPI_TABLE_INSTALL_ACPI_TABLE TableInstallFunction;=0D +=0D + Hdr =3D (EFI_ACPI_DESCRIPTION_HEADER*) AcpiTableBuffer;=0D + switch (Hdr->Signature) {=0D + case EFI_ACPI_1_0_APIC_SIGNATURE:=0D + TableInstallFunction =3D BhyveInstallAcpiMadtTable;=0D + break;=0D + default:=0D + TableInstallFunction =3D InstallAcpiTable;=0D + }=0D +=0D + return TableInstallFunction (=0D + AcpiProtocol,=0D + AcpiTableBuffer,=0D + AcpiTableBufferSize,=0D + TableKey=0D + );=0D +}=0D diff --git a/OvmfPkg/Bhyve/AcpiPlatformDxe/EntryPoint.c b/OvmfPkg/Bhyve/Acp= iPlatformDxe/EntryPoint.c new file mode 100644 index 0000000000..f66f892911 --- /dev/null +++ b/OvmfPkg/Bhyve/AcpiPlatformDxe/EntryPoint.c @@ -0,0 +1,90 @@ +/** @file=0D + Entry point of OVMF ACPI Platform Driver=0D +=0D + Copyright (C) 2015, Red Hat, Inc.=0D + Copyright (c) 2008 - 2015, Intel Corporation. All rights reserved.<BR>=0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include <Guid/RootBridgesConnectedEventGroup.h>=0D +#include "AcpiPlatform.h"=0D +=0D +STATIC=0D +EFI_ACPI_TABLE_PROTOCOL *=0D +FindAcpiTableProtocol (=0D + VOID=0D + )=0D +{=0D + EFI_STATUS Status;=0D + EFI_ACPI_TABLE_PROTOCOL *AcpiTable;=0D +=0D + Status =3D gBS->LocateProtocol (=0D + &gEfiAcpiTableProtocolGuid,=0D + NULL,=0D + (VOID**)&AcpiTable=0D + );=0D + ASSERT_EFI_ERROR (Status);=0D + return AcpiTable;=0D +}=0D +=0D +=0D +STATIC=0D +VOID=0D +EFIAPI=0D +OnRootBridgesConnected (=0D + IN EFI_EVENT Event,=0D + IN VOID *Context=0D + )=0D +{=0D + EFI_STATUS Status;=0D +=0D + DEBUG ((DEBUG_INFO,=0D + "%a: root bridges have been connected, installing ACPI tables\n",=0D + __FUNCTION__));=0D + Status =3D InstallAcpiTables (FindAcpiTableProtocol ());=0D + if (EFI_ERROR (Status)) {=0D + DEBUG ((DEBUG_ERROR, "%a: InstallAcpiTables: %r\n", __FUNCTION__, Stat= us));=0D + }=0D + gBS->CloseEvent (Event);=0D +}=0D +=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +AcpiPlatformEntryPoint (=0D + IN EFI_HANDLE ImageHandle,=0D + IN EFI_SYSTEM_TABLE *SystemTable=0D + )=0D +{=0D + EFI_STATUS Status;=0D + EFI_EVENT RootBridgesConnected;=0D +=0D + //=0D + // If the platform doesn't support PCI, or PCI enumeration has been disa= bled,=0D + // install the tables at once, and let the entry point's return code ref= lect=0D + // the full functionality.=0D + //=0D + if (PcdGetBool (PcdPciDisableBusEnumeration)) {=0D + DEBUG ((DEBUG_INFO, "%a: PCI or its enumeration disabled, installing "= =0D + "ACPI tables\n", __FUNCTION__));=0D + return InstallAcpiTables (FindAcpiTableProtocol ());=0D + }=0D +=0D + //=0D + // Otherwise, delay installing the ACPI tables until root bridges are=0D + // connected. The entry point's return status will only reflect the call= back=0D + // setup. (Note that we're a DXE_DRIVER; our entry point function is inv= oked=0D + // strictly before BDS is entered and can connect the root bridges.)=0D + //=0D + Status =3D gBS->CreateEventEx (EVT_NOTIFY_SIGNAL, TPL_CALLBACK,=0D + OnRootBridgesConnected, NULL /* Context */,=0D + &gRootBridgesConnectedEventGroupGuid, &RootBridgesConnec= ted);=0D + if (!EFI_ERROR (Status)) {=0D + DEBUG ((DEBUG_INFO,=0D + "%a: waiting for root bridges to be connected, registered callback\n= ",=0D + __FUNCTION__));=0D + }=0D +=0D + return Status;=0D +}=0D diff --git a/OvmfPkg/Bhyve/AcpiPlatformDxe/PciDecoding.c b/OvmfPkg/Bhyve/Ac= piPlatformDxe/PciDecoding.c new file mode 100644 index 0000000000..73894106c9 --- /dev/null +++ b/OvmfPkg/Bhyve/AcpiPlatformDxe/PciDecoding.c @@ -0,0 +1,192 @@ +/** @file=0D + Temporarily enable IO and MMIO decoding for all PCI devices while QEMU=0D + regenerates the ACPI tables.=0D +=0D + Copyright (C) 2016, Red Hat, Inc.=0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include <Library/MemoryAllocationLib.h>=0D +=0D +#include "AcpiPlatform.h"=0D +=0D +=0D +/**=0D + Collect all PciIo protocol instances in the system. Save their original= =0D + attributes, and enable IO and MMIO decoding for each.=0D +=0D + This is a best effort function; it doesn't return status codes. Its=0D + caller is supposed to proceed even if this function fails.=0D +=0D + @param[out] OriginalAttributes On output, a dynamically allocated array= of=0D + ORIGINAL_ATTRIBUTES elements. The array = lists=0D + the PciIo protocol instances found in th= e=0D + system at the time of the call, plus the= =0D + original PCI attributes for each.=0D +=0D + Before returning, the function enables I= O and=0D + MMIO decoding for each PciIo instance it= =0D + finds.=0D +=0D + On error, or when no such instances are= =0D + found, OriginalAttributes is set to NULL= .=0D +=0D + @param[out] Count On output, the number of elements in=0D + OriginalAttributes. On error it is set t= o=0D + zero.=0D +**/=0D +VOID=0D +EnablePciDecoding (=0D + OUT ORIGINAL_ATTRIBUTES **OriginalAttributes,=0D + OUT UINTN *Count=0D + )=0D +{=0D + EFI_STATUS Status;=0D + UINTN NoHandles;=0D + EFI_HANDLE *Handles;=0D + ORIGINAL_ATTRIBUTES *OrigAttrs;=0D + UINTN Idx;=0D +=0D + *OriginalAttributes =3D NULL;=0D + *Count =3D 0;=0D +=0D + if (PcdGetBool (PcdPciDisableBusEnumeration)) {=0D + //=0D + // The platform downloads ACPI tables from QEMU in general, but there = are=0D + // no root bridges in this execution. We're done.=0D + //=0D + return;=0D + }=0D +=0D + Status =3D gBS->LocateHandleBuffer (ByProtocol, &gEfiPciIoProtocolGuid,= =0D + NULL /* SearchKey */, &NoHandles, &Handles);=0D + if (Status =3D=3D EFI_NOT_FOUND) {=0D + //=0D + // No PCI devices were found on either of the root bridges. We're done= .=0D + //=0D + return;=0D + }=0D +=0D + if (EFI_ERROR (Status)) {=0D + DEBUG ((DEBUG_WARN, "%a: LocateHandleBuffer(): %r\n", __FUNCTION__,=0D + Status));=0D + return;=0D + }=0D +=0D + OrigAttrs =3D AllocatePool (NoHandles * sizeof *OrigAttrs);=0D + if (OrigAttrs =3D=3D NULL) {=0D + DEBUG ((DEBUG_WARN, "%a: AllocatePool(): out of resources\n",=0D + __FUNCTION__));=0D + goto FreeHandles;=0D + }=0D +=0D + for (Idx =3D 0; Idx < NoHandles; ++Idx) {=0D + EFI_PCI_IO_PROTOCOL *PciIo;=0D + UINT64 Attributes;=0D +=0D + //=0D + // Look up PciIo on the handle and stash it=0D + //=0D + Status =3D gBS->HandleProtocol (Handles[Idx], &gEfiPciIoProtocolGuid,= =0D + (VOID**)&PciIo);=0D + ASSERT_EFI_ERROR (Status);=0D + OrigAttrs[Idx].PciIo =3D PciIo;=0D +=0D + //=0D + // Stash the current attributes=0D + //=0D + Status =3D PciIo->Attributes (PciIo, EfiPciIoAttributeOperationGet, 0,= =0D + &OrigAttrs[Idx].PciAttributes);=0D + if (EFI_ERROR (Status)) {=0D + DEBUG ((DEBUG_WARN, "%a: EfiPciIoAttributeOperationGet: %r\n",=0D + __FUNCTION__, Status));=0D + goto RestoreAttributes;=0D + }=0D +=0D + //=0D + // Retrieve supported attributes=0D + //=0D + Status =3D PciIo->Attributes (PciIo, EfiPciIoAttributeOperationSupport= ed, 0,=0D + &Attributes);=0D + if (EFI_ERROR (Status)) {=0D + DEBUG ((DEBUG_WARN, "%a: EfiPciIoAttributeOperationSupported: %r\n",= =0D + __FUNCTION__, Status));=0D + goto RestoreAttributes;=0D + }=0D +=0D + //=0D + // Enable IO and MMIO decoding=0D + //=0D + Attributes &=3D EFI_PCI_IO_ATTRIBUTE_IO | EFI_PCI_IO_ATTRIBUTE_MEMORY;= =0D + Status =3D PciIo->Attributes (PciIo, EfiPciIoAttributeOperationEnable,= =0D + Attributes, NULL);=0D + if (EFI_ERROR (Status)) {=0D + DEBUG ((DEBUG_WARN, "%a: EfiPciIoAttributeOperationEnable: %r\n",=0D + __FUNCTION__, Status));=0D + goto RestoreAttributes;=0D + }=0D + }=0D +=0D + //=0D + // Success=0D + //=0D + FreePool (Handles);=0D + *OriginalAttributes =3D OrigAttrs;=0D + *Count =3D NoHandles;=0D + return;=0D +=0D +RestoreAttributes:=0D + while (Idx > 0) {=0D + --Idx;=0D + OrigAttrs[Idx].PciIo->Attributes (OrigAttrs[Idx].PciIo,=0D + EfiPciIoAttributeOperationSet,=0D + OrigAttrs[Idx].PciAttributes,=0D + NULL=0D + );=0D + }=0D + FreePool (OrigAttrs);=0D +=0D +FreeHandles:=0D + FreePool (Handles);=0D +}=0D +=0D +=0D +/**=0D + Restore the original PCI attributes saved with EnablePciDecoding().=0D +=0D + @param[in] OriginalAttributes The array allocated and populated by=0D + EnablePciDecoding(). This parameter may b= e=0D + NULL. If OriginalAttributes is NULL, then= the=0D + function is a no-op; otherwise the PciIo= =0D + attributes will be restored, and the=0D + OriginalAttributes array will be freed.=0D +=0D + @param[in] Count The Count value stored by EnablePciDecodi= ng(),=0D + the number of elements in OriginalAttribu= tes.=0D + Count may be zero if and only if=0D + OriginalAttributes is NULL.=0D +**/=0D +VOID=0D +RestorePciDecoding (=0D + IN ORIGINAL_ATTRIBUTES *OriginalAttributes,=0D + IN UINTN Count=0D + )=0D +{=0D + UINTN Idx;=0D +=0D + ASSERT ((OriginalAttributes =3D=3D NULL) =3D=3D (Count =3D=3D 0));=0D + if (OriginalAttributes =3D=3D NULL) {=0D + return;=0D + }=0D +=0D + for (Idx =3D 0; Idx < Count; ++Idx) {=0D + OriginalAttributes[Idx].PciIo->Attributes (=0D + OriginalAttributes[Idx].PciIo,=0D + EfiPciIoAttributeOperationSet,=0D + OriginalAttributes[Idx].PciAttributes= ,=0D + NULL=0D + );=0D + }=0D + FreePool (OriginalAttributes);=0D +}=0D diff --git a/OvmfPkg/Bhyve/AcpiTables/AcpiTables.inf b/OvmfPkg/Bhyve/AcpiTa= bles/AcpiTables.inf new file mode 100644 index 0000000000..18a9e2aa78 --- /dev/null +++ b/OvmfPkg/Bhyve/AcpiTables/AcpiTables.inf @@ -0,0 +1,39 @@ +## @file=0D +# Component description file for PlatformAcpiTables module.=0D +#=0D +# ACPI table data and ASL sources required to boot the platform.=0D +#=0D +# Copyright (c) 2020, Rebecca Cran <rebecca@...>=0D +# Copyright (c) 2008 - 2018, Intel Corporation. All rights reserved.<BR>= =0D +# Copyright (c) 2014, Pluribus Networks, Inc.=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010005=0D + BASE_NAME =3D PlatformAcpiTables=0D + FILE_GUID =3D 7E374E25-8E01-4FEE-87F2-390C23C606CD= =0D + MODULE_TYPE =3D USER_DEFINED=0D + VERSION_STRING =3D 1.0=0D +=0D +#=0D +# The following information is for reference only and not required by the = build tools.=0D +#=0D +# VALID_ARCHITECTURES =3D IA32 X64 EBC=0D +#=0D +=0D +[Sources]=0D + Platform.h=0D + Madt.aslc=0D + Facp.aslc=0D + Facs.aslc=0D + Dsdt.asl=0D + Hpet.aslc=0D + Spcr.aslc=0D + Mcfg.aslc=0D +=0D +[Packages]=0D + MdePkg/MdePkg.dec=0D +=0D diff --git a/OvmfPkg/Bhyve/AcpiTables/Dsdt.asl b/OvmfPkg/Bhyve/AcpiTables/D= sdt.asl new file mode 100644 index 0000000000..17e2cf69e6 --- /dev/null +++ b/OvmfPkg/Bhyve/AcpiTables/Dsdt.asl @@ -0,0 +1,1140 @@ +/*=0D + * Copyright (c) 2020, Rebecca Cran <rebecca@...>=0D + *=0D + * SPDX-License-Identifier: BSD-2-Clause-Patent=0D + */=0D +=0D +/*=0D + * Intel ACPI Component Architecture=0D + * AML Disassembler version 20100528=0D + *=0D + * Disassembly of DSDT.dat, Sat Apr 18 15:41:05 2015=0D + *=0D + *=0D + * Original Table Header:=0D + * Signature "DSDT"=0D + * Length 0x000008FA (2298)=0D + * Revision 0x02=0D + * Checksum 0xC4=0D + * OEM ID "BHYVE "=0D + * OEM Table ID "BVDSDT "=0D + * OEM Revision 0x00000001 (1)=0D + * Compiler ID "INTL"=0D + * Compiler Version 0x20150204 (538247684)=0D + */=0D +DefinitionBlock ("DSDT.aml", "DSDT", 2, "BHYVE", "BVDSDT", 0x00000001)=0D +{=0D + Name (_S5, Package (0x02)=0D + {=0D + 0x05,=0D + Zero=0D + })=0D + Name (PICM, Zero)=0D + Method (_PIC, 1, NotSerialized)=0D + {=0D + Store (Arg0, PICM)=0D + }=0D +=0D + Scope (_SB)=0D + {=0D + Device (PC00)=0D + {=0D + Name (_HID, EisaId ("PNP0A03"))=0D + Name (_ADR, Zero)=0D + Method (_BBN, 0, NotSerialized)=0D + {=0D + Return (Zero)=0D + }=0D +=0D + Name (_CRS, ResourceTemplate ()=0D + {=0D + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDe= code,=0D + 0x0000, // Granularity=0D + 0x0000, // Range Minimum=0D + 0x00FF, // Range Maximum=0D + 0x0000, // Translation Offset=0D + 0x0100, // Length=0D + ,, )=0D + IO (Decode16,=0D + 0x03C0, // Range Minimum=0D + 0x03C0, // Range Maximum=0D + 0x00, // Alignment=0D + 0x20, // Length=0D + )=0D + IO (Decode16,=0D + 0x0CF8, // Range Minimum=0D + 0x0CF8, // Range Maximum=0D + 0x01, // Alignment=0D + 0x08, // Length=0D + )=0D + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, E= ntireRange,=0D + 0x0000, // Granularity=0D + 0x0000, // Range Minimum=0D + 0x0CF7, // Range Maximum=0D + 0x0000, // Translation Offset=0D + 0x0CF8, // Length=0D + ,, , TypeStatic)=0D + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, E= ntireRange,=0D + 0x0000, // Granularity=0D + 0x0D00, // Range Minimum=0D + 0xFFFF, // Range Maximum=0D + 0x0000, // Translation Offset=0D + 0xF300, // Length=0D + ,, , TypeStatic)=0D + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFix= ed, Cacheable, ReadWrite,=0D + 0x00000000, // Granularity=0D + 0x000A0000, // Range Minimum=0D + 0x000BFFFF, // Range Maximum=0D + 0x00000000, // Translation Offset=0D + 0x00020000, // Length=0D + ,, , AddressRangeMemory, TypeStatic)=0D + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFix= ed, NonCacheable, ReadWrite,=0D + 0x00000000, // Granularity=0D + 0xC0000000, // Range Minimum=0D + 0xDFFFFFFF, // Range Maximum=0D + 0x00000000, // Translation Offset=0D + 0x20000000, // Range Length=0D + ,, PW32)=0D + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFix= ed, NonCacheable, ReadWrite,=0D + 0x00000000, // Granularity=0D + 0xF0000000, // Range Minimum=0D + 0xF07FFFFF, // Range Maximum=0D + 0x00000000, // Translation Offset=0D + 0x00800000, // Range Length=0D + ,, FB32)=0D + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFix= ed, NonCacheable, ReadWrite,=0D + 0x0000000000000000, // Granularity=0D + 0x000000D000000000, // Range Minimum=0D + 0x000000D0000FFFFF, // Range Maximum=0D + 0x0000000000000000, // Translation Offset=0D + 0x0000000000100000, // Length=0D + ,, , AddressRangeMemory, TypeStatic)=0D + })=0D + Name (PPRT, Package ()=0D + {=0D + Package () { 0x0000FFFF, 0, LPC.LNKF, Zero },=0D + Package () { 0x0000FFFF, 1, LPC.LNKG, Zero },=0D + Package () { 0x0000FFFF, 2, LPC.LNKH, Zero },=0D + Package () { 0x0000FFFF, 3, LPC.LNKA, Zero },=0D +=0D + Package () { 0x0001FFFF, 0, LPC.LNKG, Zero },=0D + Package () { 0x0001FFFF, 1, LPC.LNKH, Zero },=0D + Package () { 0x0001FFFF, 2, LPC.LNKA, Zero },=0D + Package () { 0x0001FFFF, 3, LPC.LNKB, Zero },=0D +=0D + Package () { 0x0002FFFF, 0, LPC.LNKH, Zero },=0D + Package () { 0x0002FFFF, 1, LPC.LNKA, Zero },=0D + Package () { 0x0002FFFF, 2, LPC.LNKB, Zero },=0D + Package () { 0x0002FFFF, 3, LPC.LNKC, Zero },=0D +=0D + Package () { 0x0003FFFF, 0, LPC.LNKA, Zero },=0D + Package () { 0x0003FFFF, 1, LPC.LNKB, Zero },=0D + Package () { 0x0003FFFF, 2, LPC.LNKC, Zero },=0D + Package () { 0x0003FFFF, 3, LPC.LNKD, Zero },=0D +=0D + Package () { 0x0004FFFF, 0, LPC.LNKB, Zero },=0D + Package () { 0x0004FFFF, 1, LPC.LNKC, Zero },=0D + Package () { 0x0004FFFF, 2, LPC.LNKD, Zero },=0D + Package () { 0x0004FFFF, 3, LPC.LNKE, Zero },=0D +=0D + Package () { 0x0005FFFF, 0, LPC.LNKC, Zero },=0D + Package () { 0x0005FFFF, 1, LPC.LNKD, Zero },=0D + Package () { 0x0005FFFF, 2, LPC.LNKE, Zero },=0D + Package () { 0x0005FFFF, 3, LPC.LNKF, Zero },=0D +=0D + Package () { 0x0006FFFF, 0, LPC.LNKD, Zero },=0D + Package () { 0x0006FFFF, 1, LPC.LNKE, Zero },=0D + Package () { 0x0006FFFF, 2, LPC.LNKF, Zero },=0D + Package () { 0x0006FFFF, 3, LPC.LNKG, Zero },=0D +=0D + Package () { 0x0007FFFF, 0, LPC.LNKE, Zero },=0D + Package () { 0x0007FFFF, 1, LPC.LNKF, Zero },=0D + Package () { 0x0007FFFF, 2, LPC.LNKG, Zero },=0D + Package () { 0x0007FFFF, 3, LPC.LNKH, Zero },=0D +=0D + Package () { 0x0008FFFF, 0, LPC.LNKF, Zero },=0D + Package () { 0x0008FFFF, 1, LPC.LNKG, Zero },=0D + Package () { 0x0008FFFF, 2, LPC.LNKH, Zero },=0D + Package () { 0x0008FFFF, 3, LPC.LNKA, Zero },=0D +=0D + Package () { 0x0009FFFF, 0, LPC.LNKG, Zero },=0D + Package () { 0x0009FFFF, 1, LPC.LNKH, Zero },=0D + Package () { 0x0009FFFF, 2, LPC.LNKA, Zero },=0D + Package () { 0x0009FFFF, 3, LPC.LNKB, Zero },=0D +=0D + Package () { 0x000AFFFF, 0, LPC.LNKH, Zero },=0D + Package () { 0x000AFFFF, 1, LPC.LNKA, Zero },=0D + Package () { 0x000AFFFF, 2, LPC.LNKB, Zero },=0D + Package () { 0x000AFFFF, 3, LPC.LNKC, Zero },=0D +=0D + Package () { 0x000BFFFF, 0, LPC.LNKA, Zero },=0D + Package () { 0x000BFFFF, 1, LPC.LNKB, Zero },=0D + Package () { 0x000BFFFF, 2, LPC.LNKC, Zero },=0D + Package () { 0x000BFFFF, 3, LPC.LNKD, Zero },=0D +=0D + Package () { 0x000CFFFF, 0, LPC.LNKB, Zero },=0D + Package () { 0x000CFFFF, 1, LPC.LNKC, Zero },=0D + Package () { 0x000CFFFF, 2, LPC.LNKD, Zero },=0D + Package () { 0x000CFFFF, 3, LPC.LNKE, Zero },=0D +=0D + Package () { 0x000DFFFF, 0, LPC.LNKC, Zero },=0D + Package () { 0x000DFFFF, 1, LPC.LNKD, Zero },=0D + Package () { 0x000DFFFF, 2, LPC.LNKE, Zero },=0D + Package () { 0x000DFFFF, 3, LPC.LNKF, Zero },=0D +=0D + Package () { 0x000EFFFF, 0, LPC.LNKD, Zero },=0D + Package () { 0x000EFFFF, 1, LPC.LNKE, Zero },=0D + Package () { 0x000EFFFF, 2, LPC.LNKF, Zero },=0D + Package () { 0x000EFFFF, 3, LPC.LNKG, Zero },=0D +=0D + Package () { 0x000FFFFF, 0, LPC.LNKE, Zero },=0D + Package () { 0x000FFFFF, 1, LPC.LNKF, Zero },=0D + Package () { 0x000FFFFF, 2, LPC.LNKG, Zero },=0D + Package () { 0x000FFFFF, 3, LPC.LNKH, Zero },=0D +=0D + Package () { 0x0010FFFF, 0, LPC.LNKF, Zero },=0D + Package () { 0x0010FFFF, 1, LPC.LNKG, Zero },=0D + Package () { 0x0010FFFF, 2, LPC.LNKH, Zero },=0D + Package () { 0x0010FFFF, 3, LPC.LNKA, Zero },=0D +=0D + Package () { 0x0011FFFF, 0, LPC.LNKG, Zero },=0D + Package () { 0x0011FFFF, 1, LPC.LNKH, Zero },=0D + Package () { 0x0011FFFF, 2, LPC.LNKA, Zero },=0D + Package () { 0x0011FFFF, 3, LPC.LNKB, Zero },=0D +=0D + Package () { 0x0012FFFF, 0, LPC.LNKH, Zero },=0D + Package () { 0x0012FFFF, 1, LPC.LNKA, Zero },=0D + Package () { 0x0012FFFF, 2, LPC.LNKB, Zero },=0D + Package () { 0x0012FFFF, 3, LPC.LNKC, Zero },=0D +=0D + Package () { 0x0013FFFF, 0, LPC.LNKA, Zero },=0D + Package () { 0x0013FFFF, 1, LPC.LNKB, Zero },=0D + Package () { 0x0013FFFF, 2, LPC.LNKC, Zero },=0D + Package () { 0x0013FFFF, 3, LPC.LNKD, Zero },=0D +=0D + Package () { 0x0014FFFF, 0, LPC.LNKB, Zero },=0D + Package () { 0x0014FFFF, 1, LPC.LNKC, Zero },=0D + Package () { 0x0014FFFF, 2, LPC.LNKD, Zero },=0D + Package () { 0x0014FFFF, 3, LPC.LNKE, Zero },=0D +=0D + Package () { 0x0015FFFF, 0, LPC.LNKC, Zero },=0D + Package () { 0x0015FFFF, 1, LPC.LNKD, Zero },=0D + Package () { 0x0015FFFF, 2, LPC.LNKE, Zero },=0D + Package () { 0x0015FFFF, 3, LPC.LNKF, Zero },=0D +=0D + Package () { 0x0016FFFF, 0, LPC.LNKD, Zero },=0D + Package () { 0x0016FFFF, 1, LPC.LNKE, Zero },=0D + Package () { 0x0016FFFF, 2, LPC.LNKF, Zero },=0D + Package () { 0x0016FFFF, 3, LPC.LNKG, Zero },=0D +=0D + Package () { 0x0017FFFF, 0, LPC.LNKE, Zero },=0D + Package () { 0x0017FFFF, 1, LPC.LNKF, Zero },=0D + Package () { 0x0017FFFF, 2, LPC.LNKG, Zero },=0D + Package () { 0x0017FFFF, 3, LPC.LNKH, Zero },=0D +=0D + Package () { 0x0018FFFF, 0, LPC.LNKF, Zero },=0D + Package () { 0x0018FFFF, 1, LPC.LNKG, Zero },=0D + Package () { 0x0018FFFF, 2, LPC.LNKH, Zero },=0D + Package () { 0x0018FFFF, 3, LPC.LNKA, Zero },=0D +=0D + Package () { 0x0019FFFF, 0, LPC.LNKG, Zero },=0D + Package () { 0x0019FFFF, 1, LPC.LNKH, Zero },=0D + Package () { 0x0019FFFF, 2, LPC.LNKA, Zero },=0D + Package () { 0x0019FFFF, 3, LPC.LNKB, Zero },=0D +=0D + Package () { 0x001AFFFF, 0, LPC.LNKH, Zero },=0D + Package () { 0x001AFFFF, 1, LPC.LNKA, Zero },=0D + Package () { 0x001AFFFF, 2, LPC.LNKB, Zero },=0D + Package () { 0x001AFFFF, 3, LPC.LNKC, Zero },=0D +=0D + Package () { 0x001BFFFF, 0, LPC.LNKA, Zero },=0D + Package () { 0x001BFFFF, 1, LPC.LNKB, Zero },=0D + Package () { 0x001BFFFF, 2, LPC.LNKC, Zero },=0D + Package () { 0x001BFFFF, 3, LPC.LNKD, Zero },=0D +=0D + Package () { 0x001CFFFF, 0, LPC.LNKB, Zero },=0D + Package () { 0x001CFFFF, 1, LPC.LNKC, Zero },=0D + Package () { 0x001CFFFF, 2, LPC.LNKD, Zero },=0D + Package () { 0x001CFFFF, 3, LPC.LNKE, Zero },=0D +=0D + Package () { 0x001DFFFF, 0, LPC.LNKC, Zero },=0D + Package () { 0x001DFFFF, 1, LPC.LNKD, Zero },=0D + Package () { 0x001DFFFF, 2, LPC.LNKE, Zero },=0D + Package () { 0x001DFFFF, 3, LPC.LNKF, Zero },=0D +=0D + Package () { 0x001EFFFF, 0, LPC.LNKD, Zero },=0D + Package () { 0x001EFFFF, 1, LPC.LNKE, Zero },=0D + Package () { 0x001EFFFF, 2, LPC.LNKF, Zero },=0D + Package () { 0x001EFFFF, 3, LPC.LNKG, Zero },=0D +=0D + Package () { 0x001FFFFF, 0, LPC.LNKE, Zero },=0D + Package () { 0x001FFFFF, 1, LPC.LNKF, Zero },=0D + Package () { 0x001FFFFF, 2, LPC.LNKG, Zero },=0D + Package () { 0x001FFFFF, 3, LPC.LNKH, Zero }=0D + })=0D + Name (APRT, Package ()=0D + {=0D + Package () { 0x0000FFFF, 0, Zero, 0x15 },=0D + Package () { 0x0000FFFF, 1, Zero, 0x16 },=0D + Package () { 0x0000FFFF, 2, Zero, 0x17 },=0D + Package () { 0x0000FFFF, 3, Zero, 0x10 },=0D +=0D + Package () { 0x0001FFFF, 0, Zero, 0x16 },=0D + Package () { 0x0001FFFF, 1, Zero, 0x17 },=0D + Package () { 0x0001FFFF, 2, Zero, 0x10 },=0D + Package () { 0x0001FFFF, 3, Zero, 0x11 },=0D +=0D + Package () { 0x0002FFFF, 0, Zero, 0x17 },=0D + Package () { 0x0002FFFF, 1, Zero, 0x10 },=0D + Package () { 0x0002FFFF, 2, Zero, 0x11 },=0D + Package () { 0x0002FFFF, 3, Zero, 0x12 },=0D +=0D + Package () { 0x0003FFFF, 0, Zero, 0x10 },=0D + Package () { 0x0003FFFF, 1, Zero, 0x11 },=0D + Package () { 0x0003FFFF, 2, Zero, 0x12 },=0D + Package () { 0x0003FFFF, 3, Zero, 0x13 },=0D +=0D + Package () { 0x0004FFFF, 0, Zero, 0x11 },=0D + Package () { 0x0004FFFF, 1, Zero, 0x12 },=0D + Package () { 0x0004FFFF, 2, Zero, 0x13 },=0D + Package () { 0x0004FFFF, 3, Zero, 0x14 },=0D +=0D + Package () { 0x0005FFFF, 0, Zero, 0x12 },=0D + Package () { 0x0005FFFF, 1, Zero, 0x13 },=0D + Package () { 0x0005FFFF, 2, Zero, 0x14 },=0D + Package () { 0x0005FFFF, 3, Zero, 0x15 },=0D +=0D + Package () { 0x0006FFFF, 0, Zero, 0x13 },=0D + Package () { 0x0006FFFF, 1, Zero, 0x14 },=0D + Package () { 0x0006FFFF, 2, Zero, 0x15 },=0D + Package () { 0x0006FFFF, 3, Zero, 0x16 },=0D +=0D + Package () { 0x0007FFFF, 0, Zero, 0x14 },=0D + Package () { 0x0007FFFF, 1, Zero, 0x15 },=0D + Package () { 0x0007FFFF, 2, Zero, 0x16 },=0D + Package () { 0x0007FFFF, 3, Zero, 0x17 },=0D +=0D + Package () { 0x0008FFFF, 0, Zero, 0x15 },=0D + Package () { 0x0008FFFF, 1, Zero, 0x16 },=0D + Package () { 0x0008FFFF, 2, Zero, 0x17 },=0D + Package () { 0x0008FFFF, 3, Zero, 0x10 },=0D +=0D + Package () { 0x0009FFFF, 0, Zero, 0x16 },=0D + Package () { 0x0009FFFF, 1, Zero, 0x17 },=0D + Package () { 0x0009FFFF, 2, Zero, 0x10 },=0D + Package () { 0x0009FFFF, 3, Zero, 0x11 },=0D +=0D + Package () { 0x000AFFFF, 0, Zero, 0x17 },=0D + Package () { 0x000AFFFF, 1, Zero, 0x10 },=0D + Package () { 0x000AFFFF, 2, Zero, 0x11 },=0D + Package () { 0x000AFFFF, 3, Zero, 0x12 },=0D +=0D + Package () { 0x000BFFFF, 0, Zero, 0x10 },=0D + Package () { 0x000BFFFF, 1, Zero, 0x11 },=0D + Package () { 0x000BFFFF, 2, Zero, 0x12 },=0D + Package () { 0x000BFFFF, 3, Zero, 0x13 },=0D +=0D + Package () { 0x000CFFFF, 0, Zero, 0x11 },=0D + Package () { 0x000CFFFF, 1, Zero, 0x12 },=0D + Package () { 0x000CFFFF, 2, Zero, 0x13 },=0D + Package () { 0x000CFFFF, 3, Zero, 0x14 },=0D +=0D + Package () { 0x000DFFFF, 0, Zero, 0x12 },=0D + Package () { 0x000DFFFF, 1, Zero, 0x13 },=0D + Package () { 0x000DFFFF, 2, Zero, 0x14 },=0D + Package () { 0x000DFFFF, 3, Zero, 0x15 },=0D +=0D + Package () { 0x000EFFFF, 0, Zero, 0x13 },=0D + Package () { 0x000EFFFF, 1, Zero, 0x14 },=0D + Package () { 0x000EFFFF, 2, Zero, 0x15 },=0D + Package () { 0x000EFFFF, 3, Zero, 0x16 },=0D +=0D + Package () { 0x000FFFFF, 0, Zero, 0x14 },=0D + Package () { 0x000FFFFF, 1, Zero, 0x15 },=0D + Package () { 0x000FFFFF, 2, Zero, 0x16 },=0D + Package () { 0x000FFFFF, 3, Zero, 0x17 },=0D +=0D + Package () { 0x0010FFFF, 0, Zero, 0x15 },=0D + Package () { 0x0010FFFF, 1, Zero, 0x16 },=0D + Package () { 0x0010FFFF, 2, Zero, 0x17 },=0D + Package () { 0x0010FFFF, 3, Zero, 0x10 },=0D +=0D + Package () { 0x0011FFFF, 0, Zero, 0x16 },=0D + Package () { 0x0011FFFF, 1, Zero, 0x17 },=0D + Package () { 0x0011FFFF, 2, Zero, 0x10 },=0D + Package () { 0x0011FFFF, 3, Zero, 0x11 },=0D +=0D + Package () { 0x0012FFFF, 0, Zero, 0x17 },=0D + Package () { 0x0012FFFF, 1, Zero, 0x10 },=0D + Package () { 0x0012FFFF, 2, Zero, 0x11 },=0D + Package () { 0x0012FFFF, 3, Zero, 0x12 },=0D +=0D + Package () { 0x0013FFFF, 0, Zero, 0x10 },=0D + Package () { 0x0013FFFF, 1, Zero, 0x11 },=0D + Package () { 0x0013FFFF, 2, Zero, 0x12 },=0D + Package () { 0x0013FFFF, 3, Zero, 0x13 },=0D +=0D + Package () { 0x0014FFFF, 0, Zero, 0x11 },=0D + Package () { 0x0014FFFF, 1, Zero, 0x12 },=0D + Package () { 0x0014FFFF, 2, Zero, 0x13 },=0D + Package () { 0x0014FFFF, 3, Zero, 0x14 },=0D +=0D + Package () { 0x0015FFFF, 0, Zero, 0x12 },=0D + Package () { 0x0015FFFF, 1, Zero, 0x13 },=0D + Package () { 0x0015FFFF, 2, Zero, 0x14 },=0D + Package () { 0x0015FFFF, 3, Zero, 0x15 },=0D +=0D + Package () { 0x0016FFFF, 0, Zero, 0x13 },=0D + Package () { 0x0016FFFF, 1, Zero, 0x14 },=0D + Package () { 0x0016FFFF, 2, Zero, 0x15 },=0D + Package () { 0x0016FFFF, 3, Zero, 0x16 },=0D +=0D + Package () { 0x0017FFFF, 0, Zero, 0x14 },=0D + Package () { 0x0017FFFF, 1, Zero, 0x15 },=0D + Package () { 0x0017FFFF, 2, Zero, 0x16 },=0D + Package () { 0x0017FFFF, 3, Zero, 0x17 },=0D +=0D + Package () { 0x0018FFFF, 0, Zero, 0x15 },=0D + Package () { 0x0018FFFF, 1, Zero, 0x16 },=0D + Package () { 0x0018FFFF, 2, Zero, 0x17 },=0D + Package () { 0x0018FFFF, 3, Zero, 0x10 },=0D +=0D + Package () { 0x0019FFFF, 0, Zero, 0x16 },=0D + Package () { 0x0019FFFF, 1, Zero, 0x17 },=0D + Package () { 0x0019FFFF, 2, Zero, 0x10 },=0D + Package () { 0x0019FFFF, 3, Zero, 0x11 },=0D +=0D + Package () { 0x001AFFFF, 0, Zero, 0x17 },=0D + Package () { 0x001AFFFF, 1, Zero, 0x10 },=0D + Package () { 0x001AFFFF, 2, Zero, 0x11 },=0D + Package () { 0x001AFFFF, 3, Zero, 0x12 },=0D +=0D + Package () { 0x001BFFFF, 0, Zero, 0x10 },=0D + Package () { 0x001BFFFF, 1, Zero, 0x11 },=0D + Package () { 0x001BFFFF, 2, Zero, 0x12 },=0D + Package () { 0x001BFFFF, 3, Zero, 0x13 },=0D +=0D + Package () { 0x001CFFFF, 0, Zero, 0x11 },=0D + Package () { 0x001CFFFF, 1, Zero, 0x12 },=0D + Package () { 0x001CFFFF, 2, Zero, 0x13 },=0D + Package () { 0x001CFFFF, 3, Zero, 0x14 },=0D +=0D + Package () { 0x001DFFFF, 0, Zero, 0x12 },=0D + Package () { 0x001DFFFF, 1, Zero, 0x13 },=0D + Package () { 0x001DFFFF, 2, Zero, 0x14 },=0D + Package () { 0x001DFFFF, 3, Zero, 0x15 },=0D +=0D + Package () { 0x001EFFFF, 0, Zero, 0x13 },=0D + Package () { 0x001EFFFF, 1, Zero, 0x14 },=0D + Package () { 0x001EFFFF, 2, Zero, 0x15 },=0D + Package () { 0x001EFFFF, 3, Zero, 0x16 },=0D +=0D + Package () { 0x001FFFFF, 0, Zero, 0x14 },=0D + Package () { 0x001FFFFF, 1, Zero, 0x15 },=0D + Package () { 0x001FFFFF, 2, Zero, 0x16 },=0D + Package () { 0x001FFFFF, 3, Zero, 0x17 }=0D + })=0D + Method (_PRT, 0, NotSerialized)=0D + {=0D + If (PICM)=0D + {=0D + Return (APRT)=0D + }=0D + Else=0D + {=0D + Return (PPRT)=0D + }=0D + }=0D +=0D + Device (LPC)=0D + {=0D + Name (_ADR, 0x001F0000)=0D + OperationRegion (LPCR, PCI_Config, Zero, 0x0100)=0D + Field (LPCR, AnyAcc, NoLock, Preserve)=0D + {=0D + Offset (0x60),=0D + PIRA, 8,=0D + PIRB, 8,=0D + PIRC, 8,=0D + PIRD, 8,=0D + Offset (0x68),=0D + PIRE, 8,=0D + PIRF, 8,=0D + PIRG, 8,=0D + PIRH, 8=0D + }=0D +=0D + Device (KBD)=0D + {=0D + Name (_HID, EISAID ("PNP0303"))=0D + Name (_CID, EISAID ("PNP030B"))=0D + Name (_CRS, ResourceTemplate ()=0D + {=0D + IO (Decode16,=0D + 0x0060, // Range Minimum=0D + 0x0060, // Range Maximum=0D + 0x00, // Alignment=0D + 0x01, // Length=0D + )=0D + IO (Decode16,=0D + 0x0064, // Range Minimum=0D + 0x0064, // Range Maximum=0D + 0x00, // Alignment=0D + 0x01, // Length=0D + )=0D + IRQNoFlags ()=0D + {1}=0D + })=0D + }=0D +=0D + Device (MOU)=0D + {=0D + Name (_HID, EISAID ("PNP0F03"))=0D + Name (_CID, EISAID ("PNP0F13"))=0D + Name (_CRS, ResourceTemplate ()=0D + {=0D + IRQNoFlags ()=0D + {12}=0D + })=0D + }=0D +=0D + Method (PIRV, 1, NotSerialized)=0D + {=0D + If (And (Arg0, 0x80))=0D + {=0D + Return (Zero)=0D + }=0D +=0D + And (Arg0, 0x0F, Local0)=0D + If (LLess (Local0, 0x03))=0D + {=0D + Return (Zero)=0D + }=0D +=0D + If (LEqual (Local0, 0x08))=0D + {=0D + Return (Zero)=0D + }=0D +=0D + If (LEqual (Local0, 0x0D))=0D + {=0D + Return (Zero)=0D + }=0D +=0D + Return (One)=0D + }=0D +=0D + Device (LNKA)=0D + {=0D + Name (_HID, EisaId ("PNP0C0F"))=0D + Name (_UID, One)=0D + Method (_STA, 0, NotSerialized)=0D + {=0D + If (PIRV (PIRA))=0D + {=0D + Return (0x0B)=0D + }=0D + Else=0D + {=0D + Return (0x09)=0D + }=0D + }=0D +=0D + Name (_PRS, ResourceTemplate ()=0D + {=0D + IRQ (Level, ActiveLow, Shared, )=0D + {3,4,5,6,7,9,10,11,12,14,15}=0D + })=0D + Name (CB01, ResourceTemplate ()=0D + {=0D + IRQ (Level, ActiveLow, Shared, )=0D + {}=0D + })=0D + CreateWordField (CB01, One, CIRA)=0D + Method (_CRS, 0, NotSerialized)=0D + {=0D + And (PIRA, 0x8F, Local0)=0D + If (PIRV (Local0))=0D + {=0D + ShiftLeft (One, Local0, CIRA)=0D + }=0D + Else=0D + {=0D + Store (Zero, CIRA)=0D + }=0D +=0D + Return (CB01)=0D + }=0D +=0D + Method (_DIS, 0, NotSerialized)=0D + {=0D + Store (0x80, PIRA)=0D + }=0D +=0D + Method (_SRS, 1, NotSerialized)=0D + {=0D + CreateWordField (Arg0, One, SIRA)=0D + FindSetRightBit (SIRA, Local0)=0D + Store (Decrement (Local0), PIRA)=0D + }=0D + }=0D +=0D + Device (LNKB)=0D + {=0D + Name (_HID, EisaId ("PNP0C0F"))=0D + Name (_UID, 0x02)=0D + Method (_STA, 0, NotSerialized)=0D + {=0D + If (PIRV (PIRB))=0D + {=0D + Return (0x0B)=0D + }=0D + Else=0D + {=0D + Return (0x09)=0D + }=0D + }=0D +=0D + Name (_PRS, ResourceTemplate ()=0D + {=0D + IRQ (Level, ActiveLow, Shared, )=0D + {3,4,5,6,7,9,10,11,12,14,15}=0D + })=0D + Name (CB02, ResourceTemplate ()=0D + {=0D + IRQ (Level, ActiveLow, Shared, )=0D + {}=0D + })=0D + CreateWordField (CB02, One, CIRB)=0D + Method (_CRS, 0, NotSerialized)=0D + {=0D + And (PIRB, 0x8F, Local0)=0D + If (PIRV (Local0))=0D + {=0D + ShiftLeft (One, Local0, CIRB)=0D + }=0D + Else=0D + {=0D + Store (Zero, CIRB)=0D + }=0D +=0D + Return (CB02)=0D + }=0D +=0D + Method (_DIS, 0, NotSerialized)=0D + {=0D + Store (0x80, PIRB)=0D + }=0D +=0D + Method (_SRS, 1, NotSerialized)=0D + {=0D + CreateWordField (Arg0, One, SIRB)=0D + FindSetRightBit (SIRB, Local0)=0D + Store (Decrement (Local0), PIRB)=0D + }=0D + }=0D +=0D + Device (LNKC)=0D + {=0D + Name (_HID, EisaId ("PNP0C0F"))=0D + Name (_UID, 0x03)=0D + Method (_STA, 0, NotSerialized)=0D + {=0D + If (PIRV (PIRC))=0D + {=0D + Return (0x0B)=0D + }=0D + Else=0D + {=0D + Return (0x09)=0D + }=0D + }=0D +=0D + Name (_PRS, ResourceTemplate ()=0D + {=0D + IRQ (Level, ActiveLow, Shared, )=0D + {3,4,5,6,7,9,10,11,12,14,15}=0D + })=0D + Name (CB03, ResourceTemplate ()=0D + {=0D + IRQ (Level, ActiveLow, Shared, )=0D + {}=0D + })=0D + CreateWordField (CB03, One, CIRC)=0D + Method (_CRS, 0, NotSerialized)=0D + {=0D + And (PIRC, 0x8F, Local0)=0D + If (PIRV (Local0))=0D + {=0D + ShiftLeft (One, Local0, CIRC)=0D + }=0D + Else=0D + {=0D + Store (Zero, CIRC)=0D + }=0D +=0D + Return (CB03)=0D + }=0D +=0D + Method (_DIS, 0, NotSerialized)=0D + {=0D + Store (0x80, PIRC)=0D + }=0D +=0D + Method (_SRS, 1, NotSerialized)=0D + {=0D + CreateWordField (Arg0, One, SIRC)=0D + FindSetRightBit (SIRC, Local0)=0D + Store (Decrement (Local0), PIRC)=0D + }=0D + }=0D +=0D + Device (LNKD)=0D + {=0D + Name (_HID, EisaId ("PNP0C0F"))=0D + Name (_UID, 0x04)=0D + Method (_STA, 0, NotSerialized)=0D + {=0D + If (PIRV (PIRD))=0D + {=0D + Return (0x0B)=0D + }=0D + Else=0D + {=0D + Return (0x09)=0D + }=0D + }=0D +=0D + Name (_PRS, ResourceTemplate ()=0D + {=0D + IRQ (Level, ActiveLow, Shared, )=0D + {3,4,5,6,7,9,10,11,12,14,15}=0D + })=0D + Name (CB04, ResourceTemplate ()=0D + {=0D + IRQ (Level, ActiveLow, Shared, )=0D + {}=0D + })=0D + CreateWordField (CB04, One, CIRD)=0D + Method (_CRS, 0, NotSerialized)=0D + {=0D + And (PIRD, 0x8F, Local0)=0D + If (PIRV (Local0))=0D + {=0D + ShiftLeft (One, Local0, CIRD)=0D + }=0D + Else=0D + {=0D + Store (Zero, CIRD)=0D + }=0D +=0D + Return (CB04)=0D + }=0D +=0D + Method (_DIS, 0, NotSerialized)=0D + {=0D + Store (0x80, PIRD)=0D + }=0D +=0D + Method (_SRS, 1, NotSerialized)=0D + {=0D + CreateWordField (Arg0, One, SIRD)=0D + FindSetRightBit (SIRD, Local0)=0D + Store (Decrement (Local0), PIRD)=0D + }=0D + }=0D +=0D + Device (LNKE)=0D + {=0D + Name (_HID, EisaId ("PNP0C0F"))=0D + Name (_UID, 0x05)=0D + Method (_STA, 0, NotSerialized)=0D + {=0D + If (PIRV (PIRE))=0D + {=0D + Return (0x0B)=0D + }=0D + Else=0D + {=0D + Return (0x09)=0D + }=0D + }=0D +=0D + Name (_PRS, ResourceTemplate ()=0D + {=0D + IRQ (Level, ActiveLow, Shared, )=0D + {3,4,5,6,7,9,10,11,12,14,15}=0D + })=0D + Name (CB05, ResourceTemplate ()=0D + {=0D + IRQ (Level, ActiveLow, Shared, )=0D + {}=0D + })=0D + CreateWordField (CB05, One, CIRE)=0D + Method (_CRS, 0, NotSerialized)=0D + {=0D + And (PIRE, 0x8F, Local0)=0D + If (PIRV (Local0))=0D + {=0D + ShiftLeft (One, Local0, CIRE)=0D + }=0D + Else=0D + {=0D + Store (Zero, CIRE)=0D + }=0D +=0D + Return (CB05)=0D + }=0D +=0D + Method (_DIS, 0, NotSerialized)=0D + {=0D + Store (0x80, PIRE)=0D + }=0D +=0D + Method (_SRS, 1, NotSerialized)=0D + {=0D + CreateWordField (Arg0, One, SIRE)=0D + FindSetRightBit (SIRE, Local0)=0D + Store (Decrement (Local0), PIRE)=0D + }=0D + }=0D +=0D + Device (LNKF)=0D + {=0D + Name (_HID, EisaId ("PNP0C0F"))=0D + Name (_UID, 0x06)=0D + Method (_STA, 0, NotSerialized)=0D + {=0D + If (PIRV (PIRF))=0D + {=0D + Return (0x0B)=0D + }=0D + Else=0D + {=0D + Return (0x09)=0D + }=0D + }=0D +=0D + Name (_PRS, ResourceTemplate ()=0D + {=0D + IRQ (Level, ActiveLow, Shared, )=0D + {3,4,5,6,7,9,10,11,12,14,15}=0D + })=0D + Name (CB06, ResourceTemplate ()=0D + {=0D + IRQ (Level, ActiveLow, Shared, )=0D + {}=0D + })=0D + CreateWordField (CB06, One, CIRF)=0D + Method (_CRS, 0, NotSerialized)=0D + {=0D + And (PIRF, 0x8F, Local0)=0D + If (PIRV (Local0))=0D + {=0D + ShiftLeft (One, Local0, CIRF)=0D + }=0D + Else=0D + {=0D + Store (Zero, CIRF)=0D + }=0D +=0D + Return (CB06)=0D + }=0D +=0D + Method (_DIS, 0, NotSerialized)=0D + {=0D + Store (0x80, PIRF)=0D + }=0D +=0D + Method (_SRS, 1, NotSerialized)=0D + {=0D + CreateWordField (Arg0, One, SIRF)=0D + FindSetRightBit (SIRF, Local0)=0D + Store (Decrement (Local0), PIRF)=0D + }=0D + }=0D +=0D + Device (LNKG)=0D + {=0D + Name (_HID, EisaId ("PNP0C0F"))=0D + Name (_UID, 0x07)=0D + Method (_STA, 0, NotSerialized)=0D + {=0D + If (PIRV (PIRG))=0D + {=0D + Return (0x0B)=0D + }=0D + Else=0D + {=0D + Return (0x09)=0D + }=0D + }=0D +=0D + Name (_PRS, ResourceTemplate ()=0D + {=0D + IRQ (Level, ActiveLow, Shared, )=0D + {3,4,5,6,7,9,10,11,12,14,15}=0D + })=0D + Name (CB07, ResourceTemplate ()=0D + {=0D + IRQ (Level, ActiveLow, Shared, )=0D + {}=0D + })=0D + CreateWordField (CB07, One, CIRG)=0D + Method (_CRS, 0, NotSerialized)=0D + {=0D + And (PIRG, 0x8F, Local0)=0D + If (PIRV (Local0))=0D + {=0D + ShiftLeft (One, Local0, CIRG)=0D + }=0D + Else=0D + {=0D + Store (Zero, CIRG)=0D + }=0D +=0D + Return (CB07)=0D + }=0D +=0D + Method (_DIS, 0, NotSerialized)=0D + {=0D + Store (0x80, PIRG)=0D + }=0D +=0D + Method (_SRS, 1, NotSerialized)=0D + {=0D + CreateWordField (Arg0, One, SIRG)=0D + FindSetRightBit (SIRG, Local0)=0D + Store (Decrement (Local0), PIRG)=0D + }=0D + }=0D +=0D + Device (LNKH)=0D + {=0D + Name (_HID, EisaId ("PNP0C0F"))=0D + Name (_UID, 0x08)=0D + Method (_STA, 0, NotSerialized)=0D + {=0D + If (PIRV (PIRH))=0D + {=0D + Return (0x0B)=0D + }=0D + Else=0D + {=0D + Return (0x09)=0D + }=0D + }=0D +=0D + Name (_PRS, ResourceTemplate ()=0D + {=0D + IRQ (Level, ActiveLow, Shared, )=0D + {3,4,5,6,7,9,10,11,12,14,15}=0D + })=0D + Name (CB08, ResourceTemplate ()=0D + {=0D + IRQ (Level, ActiveLow, Shared, )=0D + {}=0D + })=0D + CreateWordField (CB08, One, CIRH)=0D + Method (_CRS, 0, NotSerialized)=0D + {=0D + And (PIRH, 0x8F, Local0)=0D + If (PIRV (Local0))=0D + {=0D + ShiftLeft (One, Local0, CIRH)=0D + }=0D + Else=0D + {=0D + Store (Zero, CIRH)=0D + }=0D +=0D + Return (CB08)=0D + }=0D +=0D + Method (_DIS, 0, NotSerialized)=0D + {=0D + Store (0x80, PIRH)=0D + }=0D +=0D + Method (_SRS, 1, NotSerialized)=0D + {=0D + CreateWordField (Arg0, One, SIRH)=0D + FindSetRightBit (SIRH, Local0)=0D + Store (Decrement (Local0), PIRH)=0D + }=0D + }=0D +=0D + Device (SIO)=0D + {=0D + Name (_HID, EisaId ("PNP0C02"))=0D + Name (_CRS, ResourceTemplate ()=0D + {=0D + IO (Decode16,=0D + 0x0220, // Range Minimum=0D + 0x0220, // Range Maximum=0D + 0x01, // Alignment=0D + 0x04, // Length=0D + )=0D + IO (Decode16,=0D + 0x0224, // Range Minimum=0D + 0x0224, // Range Maximum=0D + 0x01, // Alignment=0D + 0x04, // Length=0D + )=0D + Memory32Fixed (ReadWrite,=0D + 0xE0000000, // Address Base=0D + 0x10000000, // Address Length=0D + )=0D + IO (Decode16,=0D + 0x04D0, // Range Minimum=0D + 0x04D0, // Range Maximum=0D + 0x01, // Alignment=0D + 0x02, // Length=0D + )=0D + IO (Decode16,=0D + 0x0061, // Range Minimum=0D + 0x0061, // Range Maximum=0D + 0x01, // Alignment=0D + 0x01, // Length=0D + )=0D + IO (Decode16,=0D + 0x0400, // Range Minimum=0D + 0x0400, // Range Maximum=0D + 0x01, // Alignment=0D + 0x08, // Length=0D + )=0D + IO (Decode16,=0D + 0x00B2, // Range Minimum=0D + 0x00B2, // Range Maximum=0D + 0x01, // Alignment=0D + 0x01, // Length=0D + )=0D + IO (Decode16,=0D + 0x0084, // Range Minimum=0D + 0x0084, // Range Maximum=0D + 0x01, // Alignment=0D + 0x01, // Length=0D + )=0D + IO (Decode16,=0D + 0x0072, // Range Minimum=0D + 0x0072, // Range Maximum=0D + 0x01, // Alignment=0D + 0x06, // Length=0D + )=0D + })=0D + }=0D +=0D + Device (COM1)=0D + {=0D + Name (_HID, EisaId ("PNP0501"))=0D + Name (_UID, One)=0D + Name (_CRS, ResourceTemplate ()=0D + {=0D + IO (Decode16,=0D + 0x03F8, // Range Minimum=0D + 0x03F8, // Range Maximum=0D + 0x01, // Alignment=0D + 0x08, // Length=0D + )=0D + IRQNoFlags ()=0D + {4}=0D + })=0D + }=0D +=0D + Device (COM2)=0D + {=0D + Name (_HID, EisaId ("PNP0501"))=0D + Name (_UID, 0x02)=0D + Name (_CRS, ResourceTemplate ()=0D + {=0D + IO (Decode16,=0D + 0x02F8, // Range Minimum=0D + 0x02F8, // Range Maximum=0D + 0x01, // Alignment=0D + 0x08, // Length=0D + )=0D + IRQNoFlags ()=0D + {3}=0D + })=0D + }=0D +=0D + Device (RTC)=0D + {=0D + Name (_HID, EisaId ("PNP0B00"))=0D + Name (_CRS, ResourceTemplate ()=0D + {=0D + IO (Decode16,=0D + 0x0070, // Range Minimum=0D + 0x0070, // Range Maximum=0D + 0x00, // Alignment=0D + 0x02, // Length=0D + )=0D + IRQNoFlags ()=0D + {8}=0D + IO (Decode16,=0D + 0x0072, // Range Minimum=0D + 0x0072, // Range Maximum=0D + 0x02, // Alignment=0D + 0x06, // Length=0D + )=0D + })=0D + }=0D +=0D + Device (PIC)=0D + {=0D + Name (_HID, EisaId ("PNP0000"))=0D + Name (_CRS, ResourceTemplate ()=0D + {=0D + IO (Decode16,=0D + 0x0020, // Range Minimum=0D + 0x0020, // Range Maximum=0D + 0x01, // Alignment=0D + 0x02, // Length=0D + )=0D + IO (Decode16,=0D + 0x00A0, // Range Minimum=0D + 0x00A0, // Range Maximum=0D + 0x01, // Alignment=0D + 0x02, // Length=0D + )=0D + IRQNoFlags ()=0D + {2}=0D + })=0D + }=0D +=0D + Device (TIMR)=0D + {=0D + Name (_HID, EisaId ("PNP0100"))=0D + Name (_CRS, ResourceTemplate ()=0D + {=0D + IO (Decode16,=0D + 0x0040, // Range Minimum=0D + 0x0040, // Range Maximum=0D + 0x01, // Alignment=0D + 0x04, // Length=0D + )=0D + IRQNoFlags ()=0D + {0}=0D + })=0D + }=0D + }=0D + }=0D + }=0D +=0D + Scope (_SB.PC00)=0D + {=0D + Device (HPET)=0D + {=0D + Name (_HID, EisaId ("PNP0103"))=0D + Name (_UID, Zero)=0D + Name (_CRS, ResourceTemplate ()=0D + {=0D + Memory32Fixed (ReadWrite,=0D + 0xFED00000, // Address Base=0D + 0x00000400, // Address Length=0D + )=0D + })=0D + }=0D + }=0D +}=0D +=0D diff --git a/OvmfPkg/Bhyve/AcpiTables/Facp.aslc b/OvmfPkg/Bhyve/AcpiTables/= Facp.aslc new file mode 100644 index 0000000000..b3d703eb89 --- /dev/null +++ b/OvmfPkg/Bhyve/AcpiTables/Facp.aslc @@ -0,0 +1,76 @@ +/*=0D + * Copyright (c) 2020, Rebecca Cran <rebecca@...>=0D + * Copyright (c) 2014, Pluribus Networks, Inc.=0D + *=0D + * SPDX-License-Identifier: BSD-2-Clause-Patent=0D + */=0D +=0D +#include "Platform.h"=0D +=0D +#define EFI_ACPI_OEM_TABLE_ID SIGNATURE_64('B','V','F','A','C','P',' '= ,' ')=0D +=0D +EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE FACP =3D {=0D + {=0D + EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,=0D + sizeof (EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE),=0D + EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION,=0D + 0, // to make sum of entire table =3D=3D 0=0D + {EFI_ACPI_OEM_ID}, // OEMID is a 6 bytes long field=0D + EFI_ACPI_OEM_TABLE_ID, // OEM table identification(8 bytes long)= =0D + EFI_ACPI_OEM_REVISION, // OEM revision number=0D + EFI_ACPI_CREATOR_ID, // ASL compiler vendor ID=0D + EFI_ACPI_CREATOR_REVISION // ASL compiler revision number=0D + },=0D + 0, // Physical addesss of FACS=0D + 0, // Physical address of DSDT=0D + INT_MODEL, // System Interrupt Model=0D + RESERVED, // reserved=0D + SCI_INT_VECTOR, // System vector of SCI interrupt=0D + SMI_CMD_IO_PORT, // Port address of SMI command port=0D + ACPI_ENABLE, // value to write to port smi_cmd to enable ACPI=0D + ACPI_DISABLE, // value to write to port smi_cmd to disable ACPI=0D + S4BIOS_REQ, // Value to write to SMI CMD port to enter the S4BIOS = state=0D + 0, // PState control=0D + PM1a_EVT_BLK, // Port address of Power Mgt 1a Event Reg Blk=0D + PM1b_EVT_BLK, // Port address of Power Mgt 1b Event Reg Blk=0D + PM1a_CNT_BLK, // Port address of Power Mgt 1a Ctrl Reg Blk=0D + PM1b_CNT_BLK, // Port address of Power Mgt 1b Ctrl Reg Blk=0D + PM2_CNT_BLK, // Port address of Power Mgt 2 Ctrl Reg Blk=0D + PM_TMR_BLK, // Port address of Power Mgt Timer Ctrl Reg Blk=0D + GPE0_BLK, // Port addr of General Purpose Event 0 Reg Blk=0D + GPE1_BLK, // Port addr of General Purpose Event 1 Reg Blk=0D + PM1_EVT_LEN, // Byte Length of ports at pm1X_evt_blk=0D + PM1_CNT_LEN, // Byte Length of ports at pm1X_cnt_blk=0D + PM2_CNT_LEN, // Byte Length of ports at pm2_cnt_blk=0D + PM_TM_LEN, // Byte Length of ports at pm_tm_blk=0D + GPE0_BLK_LEN, // Byte Length of ports at gpe0_blk=0D + GPE1_BLK_LEN, // Byte Length of ports at gpe1_blk=0D + GPE1_BASE, // offset in gpe model where gpe1 events start=0D + 0, // _CST support=0D + P_LVL2_LAT, // worst case HW latency to enter/exit C2 state=0D + P_LVL3_LAT, // worst case HW latency to enter/exit C3 state=0D + FLUSH_SIZE, // Size of area read to flush caches=0D + FLUSH_STRIDE, // Stride used in flushing caches=0D + DUTY_OFFSET, // bit location of duty cycle field in p_cnt reg=0D + DUTY_WIDTH, // bit width of duty cycle field in p_cnt reg=0D + DAY_ALRM, // index to day-of-month alarm in RTC CMOS RAM=0D + MON_ALRM, // index to month-of-year alarm in RTC CMOS RAM=0D + CENTURY, // index to century in RTC CMOS RAM=0D + IAPC_BOOT_ARCH, // Boot architecture flag=0D + RESERVED, // reserved=0D + FACP_FLAGS,=0D + FACP_RESET_REG,=0D + FACP_RESET_VAL,=0D +};=0D +=0D +VOID*=0D +ReferenceAcpiTable (=0D + VOID=0D + )=0D +{=0D + //=0D + // Reference the table being generated to prevent the optimizer from rem= oving the=0D + // data structure from the exeutable=0D + //=0D + return (VOID*)&FACP;=0D +}=0D diff --git a/OvmfPkg/Bhyve/AcpiTables/Facs.aslc b/OvmfPkg/Bhyve/AcpiTables/= Facs.aslc new file mode 100644 index 0000000000..05b6410dd5 --- /dev/null +++ b/OvmfPkg/Bhyve/AcpiTables/Facs.aslc @@ -0,0 +1,80 @@ +/** @file=0D + FACS Table=0D +=0D + Copyright (c) 2020, Rebecca Cran <rebecca@...>=0D + Copyright (c) 2008 - 2012, Intel Corporation. All rights reserved.<BR>=0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include <IndustryStandard/Acpi.h>=0D +=0D +EFI_ACPI_1_0_FIRMWARE_ACPI_CONTROL_STRUCTURE FACS =3D {=0D + EFI_ACPI_1_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE,=0D + sizeof (EFI_ACPI_1_0_FIRMWARE_ACPI_CONTROL_STRUCTURE),=0D +=0D + //=0D + // Hardware Signature will be updated at runtime=0D + //=0D + 0x00000000,=0D + 0x00,=0D + 0x00,=0D + 0x00,=0D + {=0D + EFI_ACPI_RESERVED_BYTE,=0D + EFI_ACPI_RESERVED_BYTE,=0D + EFI_ACPI_RESERVED_BYTE,=0D + EFI_ACPI_RESERVED_BYTE,=0D + EFI_ACPI_RESERVED_BYTE,=0D + EFI_ACPI_RESERVED_BYTE,=0D + EFI_ACPI_RESERVED_BYTE,=0D + EFI_ACPI_RESERVED_BYTE,=0D + EFI_ACPI_RESERVED_BYTE,=0D + EFI_ACPI_RESERVED_BYTE,=0D + EFI_ACPI_RESERVED_BYTE,=0D + EFI_ACPI_RESERVED_BYTE,=0D + EFI_ACPI_RESERVED_BYTE,=0D + EFI_ACPI_RESERVED_BYTE,=0D + EFI_ACPI_RESERVED_BYTE,=0D + EFI_ACPI_RESERVED_BYTE,=0D + EFI_ACPI_RESERVED_BYTE,=0D + EFI_ACPI_RESERVED_BYTE,=0D + EFI_ACPI_RESERVED_BYTE,=0D + EFI_ACPI_RESERVED_BYTE,=0D + EFI_ACPI_RESERVED_BYTE,=0D + EFI_ACPI_RESERVED_BYTE,=0D + EFI_ACPI_RESERVED_BYTE,=0D + EFI_ACPI_RESERVED_BYTE,=0D + EFI_ACPI_RESERVED_BYTE,=0D + EFI_ACPI_RESERVED_BYTE,=0D + EFI_ACPI_RESERVED_BYTE,=0D + EFI_ACPI_RESERVED_BYTE,=0D + EFI_ACPI_RESERVED_BYTE,=0D + EFI_ACPI_RESERVED_BYTE,=0D + EFI_ACPI_RESERVED_BYTE,=0D + EFI_ACPI_RESERVED_BYTE,=0D + EFI_ACPI_RESERVED_BYTE,=0D + EFI_ACPI_RESERVED_BYTE,=0D + EFI_ACPI_RESERVED_BYTE,=0D + EFI_ACPI_RESERVED_BYTE,=0D + EFI_ACPI_RESERVED_BYTE,=0D + EFI_ACPI_RESERVED_BYTE,=0D + EFI_ACPI_RESERVED_BYTE,=0D + EFI_ACPI_RESERVED_BYTE=0D + }=0D +};=0D +=0D +=0D +VOID*=0D +ReferenceAcpiTable (=0D + VOID=0D + )=0D +{=0D + //=0D + // Reference the table being generated to prevent the optimizer from rem= oving the=0D + // data structure from the exeutable=0D + //=0D + return (VOID*)&FACS;=0D +}=0D +=0D diff --git a/OvmfPkg/Bhyve/AcpiTables/Hpet.aslc b/OvmfPkg/Bhyve/AcpiTables/= Hpet.aslc new file mode 100644 index 0000000000..73bb784e43 --- /dev/null +++ b/OvmfPkg/Bhyve/AcpiTables/Hpet.aslc @@ -0,0 +1,72 @@ +/*=0D + * Copyright (c) 2020, Rebecca Cran <rebecca@...>=0D + * Copyright (c) 2014, Pluribus Networks, Inc.=0D + *=0D + * SPDX-License-Identifier: BSD-2-Clause-Patent=0D + */=0D +=0D +#include <IndustryStandard/HighPrecisionEventTimerTable.h>=0D +=0D +#include "Platform.h"=0D +=0D +#define EFI_ACPI_HPET_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('H', 'P', = 'E', 'T')=0D +#define EFI_ACPI_OEM_TABLE_ID SIGNATURE_64('B','V','H= ','P','E','T',' ',' ')=0D +=0D +//=0D +// Ensure proper structure formats=0D +//=0D +#pragma pack (1)=0D +=0D +//=0D +// ACPI HPET structure=0D +//=0D +typedef struct {=0D + EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_HEADER Header;=0D +} EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_DESCRIPTION_TABLE;=0D +=0D +#pragma pack ()=0D +=0D +//=0D +// HPET Description Table=0D +//=0D +EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_DESCRIPTION_TABLE Hpet =3D {=0D + {=0D + {=0D + EFI_ACPI_HPET_DESCRIPTION_TABLE_SIGNATURE,=0D + sizeof (EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_DESCRIPTION_TABLE),=0D + EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_REVISION,=0D + 0x00, // Checksum will be updated at ru= ntime=0D + {EFI_ACPI_OEM_ID},=0D + EFI_ACPI_OEM_TABLE_ID,=0D + EFI_ACPI_OEM_REVISION,=0D + EFI_ACPI_CREATOR_ID,=0D + EFI_ACPI_CREATOR_REVISION=0D + },=0D +=0D + //=0D + // HPET specific fields=0D + //=0D + 0x0000A400, // EventTimerBlockId=0D + {=0D + EFI_ACPI_2_0_SYSTEM_MEMORY,=0D + 0,=0D + 0,=0D + EFI_ACPI_RESERVED_BYTE,=0D + 0xFED00000,=0D + },=0D + 0 // HpetNumber=0D + }=0D +};=0D +=0D +=0D +VOID*=0D +ReferenceAcpiTable (=0D + VOID=0D + )=0D +{=0D + //=0D + // Reference the table being generated to prevent the optimizer from rem= oving the=0D + // data structure from the exeutable=0D + //=0D + return (VOID*)&Hpet;=0D +}=0D diff --git a/OvmfPkg/Bhyve/AcpiTables/Madt.aslc b/OvmfPkg/Bhyve/AcpiTables/= Madt.aslc new file mode 100644 index 0000000000..e8e956ed80 --- /dev/null +++ b/OvmfPkg/Bhyve/AcpiTables/Madt.aslc @@ -0,0 +1,145 @@ +/** @file=0D + MADT Table=0D +=0D + This file contains a structure definition for the ACPI 1.0 Multiple APIC= =0D + Description Table (MADT).=0D +=0D + Copyright (c) 2020, Rebecca Cran <rebecca@...>=0D + Copyright (c) 2014, Pluribus Networks, Inc.=0D + Copyright (c) 2008 - 2012, Intel Corporation. All rights reserved.<BR>=0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include <IndustryStandard/Acpi.h>=0D +#include <Platform.h>=0D +=0D +#define EFI_ACPI_OEM_TABLE_ID SIGNATURE_64('B','V','M= ','A','D','T',' ',' ')=0D +=0D +//=0D +// Local APIC address=0D +//=0D +#define EFI_ACPI_LOCAL_APIC_ADDRESS 0xFEE00000=0D +=0D +//=0D +// Multiple APIC Flags are defined in AcpiX.0.h=0D +//=0D +#define EFI_ACPI_1_0_MULTIPLE_APIC_FLAGS (EFI_ACPI_1_0_PCAT_COMPAT)=0D +=0D +//=0D +// Define the number of each table type.=0D +// This is where the table layout is modified.=0D +//=0D +#define EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT 1=0D +#define EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT 1=0D +#define EFI_ACPI_IO_APIC_COUNT 1=0D +=0D +//=0D +// Ensure proper structure formats=0D +//=0D +#pragma pack (1)=0D +=0D +//=0D +// ACPI 1.0 MADT structure=0D +//=0D +typedef struct {=0D + EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;=0D +=0D +#if EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT > 0=0D + EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC_STRUCTURE LocalApic[EFI_ACPI= _PROCESSOR_LOCAL_APIC_COUNT];=0D +#endif=0D +=0D +#if EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT > 0=0D + EFI_ACPI_1_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE Iso[EFI_ACPI_INTER= RUPT_SOURCE_OVERRIDE_COUNT];=0D +#endif=0D +=0D +#if EFI_ACPI_IO_APIC_COUNT > 0=0D + EFI_ACPI_1_0_IO_APIC_STRUCTURE IoApic[EFI_ACPI_IO= _APIC_COUNT];=0D +#endif=0D +=0D +} EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE;=0D +=0D +#pragma pack ()=0D +=0D +//=0D +// Multiple APIC Description Table=0D +//=0D +EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE Madt =3D {=0D + {=0D + {=0D + EFI_ACPI_1_0_APIC_SIGNATURE,=0D + sizeof (EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE),=0D + EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION,=0D + 0x00, // Checksu= m will be updated at runtime=0D + {EFI_ACPI_OEM_ID},=0D + EFI_ACPI_OEM_TABLE_ID,=0D + EFI_ACPI_OEM_REVISION,=0D + EFI_ACPI_CREATOR_ID,=0D + EFI_ACPI_CREATOR_REVISION=0D + },=0D +=0D + //=0D + // MADT specific fields=0D + //=0D + EFI_ACPI_LOCAL_APIC_ADDRESS,=0D + EFI_ACPI_1_0_MULTIPLE_APIC_FLAGS,=0D + },=0D +=0D + //=0D + // Processor Local APIC Structure=0D + //=0D + {=0D + {=0D + EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC, // Type=0D + sizeof (EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length= =0D + 0x00, // Process= or ID=0D + 0x00, // Local A= PIC ID=0D + 0x00000001 // Flags -= Enabled by default=0D + }=0D + },=0D +=0D + //=0D + // Interrupt Source Override Structure=0D + //=0D + {=0D + {=0D + //=0D + // IRQ0=3D>IRQ2 Interrupt Source Override Structure=0D + //=0D + EFI_ACPI_1_0_INTERRUPT_SOURCE_OVERRIDE, // Type=0D + sizeof (EFI_ACPI_1_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE),// Length= =0D + 0x00, // Bus - I= SA=0D + 0x00, // Source = - IRQ0=0D + 0x00000002, // Global = System Interrupt - IRQ2=0D + 0x0005 // Flags -= Conforms to specifications of the bus=0D + },=0D + },=0D +=0D + //=0D + // IO APIC Structure=0D + //=0D + {=0D + {=0D + EFI_ACPI_1_0_IO_APIC, // Type=0D + sizeof (EFI_ACPI_1_0_IO_APIC_STRUCTURE), // Length= =0D + 0x01, // IO APIC= ID=0D + EFI_ACPI_RESERVED_BYTE, // Reserve= d=0D + 0xFEC00000, // IO APIC= Address (physical)=0D + 0x00000000 // Global = System Interrupt Base=0D + }=0D + },=0D +};=0D +=0D +=0D +VOID*=0D +ReferenceAcpiTable (=0D + VOID=0D + )=0D +{=0D + //=0D + // Reference the table being generated to prevent the optimizer from rem= oving the=0D + // data structure from the exeutable=0D + //=0D + return (VOID*)&Madt;=0D +}=0D diff --git a/OvmfPkg/Bhyve/AcpiTables/Mcfg.aslc b/OvmfPkg/Bhyve/AcpiTables/= Mcfg.aslc new file mode 100644 index 0000000000..62a98d30da --- /dev/null +++ b/OvmfPkg/Bhyve/AcpiTables/Mcfg.aslc @@ -0,0 +1,57 @@ +/*=0D + * Copyright (c) 2020, Rebecca Cran <rebecca@...>=0D + * Copyright (c) 2015, Nahanni Systems, Inc.=0D + *=0D + * SPDX-License-Identifier: BSD-2-Clause-Patent=0D + */=0D +=0D +#include "Platform.h"=0D +=0D +#define EFI_ACPI_OEM_TABLE_ID SIGNATURE_64('B','V','M= ','C','F','G',' ',' ')=0D +=0D +#pragma pack(1)=0D +=0D +typedef struct {=0D + EFI_ACPI_DESCRIPTION_HEADER Header;=0D + UINT64 Reserved0;=0D + UINT64 BaseAddress;=0D + UINT16 PciSegmentGroupNumber;=0D + UINT8 StartBusNumber;=0D + UINT8 EndBusNumber;=0D + UINT32 Reserved1;=0D +} EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE;=0D +=0D +#pragma pack()=0D +=0D +EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE MCFG =3D {=0D + {=0D + EFI_ACPI_2_0_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_SIGNATURE,= =0D + sizeof (EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE),=0D + EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION,=0D + 0, // to make sum of entire table =3D=3D 0=0D + {EFI_ACPI_OEM_ID}, // OEMID is a 6 bytes long field=0D + EFI_ACPI_OEM_TABLE_ID, // OEM table identification(8 bytes long)= =0D + EFI_ACPI_OEM_REVISION, // OEM revision number=0D + EFI_ACPI_CREATOR_ID, // ASL compiler vendor ID=0D + EFI_ACPI_CREATOR_REVISION // ASL compiler revision number=0D + },=0D + 0, // Reserved=0D + 0x00000000E0000000, // BaseAddress=0D + 0x0000, // PciSegmentGroupNumber=0D + 0, // StartBusNumber=0D + 255, // EndBusNumber=0D + 0 // Reserved=0D +};=0D +=0D +=0D +VOID *=0D +ReferenceAcpiTable (=0D + VOID=0D + )=0D +{=0D + //=0D + // Reference the table being generated to prevent the optimizer from rem= oving the=0D + // data structure from the exeutable=0D + //=0D + return (VOID*)&MCFG;=0D +}=0D diff --git a/OvmfPkg/Bhyve/AcpiTables/Platform.h b/OvmfPkg/Bhyve/AcpiTables= /Platform.h new file mode 100644 index 0000000000..fc43ab4114 --- /dev/null +++ b/OvmfPkg/Bhyve/AcpiTables/Platform.h @@ -0,0 +1,72 @@ +/** @file=0D + Platform specific defines for constructing ACPI tables=0D +=0D + Copyright (c) 2020, Rebecca Cran <rebecca@...>=0D + Copyright (c) 2014, Pluribus Networks, Inc.=0D + Copyright (c) 2012, 2013, Red Hat, Inc.=0D + Copyright (c) 2008, Intel Corporation. All rights reserved.<BR>=0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#ifndef _Platform_h_INCLUDED_=0D +#define _Platform_h_INCLUDED_=0D +=0D +#include <IndustryStandard/Acpi.h>=0D +#include <IndustryStandard/SerialPortConsoleRedirectionTable.h>=0D +#include <IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h>=0D +=0D +//=0D +// ACPI table information used to initialize tables.=0D +//=0D +#define EFI_ACPI_OEM_ID 'B','H','Y','V','E',' ' // OEMID 6 byt= es long=0D +#define EFI_ACPI_OEM_REVISION 0x1=0D +#define EFI_ACPI_CREATOR_ID SIGNATURE_32('B','H','Y','V')=0D +#define EFI_ACPI_CREATOR_REVISION 0x00000001=0D +=0D +#define INT_MODEL 0x01=0D +#define SCI_INT_VECTOR 0x0009=0D +#define SMI_CMD_IO_PORT 0xB2=0D +#define ACPI_ENABLE 0xA0=0D +#define ACPI_DISABLE 0xA1=0D +#define S4BIOS_REQ 0x00=0D +#define PM1a_EVT_BLK 0x00000400 /* TNXXX */=0D +#define PM1b_EVT_BLK 0x00000000=0D +#define PM1a_CNT_BLK 0x00000404 /* TNXXX */=0D +#define PM1b_CNT_BLK 0x00000000=0D +#define PM2_CNT_BLK 0x00000000=0D +#define PM_TMR_BLK 0x00000408=0D +#define GPE0_BLK 0x00000000=0D +#define GPE1_BLK 0x00000000=0D +#define PM1_EVT_LEN 0x04=0D +#define PM1_CNT_LEN 0x02=0D +#define PM2_CNT_LEN 0x00=0D +#define PM_TM_LEN 0x04=0D +#define GPE0_BLK_LEN 0x00=0D +#define GPE1_BLK_LEN 0x00=0D +#define GPE1_BASE 0x00=0D +#define RESERVED 0x00=0D +#define P_LVL2_LAT 0x0000=0D +#define P_LVL3_LAT 0x0000=0D +#define FLUSH_SIZE 0x0000=0D +#define FLUSH_STRIDE 0x0000=0D +#define DUTY_OFFSET 0x00=0D +#define DUTY_WIDTH 0x00=0D +#define DAY_ALRM 0x00=0D +#define MON_ALRM 0x00=0D +#define CENTURY 0x32=0D +#define IAPC_BOOT_ARCH 0x12 /* 8042 present, disable PCIe ASPM */=0D +#define FACP_FLAGS (EFI_ACPI_1_0_WBINVD | EFI_ACPI_1_0_PROC_C1 | = \=0D + EFI_ACPI_1_0_SLP_BUTTON | EFI_ACPI_1_0_TMR_VAL_EXT= | \=0D + EFI_ACPI_2_0_RESET_REG_SUP | = \=0D + EFI_ACPI_3_0_FORCE_APIC_PHYSICAL_DESTINATION_MODE)= =0D +#define FACP_RESET_REG { \= =0D + EFI_ACPI_3_0_SYSTEM_IO, /* Address Space ID */ \= =0D + 8, /* Bit Width */ \= =0D + 0, /* Bit Offset */ \= =0D + EFI_ACPI_3_0_BYTE, /* Byte Access */ \= =0D + 0xCF9 /* I/O Port */ \= =0D +}=0D +#define FACP_RESET_VAL 0x6=0D +#endif=0D diff --git a/OvmfPkg/Bhyve/AcpiTables/Spcr.aslc b/OvmfPkg/Bhyve/AcpiTables/= Spcr.aslc new file mode 100644 index 0000000000..ec5114ad15 --- /dev/null +++ b/OvmfPkg/Bhyve/AcpiTables/Spcr.aslc @@ -0,0 +1,63 @@ +/*=0D + * Copyright (c) 2020, Rebecca Cran <rebecca@...>=0D + * Copyright (c) 2015, Nahanni Systems, Inc.=0D + *=0D + * SPDX-License-Identifier: BSD-2-Clause-Patent=0D + */=0D +=0D +#include "Platform.h"=0D +=0D +#define EFI_ACPI_OEM_TABLE_ID SIGNATURE_64('B','V','S','P','C','R',' '= ,' ')=0D +=0D +EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE SPCR =3D {=0D + {=0D + EFI_ACPI_2_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE,=0D + sizeof (EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE),=0D + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_REVISION,=0D + 0, // to make sum of entire table =3D=3D 0=0D + {EFI_ACPI_OEM_ID}, // OEMID is a 6 bytes long field=0D + EFI_ACPI_OEM_TABLE_ID, // OEM table identification(8 bytes long)= =0D + EFI_ACPI_OEM_REVISION, // OEM revision number=0D + EFI_ACPI_CREATOR_ID, // ASL compiler vendor ID=0D + EFI_ACPI_CREATOR_REVISION // ASL compiler revision number=0D + },=0D + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_16550,=0D + { 0 }, // Reserved=0D + { // BaseAddress=0D + 0x01, // AddressSpaceId=0D + 0x08, // RegisterBitWidth=0D + 0x00, // RegisterBitOffset=0D + 0x00, // Reserved=0D + 0x03F8 // Address (COM1)=0D + },=0D + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_8259,=0D + 4, // Irq=0D + 0, // GlobalSystemInterrupt=0D + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_115200,=0D + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_PARITY_NO_PARITY,=0D + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_STOP_BITS_1,=0D + 0x03, // FlowControl: RTS/CTS | DCD=0D + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_VT_UTF8,=0D + 0, // Language=0D + 0, // PciDeviceId=0D + 0, // PciVendorId=0D + 0, // PciBusNumber=0D + 0, // PciDeviceNumber=0D + 0, // PciFunctionNumber=0D + 0, // PciFlags=0D + 0, // PciSegment=0D + 0 // Reserved=0D +};=0D +=0D +=0D +VOID *=0D +ReferenceAcpiTable (=0D + VOID=0D + )=0D +{=0D + //=0D + // Reference the table being generated to prevent the optimizer from rem= oving the=0D + // data structure from the exeutable=0D + //=0D + return (VOID*)&SPCR;=0D +}=0D diff --git a/OvmfPkg/Bhyve/AcpiTables/Ssdt.asl b/OvmfPkg/Bhyve/AcpiTables/S= sdt.asl new file mode 100644 index 0000000000..175ab3b7e6 --- /dev/null +++ b/OvmfPkg/Bhyve/AcpiTables/Ssdt.asl @@ -0,0 +1,15 @@ +/** @file=0D + Placeholder for runtime-generated objects.=0D +=0D + This empty table provides only a header for dynamic copying and extensio= n,=0D + and a trigger for QemuInstallAcpiSsdtTable().=0D +=0D + Copyright (C) 2020, Rebecca Cran <rebecca@...>=0D + Copyright (C) 2012 Red Hat, Inc.=0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +DefinitionBlock ("Ssdt.aml", "SSDT", 1, "REDHAT", "OVMF ", 1) {=0D +}=0D diff --git a/OvmfPkg/Bhyve/BhyvePkg.dec b/OvmfPkg/Bhyve/BhyvePkg.dec new file mode 100644 index 0000000000..8884b6276c --- /dev/null +++ b/OvmfPkg/Bhyve/BhyvePkg.dec @@ -0,0 +1,171 @@ +#=0D +# Copyright (c) 2020, Rebecca Cran <rebecca@...>=0D +# Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>= =0D +# Copyright (c) 2014, Pluribus Networks, Inc.=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +[Defines]=0D + DEC_SPECIFICATION =3D 0x00010005=0D + PACKAGE_NAME =3D BhyvePkg=0D + PACKAGE_GUID =3D 178345e1-6ac0-439d-a3df-9abf70dccd57= =0D + PACKAGE_VERSION =3D 0.1=0D +=0D +[Includes]=0D + Include=0D + ../Include=0D +=0D +[LibraryClasses]=0D + ## @libraryclass Save and restore variables using a file=0D + #=0D + NvVarsFileLib|Include/Library/NvVarsFileLib.h=0D +=0D + ## @libraryclass Provides services to work with PCI capabilities in PC= I=0D + # config space.=0D + PciCapLib|Include/Library/PciCapLib.h=0D +=0D + ## @libraryclass Layered on top of PciCapLib, allows clients to plug a= n=0D + # EFI_PCI_IO_PROTOCOL backend into PciCapLib, for confi= g=0D + # space access.=0D + PciCapPciIoLib|Include/Library/PciCapPciIoLib.h=0D +=0D + ## @libraryclass Layered on top of PciCapLib, allows clients to plug a= =0D + # PciSegmentLib backend into PciCapLib, for config spac= e=0D + # access.=0D + PciCapPciSegmentLib|Include/Library/PciCapPciSegmentLib.h=0D +=0D + ## @libraryclass Register a status code handler for printing the Boot= =0D + # Manager's LoadImage() and StartImage() preparations, = and=0D + # return codes, to the UEFI console.=0D + PlatformBmPrintScLib|Include/Library/PlatformBmPrintScLib.h=0D +=0D + ## @libraryclass Serialize (and deserialize) variables=0D + #=0D + SerializeVariablesLib|Include/Library/SerializeVariablesLib.h=0D +=0D + ## @libraryclass Access bhyve's firmware control interface=0D + #=0D + BhyveFwCtlLib|Include/Library/BhyveFwCtlLib.h=0D +=0D +[Guids]=0D + gUefiOvmfPkgTokenSpaceGuid =3D {0x93bb96af, 0xb9f2, 0x4eb8, {0x= 94, 0x62, 0xe0, 0xba, 0x74, 0x56, 0x42, 0x36}}=0D + gOvmfPlatformConfigGuid =3D {0x7235c51c, 0x0c80, 0x4cab, {0x= 87, 0xac, 0x3b, 0x08, 0x4a, 0x63, 0x04, 0xb1}}=0D + gVirtioMmioTransportGuid =3D {0x837dca9e, 0xe874, 0x4d82, {0x= b2, 0x9a, 0x23, 0xfe, 0x0e, 0x23, 0xd1, 0xe2}}=0D + gRootBridgesConnectedEventGroupGuid =3D {0x24a2d66f, 0xeedd, 0x4086, {0x= 90, 0x42, 0xf2, 0x6e, 0x47, 0x97, 0xee, 0x69}}=0D +=0D +[Protocols]=0D + gVirtioDeviceProtocolGuid =3D {0xfa920010, 0x6785, 0x4941, {0x= b6, 0xec, 0x49, 0x8c, 0x57, 0x9f, 0x16, 0x0a}}=0D + gIoMmuAbsentProtocolGuid =3D {0xf8775d50, 0x8abd, 0x4adf, {0x= 92, 0xac, 0x85, 0x3e, 0x51, 0xf6, 0xc8, 0xdc}}=0D +=0D +[PcdsFixedAtBuild]=0D + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfPeiMemFvBase|0x0|UINT32|0=0D + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfPeiMemFvSize|0x0|UINT32|1=0D + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvBase|0x0|UINT32|0x15=0D + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvSize|0x0|UINT32|0x16=0D +=0D + ## This flag is used to control the destination port for PlatformDebugLi= bIoPort=0D + gUefiOvmfPkgTokenSpaceGuid.PcdDebugIoPort|0x2F8|UINT16|4=0D +=0D + ## When VirtioScsiDxe is instantiated for a HBA, the numbers of targets = and=0D + # LUNs are retrieved from the host during virtio-scsi setup.=0D + # MdeModulePkg/Bus/Scsi/ScsiBusDxe then scans all MaxTarget * MaxLun=0D + # possible devices. This can take extremely long, for example with=0D + # MaxTarget=3D255 and MaxLun=3D16383. The *inclusive* constants below l= imit=0D + # MaxTarget and MaxLun, independently, should the host report higher va= lues,=0D + # so that scanning the number of devices given by their product is stil= l=0D + # acceptably fast.=0D + gUefiOvmfPkgTokenSpaceGuid.PcdVirtioScsiMaxTargetLimit|31|UINT16|6=0D + gUefiOvmfPkgTokenSpaceGuid.PcdVirtioScsiMaxLunLimit|7|UINT32|7=0D +=0D + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageEventLogBase|0x0|UINT32|= 0x8=0D + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageEventLogSize|0x0|UINT32|= 0x9=0D + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFirmwareFdSize|0x0|UINT32|0xa=0D + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFirmwareBlockSize|0|UINT32|0xb=0D + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageVariableBase|0x0|UINT32|= 0xc=0D + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageFtwSpareBase|0x0|UINT32|= 0xd=0D + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageFtwWorkingBase|0x0|UINT3= 2|0xe=0D + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFdBaseAddress|0x0|UINT32|0xf=0D + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPageTablesBase|0x0|UINT32|0x11=0D + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPageTablesSize|0x0|UINT32|0x12=0D + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamBase|0x0|UINT32|0x13=0D + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamSize|0x0|UINT32|0x14=0D + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfLockBoxStorageBase|0x0|UINT32|0x18=0D + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfLockBoxStorageSize|0x0|UINT32|0x19=0D + gUefiOvmfPkgTokenSpaceGuid.PcdGuidedExtractHandlerTableSize|0x0|UINT32|0= x1a=0D + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDecompressionScratchEnd|0x0|UINT32|0x1= f=0D +=0D + ## Pcd8259LegacyModeMask defines the default mask value for platform. Th= is=0D + # value is determined.=0D + # 1) If platform only support pure UEFI, value should be set to 0xFFFF = or=0D + # 0xFFFE; Because only clock interrupt is allowed in legacy mode in = pure=0D + # UEFI platform.=0D + # 2) If platform install CSM and use thunk module:=0D + # a) If thunk call provided by CSM binary requires some legacy inter= rupt=0D + # support, the corresponding bit should be opened as 0.=0D + # For example, if keyboard interfaces provided CSM binary use leg= acy=0D + # keyboard interrupt in 8259 bit 1, then the value should be set = to=0D + # 0xFFFC.=0D + # b) If all thunk call provied by CSM binary do not require legacy=0D + # interrupt support, value should be set to 0xFFFF or 0xFFFE.=0D + #=0D + # The default value of legacy mode mask could be changed by=0D + # EFI_LEGACY_8259_PROTOCOL->SetMask(). But it is rarely need change it= =0D + # except some special cases such as when initializing the CSM binary, i= t=0D + # should be set to 0xFFFF to mask all legacy interrupt. Please restore = the=0D + # original legacy mask value if changing is made for these special case= .=0D + gUefiOvmfPkgTokenSpaceGuid.Pcd8259LegacyModeMask|0xFFFF|UINT16|0x3=0D +=0D + ## Pcd8259LegacyModeEdgeLevel defines the default edge level for legacy= =0D + # mode's interrrupt controller.=0D + # For the corresponding bits, 0 =3D Edge triggered and 1 =3D Level trig= gered.=0D + gUefiOvmfPkgTokenSpaceGuid.Pcd8259LegacyModeEdgeLevel|0x0000|UINT16|0x5= =0D +=0D +=0D +=0D +[PcdsDynamic, PcdsDynamicEx]=0D + gUefiOvmfPkgTokenSpaceGuid.PcdEmuVariableEvent|0|UINT64|2=0D + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashVariablesEnable|FALSE|BOOLEAN|0x1= 0=0D + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfHostBridgePciDevId|0|UINT16|0x1b=0D + gUefiOvmfPkgTokenSpaceGuid.PcdQemuSmbiosValidated|FALSE|BOOLEAN|0x21=0D +=0D + ## The IO port aperture shared by all PCI root bridges.=0D + #=0D + gUefiOvmfPkgTokenSpaceGuid.PcdPciIoBase|0x0|UINT64|0x22=0D + gUefiOvmfPkgTokenSpaceGuid.PcdPciIoSize|0x0|UINT64|0x23=0D +=0D + ## The 32-bit MMIO aperture shared by all PCI root bridges.=0D + #=0D + gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT64|0x24=0D + gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT64|0x25=0D +=0D + ## The 64-bit MMIO aperture shared by all PCI root bridges.=0D + #=0D + gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio64Base|0x0|UINT64|0x26=0D + gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x27=0D +=0D + ## The following setting controls how many megabytes we configure as TSE= G on=0D + # Q35, for SMRAM purposes. Permitted defaults are: 1, 2, 8. Other defau= lts=0D + # cause undefined behavior. During boot, the PCD is updated by Platform= Pei=0D + # to reflect the extended TSEG size, if one is advertized by QEMU.=0D + #=0D + # This PCD is only accessed if PcdSmmSmramRequire is TRUE (see below).= =0D + gUefiOvmfPkgTokenSpaceGuid.PcdQ35TsegMbytes|8|UINT16|0x20=0D +=0D +[PcdsFeatureFlag]=0D + gUefiOvmfPkgTokenSpaceGuid.PcdQemuBootOrderPciTranslation|TRUE|BOOLEAN|0= x1c=0D + gUefiOvmfPkgTokenSpaceGuid.PcdQemuBootOrderMmioTranslation|FALSE|BOOLEAN= |0x1d=0D +=0D + ## This feature flag enables SMM/SMRAM support. Note that it also requir= es=0D + # such support from the underlying QEMU instance; if that support is no= t=0D + # present, the firmware will reject continuing after a certain point.=0D + #=0D + # The flag also acts as a general "security switch"; when TRUE, many=0D + # components will change behavior, with the goal of preventing a malici= ous=0D + # runtime OS from tampering with firmware structures (special memory ra= nges=0D + # used by OVMF, the varstore pflash chip, LockBox etc).=0D + gUefiOvmfPkgTokenSpaceGuid.PcdSmmSmramRequire|FALSE|BOOLEAN|0x1e=0D +=0D +[Protocols]=0D +gEfiLegacyBiosProtocolGuid =3D {0xdb9a1e3d, 0x45cb, 0x4abb, {0x85= , 0x3b, 0xe5, 0x38, 0x7f, 0xdb, 0x2e, 0x2d}}=0D diff --git a/OvmfPkg/Bhyve/BhyvePkgDefines.fdf.inc b/OvmfPkg/Bhyve/BhyvePkg= Defines.fdf.inc new file mode 100644 index 0000000000..66e0e4d270 --- /dev/null +++ b/OvmfPkg/Bhyve/BhyvePkgDefines.fdf.inc @@ -0,0 +1,85 @@ +## @file=0D +# FDF include file that defines the main macros and sets the dependent PC= Ds.=0D +#=0D +# Copyright (C) 2014, Red Hat, Inc.=0D +# Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>= =0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +DEFINE BLOCK_SIZE =3D 0x1000=0D +=0D +#=0D +# A firmware binary built with FD_SIZE_IN_KB=3D1024, and a firmware binary= built=0D +# with FD_SIZE_IN_KB=3D2048, use the same variable store layout.=0D +#=0D +# Setting FD_SIZE_IN_KB to 4096 results in a different (much larger) varia= ble=0D +# store structure that is incompatible with both of the above-mentioned=0D +# firmware binaries.=0D +#=0D +!if ($(FD_SIZE_IN_KB) =3D=3D 1024) || ($(FD_SIZE_IN_KB) =3D=3D 2048)=0D +DEFINE VARS_SIZE =3D 0x20000=0D +DEFINE VARS_BLOCKS =3D 0x20=0D +DEFINE VARS_LIVE_SIZE =3D 0xE000=0D +DEFINE VARS_SPARE_SIZE =3D 0x10000=0D +!endif=0D +=0D +!if $(FD_SIZE_IN_KB) =3D=3D 1024=0D +DEFINE FW_BASE_ADDRESS =3D 0xFFF00000=0D +DEFINE FW_SIZE =3D 0x00100000=0D +DEFINE FW_BLOCKS =3D 0x100=0D +DEFINE CODE_BASE_ADDRESS =3D 0xFFF20000=0D +DEFINE CODE_SIZE =3D 0x000E0000=0D +DEFINE CODE_BLOCKS =3D 0xE0=0D +DEFINE FVMAIN_SIZE =3D 0x000CC000=0D +DEFINE SECFV_OFFSET =3D 0x000EC000=0D +DEFINE SECFV_SIZE =3D 0x14000=0D +!endif=0D +=0D +!if $(FD_SIZE_IN_KB) =3D=3D 2048=0D +DEFINE FW_BASE_ADDRESS =3D 0xFFE00000=0D +DEFINE FW_SIZE =3D 0x00200000=0D +DEFINE FW_BLOCKS =3D 0x200=0D +DEFINE CODE_BASE_ADDRESS =3D 0xFFE20000=0D +DEFINE CODE_SIZE =3D 0x001E0000=0D +DEFINE CODE_BLOCKS =3D 0x1E0=0D +DEFINE FVMAIN_SIZE =3D 0x001AC000=0D +DEFINE SECFV_OFFSET =3D 0x001CC000=0D +DEFINE SECFV_SIZE =3D 0x34000=0D +!endif=0D +=0D +!if $(FD_SIZE_IN_KB) =3D=3D 4096=0D +DEFINE VARS_SIZE =3D 0x84000=0D +DEFINE VARS_BLOCKS =3D 0x84=0D +DEFINE VARS_LIVE_SIZE =3D 0x40000=0D +DEFINE VARS_SPARE_SIZE =3D 0x42000=0D +=0D +DEFINE FW_BASE_ADDRESS =3D 0xFFC00000=0D +DEFINE FW_SIZE =3D 0x00400000=0D +DEFINE FW_BLOCKS =3D 0x400=0D +DEFINE CODE_BASE_ADDRESS =3D 0xFFC84000=0D +DEFINE CODE_SIZE =3D 0x0037C000=0D +DEFINE CODE_BLOCKS =3D 0x37C=0D +DEFINE FVMAIN_SIZE =3D 0x00348000=0D +DEFINE SECFV_OFFSET =3D 0x003CC000=0D +DEFINE SECFV_SIZE =3D 0x34000=0D +!endif=0D +=0D +SET gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFdBaseAddress =3D $(FW_BASE_ADDR= ESS)=0D +SET gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFirmwareFdSize =3D $(FW_SIZE)=0D +SET gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFirmwareBlockSize =3D $(BLOCK_SIZE)= =0D +=0D +SET gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageVariableBase =3D $(FW_= BASE_ADDRESS)=0D +SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize =3D $(VAR= S_LIVE_SIZE)=0D +=0D +SET gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageEventLogBase =3D gUefi= OvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageVariableBase + gEfiMdeModulePkgT= okenSpaceGuid.PcdFlashNvStorageVariableSize=0D +SET gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageEventLogSize =3D $(BLO= CK_SIZE)=0D +=0D +SET gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageFtwWorkingBase =3D gUe= fiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageEventLogBase + gUefiOvmfPkgTok= enSpaceGuid.PcdOvmfFlashNvStorageEventLogSize=0D +SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize =3D $(B= LOCK_SIZE)=0D +=0D +SET gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageFtwSpareBase =3D gUefi= OvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageFtwWorkingBase + gEfiMdeModulePk= gTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize=0D +SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize =3D $(VAR= S_SPARE_SIZE)=0D +=0D +DEFINE MEMFD_BASE_ADDRESS =3D 0x800000=0D diff --git a/OvmfPkg/Bhyve/BhyvePkgX64.dsc b/OvmfPkg/Bhyve/BhyvePkgX64.dsc new file mode 100644 index 0000000000..8eba48d109 --- /dev/null +++ b/OvmfPkg/Bhyve/BhyvePkgX64.dsc @@ -0,0 +1,847 @@ +#=0D +# Copyright (c) 2020, Rebecca Cran <rebecca@...>=0D +# Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>= =0D +# (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>=0D +# Copyright (c) 2014, Pluribus Networks, Inc.=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +##########################################################################= ######=0D +#=0D +# Defines Section - statements that will be processed to create a Makefile= .=0D +#=0D +##########################################################################= ######=0D +[Defines]=0D + PLATFORM_NAME =3D Bhyve=0D + PLATFORM_GUID =3D 562b76ee-ceb2-4f4f-adfe-a4c8dc46e4ff= =0D + PLATFORM_VERSION =3D 0.1=0D + DSC_SPECIFICATION =3D 0x00010005=0D + OUTPUT_DIRECTORY =3D Build/BhyveX64=0D + SUPPORTED_ARCHITECTURES =3D X64=0D + BUILD_TARGETS =3D NOOPT|DEBUG|RELEASE=0D + SKUID_IDENTIFIER =3D DEFAULT=0D + FLASH_DEFINITION =3D OvmfPkg/Bhyve/BhyvePkgX64.fdf=0D +=0D + #=0D + # Defines for default states. These can be changed on the command line.= =0D + # -D FLAG=3DVALUE=0D + #=0D + DEFINE SECURE_BOOT_ENABLE =3D FALSE=0D + DEFINE SMM_REQUIRE =3D FALSE=0D + DEFINE SOURCE_DEBUG_ENABLE =3D FALSE=0D + DEFINE TPM_ENABLE =3D FALSE=0D + DEFINE TPM_CONFIG_ENABLE =3D FALSE=0D +=0D + #=0D + # Network definition=0D + #=0D + DEFINE NETWORK_TLS_ENABLE =3D FALSE=0D + DEFINE NETWORK_IP6_ENABLE =3D FALSE=0D + DEFINE NETWORK_HTTP_BOOT_ENABLE =3D FALSE=0D + DEFINE NETWORK_ALLOW_HTTP_CONNECTIONS =3D TRUE=0D +=0D +!include NetworkPkg/NetworkDefines.dsc.inc=0D +=0D + #=0D + # Flash size selection. Setting FD_SIZE_IN_KB on the command line direct= ly to=0D + # one of the supported values, in place of any of the convenience macros= , is=0D + # permitted.=0D + #=0D +!ifdef $(FD_SIZE_1MB)=0D + DEFINE FD_SIZE_IN_KB =3D 1024=0D +!else=0D +!ifdef $(FD_SIZE_2MB)=0D + DEFINE FD_SIZE_IN_KB =3D 2048=0D +!else=0D +!ifdef $(FD_SIZE_4MB)=0D + DEFINE FD_SIZE_IN_KB =3D 4096=0D +!else=0D + DEFINE FD_SIZE_IN_KB =3D 4096=0D +!endif=0D +!endif=0D +!endif=0D +=0D +[BuildOptions]=0D + GCC:RELEASE_*_*_CC_FLAGS =3D -DMDEPKG_NDEBUG=0D + INTEL:RELEASE_*_*_CC_FLAGS =3D /D MDEPKG_NDEBUG=0D + MSFT:RELEASE_*_*_CC_FLAGS =3D /D MDEPKG_NDEBUG=0D +!if $(TOOL_CHAIN_TAG) !=3D "XCODE5" && $(TOOL_CHAIN_TAG) !=3D "CLANGPDB"=0D + GCC:*_*_*_CC_FLAGS =3D -mno-mmx -mno-sse=0D +!endif=0D +!if $(SOURCE_DEBUG_ENABLE) =3D=3D TRUE=0D + MSFT:*_*_X64_GENFW_FLAGS =3D --keepexceptiontable=0D + GCC:*_*_X64_GENFW_FLAGS =3D --keepexceptiontable=0D + INTEL:*_*_X64_GENFW_FLAGS =3D --keepexceptiontable=0D +!endif=0D +=0D + #=0D + # Disable deprecated APIs.=0D + #=0D + MSFT:*_*_*_CC_FLAGS =3D /D DISABLE_NEW_DEPRECATED_INTERFACES=0D + INTEL:*_*_*_CC_FLAGS =3D /D DISABLE_NEW_DEPRECATED_INTERFACES=0D + GCC:*_*_*_CC_FLAGS =3D -D DISABLE_NEW_DEPRECATED_INTERFACES=0D +=0D +[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]=0D + GCC:*_*_*_DLINK_FLAGS =3D -z common-page-size=3D0x1000=0D + XCODE:*_*_*_DLINK_FLAGS =3D -seg1addr 0x1000 -segalign 0x1000=0D + XCODE:*_*_*_MTOC_FLAGS =3D -align 0x1000=0D + CLANGPDB:*_*_*_DLINK_FLAGS =3D /ALIGN:4096=0D +=0D +# Force PE/COFF sections to be aligned at 4KB boundaries to support page l= evel=0D +# protection of DXE_SMM_DRIVER/SMM_CORE modules=0D +[BuildOptions.common.EDKII.DXE_SMM_DRIVER, BuildOptions.common.EDKII.SMM_C= ORE]=0D + GCC:*_*_*_DLINK_FLAGS =3D -z common-page-size=3D0x1000=0D + XCODE:*_*_*_DLINK_FLAGS =3D -seg1addr 0x1000 -segalign 0x1000=0D + XCODE:*_*_*_MTOC_FLAGS =3D -align 0x1000=0D + CLANGPDB:*_*_*_DLINK_FLAGS =3D /ALIGN:4096=0D +=0D +##########################################################################= ######=0D +#=0D +# SKU Identification section - list of all SKU IDs supported by this Platf= orm.=0D +#=0D +##########################################################################= ######=0D +[SkuIds]=0D + 0|DEFAULT=0D +=0D +##########################################################################= ######=0D +#=0D +# Library Class section - list of all Library Classes needed by this Platf= orm.=0D +#=0D +##########################################################################= ######=0D +[LibraryClasses]=0D + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf=0D + TimerLib|OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLibBhyve.inf=0D + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf=0D + BaseMemoryLib|MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf= =0D + BaseLib|MdePkg/Library/BaseLib/BaseLib.inf=0D + SafeIntLib|MdePkg/Library/BaseSafeIntLib/BaseSafeIntLib.inf=0D + BmpSupportLib|MdeModulePkg/Library/BaseBmpSupportLib/BaseBmpSupportLib.i= nf=0D + SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchroniza= tionLib.inf=0D + CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf=0D + PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibN= ull.inf=0D + PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf=0D + CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMain= tenanceLib.inf=0D + UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompres= sLib.inf=0D + UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServic= esLib.inf=0D + HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf=0D + SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf=0D + UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManag= erLib.inf=0D + BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf=0D + FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf= =0D + CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf= =0D + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf=0D + DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableL= ib.inf=0D + PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeC= offGetEntryPointLib.inf=0D + PciCf8Lib|MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf=0D + PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf=0D + PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf=0D + PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.i= nf=0D + PciCapLib|OvmfPkg/Library/BasePciCapLib/BasePciCapLib.inf=0D + PciCapPciSegmentLib|OvmfPkg/Library/BasePciCapPciSegmentLib/BasePciCapPc= iSegmentLib.inf=0D + PciCapPciIoLib|OvmfPkg/Library/UefiPciCapPciIoLib/UefiPciCapPciIoLib.inf= =0D + IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicSev.inf=0D + OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHo= okStatusCodeLibNull.inf=0D + SerialPortLib|PcAtChipsetPkg/Library/SerialIoLib/SerialIoLib.inf=0D + MtrrLib|UefiCpuPkg/Library/MtrrLib/MtrrLib.inf=0D + UefiLib|MdePkg/Library/UefiLib/UefiLib.inf=0D + UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBoo= tServicesTableLib.inf=0D + UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/U= efiRuntimeServicesTableLib.inf=0D + UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntry= Point.inf=0D + UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiA= pplicationEntryPoint.inf=0D + DevicePathLib|MdePkg/Library/UefiDevicePathLibDevicePathProtocol/UefiDev= icePathLibDevicePathProtocol.inf=0D + NvVarsFileLib|OvmfPkg/Library/NvVarsFileLib/NvVarsFileLib.inf=0D + FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf=0D + UefiCpuLib|UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf=0D + SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeS= ecurityManagementLib.inf=0D + SerializeVariablesLib|OvmfPkg/Library/SerializeVariablesLib/SerializeVar= iablesLib.inf=0D + QemuFwCfgLib|OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgLibNull.inf=0D + QemuFwCfgS3Lib|OvmfPkg/Library/QemuFwCfgS3Lib/BaseQemuFwCfgS3LibNull.inf= =0D + BhyveFwCtlLib|OvmfPkg/Bhyve/Library/BhyveFwCtlLib/BhyveFwCtlLib.inf=0D + VirtioLib|OvmfPkg/Library/VirtioLib/VirtioLib.inf=0D + MemEncryptSevLib|OvmfPkg/Library/BaseMemEncryptSevLib/BaseMemEncryptSevL= ib.inf=0D + LockBoxLib|OvmfPkg/Library/LockBoxLib/LockBoxBaseLib.inf=0D +=0D + CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/Customize= dDisplayLib.inf=0D + FrameBufferBltLib|MdeModulePkg/Library/FrameBufferBltLib/FrameBufferBltL= ib.inf=0D +=0D +!if $(SOURCE_DEBUG_ENABLE) =3D=3D TRUE=0D + PeCoffExtraActionLib|SourceLevelDebugPkg/Library/PeCoffExtraActionLibDeb= ug/PeCoffExtraActionLibDebug.inf=0D + DebugCommunicationLib|SourceLevelDebugPkg/Library/DebugCommunicationLibS= erialPort/DebugCommunicationLibSerialPort.inf=0D +!else=0D + PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeC= offExtraActionLibNull.inf=0D + DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.i= nf=0D +!endif=0D +=0D + ResetSystemLib|OvmfPkg/Library/ResetSystemLib/BaseResetSystemLibBhyve.in= f=0D + LocalApicLib|UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.inf=0D + IoApicLib|PcAtChipsetPkg/Library/BaseIoApicLib/BaseIoApicLib.inf=0D + DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseD= ebugPrintErrorLevelLib.inf=0D +=0D + IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf=0D +!if $(NETWORK_TLS_ENABLE) =3D=3D TRUE=0D + OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf=0D +!else=0D + OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLibCrypto.inf=0D +!endif=0D +=0D +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE=0D + PlatformSecureLib|OvmfPkg/Bhyve/Library/PlatformSecureLib/PlatformSecure= Lib.inf=0D + AuthVariableLib|SecurityPkg/Library/AuthVariableLib/AuthVariableLib.inf= =0D +!else=0D + AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLib= Null.inf=0D +!endif=0D + VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf=0D +=0D +=0D + #=0D + # Network libraries=0D + #=0D +!include NetworkPkg/NetworkLibs.dsc.inc=0D +=0D +!if $(NETWORK_TLS_ENABLE) =3D=3D TRUE=0D + TlsLib|CryptoPkg/Library/TlsLib/TlsLib.inf=0D +!endif=0D +=0D + ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf=0D + ShellCEntryLib|ShellPkg/Library/UefiShellCEntryLib/UefiShellCEntryLib.in= f=0D + S3BootScriptLib|MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScrip= tLib.inf=0D + SmbusLib|MdePkg/Library/BaseSmbusLibNull/BaseSmbusLibNull.inf=0D + OrderedCollectionLib|MdePkg/Library/BaseOrderedCollectionRedBlackTreeLib= /BaseOrderedCollectionRedBlackTreeLib.inf=0D + XenPlatformLib|OvmfPkg/Library/XenPlatformLib/XenPlatformLib.inf=0D +=0D +=0D +!if $(TPM_ENABLE) =3D=3D TRUE=0D + Tpm2CommandLib|SecurityPkg/Library/Tpm2CommandLib/Tpm2CommandLib.inf=0D + Tcg2PhysicalPresenceLib|OvmfPkg/Library/Tcg2PhysicalPresenceLibQemu/DxeT= cg2PhysicalPresenceLib.inf=0D + Tcg2PpVendorLib|SecurityPkg/Library/Tcg2PpVendorLibNull/Tcg2PpVendorLibN= ull.inf=0D + TpmMeasurementLib|SecurityPkg/Library/DxeTpmMeasurementLib/DxeTpmMeasure= mentLib.inf=0D +!else=0D + Tcg2PhysicalPresenceLib|OvmfPkg/Library/Tcg2PhysicalPresenceLibNull/DxeT= cg2PhysicalPresenceLib.inf=0D + TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurem= entLibNull.inf=0D +!endif=0D +=0D +[LibraryClasses.common]=0D + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf=0D +=0D +[LibraryClasses.common.SEC]=0D +!ifdef $(DEBUG_ON_SERIAL_PORT)=0D + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.in= f=0D +!else=0D + DebugLib|OvmfPkg/Library/PlatformDebugLibIoPort/PlatformRomDebugLibIoPor= t.inf=0D +!endif=0D + ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiRepor= tStatusCodeLib.inf=0D + ExtractGuidedSectionLib|MdePkg/Library/BaseExtractGuidedSectionLib/BaseE= xtractGuidedSectionLib.inf=0D +!if $(SOURCE_DEBUG_ENABLE) =3D=3D TRUE=0D + DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/SecPeiDebugAgentLib= .inf=0D +!endif=0D + HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf=0D + PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf=0D + PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLibIdt/= PeiServicesTablePointerLibIdt.inf=0D + MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAlloc= ationLib.inf=0D + CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiC= puExceptionHandlerLib.inf=0D +=0D +[LibraryClasses.common.PEI_CORE]=0D + HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf=0D + PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLibIdt/= PeiServicesTablePointerLibIdt.inf=0D + PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf=0D + MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAlloc= ationLib.inf=0D + PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf= =0D + ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiRepor= tStatusCodeLib.inf=0D + OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHo= okStatusCodeLibNull.inf=0D + PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeC= offGetEntryPointLib.inf=0D +!ifdef $(DEBUG_ON_SERIAL_PORT)=0D + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.in= f=0D +!else=0D + DebugLib|OvmfPkg/Library/PlatformDebugLibIoPort/PlatformDebugLibIoPort.i= nf=0D +!endif=0D + PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf=0D +=0D +[LibraryClasses.common.PEIM]=0D + HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf=0D + PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLibIdt/= PeiServicesTablePointerLibIdt.inf=0D + PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf=0D + MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAlloc= ationLib.inf=0D + PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf=0D + ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiRepor= tStatusCodeLib.inf=0D + OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHo= okStatusCodeLibNull.inf=0D + PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeC= offGetEntryPointLib.inf=0D +!ifdef $(DEBUG_ON_SERIAL_PORT)=0D + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.in= f=0D +!else=0D + DebugLib|OvmfPkg/Library/PlatformDebugLibIoPort/PlatformDebugLibIoPort.i= nf=0D +!endif=0D + PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf=0D + ResourcePublicationLib|MdePkg/Library/PeiResourcePublicationLib/PeiResou= rcePublicationLib.inf=0D + ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExt= ractGuidedSectionLib.inf=0D +!if $(SOURCE_DEBUG_ENABLE) =3D=3D TRUE=0D + DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/SecPeiDebugAgentLib= .inf=0D +!endif=0D + CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuE= xceptionHandlerLib.inf=0D + PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf=0D +=0D +!if $(TPM_ENABLE) =3D=3D TRUE=0D + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/PeiCryptLib.inf=0D + Tpm2DeviceLib|SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2DeviceLibDTpm.in= f=0D +!endif=0D +=0D +[LibraryClasses.common.DXE_CORE]=0D + HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf=0D + DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf= =0D + MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeC= oreMemoryAllocationLib.inf=0D + ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeRepor= tStatusCodeLib.inf=0D +!ifdef $(DEBUG_ON_SERIAL_PORT)=0D + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.in= f=0D +!else=0D + DebugLib|OvmfPkg/Library/PlatformDebugLibIoPort/PlatformDebugLibIoPort.i= nf=0D +!endif=0D + ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExt= ractGuidedSectionLib.inf=0D +!if $(SOURCE_DEBUG_ENABLE) =3D=3D TRUE=0D + DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.in= f=0D +!endif=0D + CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuE= xceptionHandlerLib.inf=0D + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf=0D +=0D +[LibraryClasses.common.DXE_RUNTIME_DRIVER]=0D + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf=0D + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf=0D + DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf= =0D + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll= ocationLib.inf=0D + ReportStatusCodeLib|MdeModulePkg/Library/RuntimeDxeReportStatusCodeLib/R= untimeDxeReportStatusCodeLib.inf=0D +!ifdef $(DEBUG_ON_SERIAL_PORT)=0D + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.in= f=0D +!else=0D + DebugLib|OvmfPkg/Library/PlatformDebugLibIoPort/PlatformDebugLibIoPort.i= nf=0D +!endif=0D + UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf=0D + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf=0D + PciLib|OvmfPkg/Library/DxePciLibI440FxQ35/DxePciLibI440FxQ35.inf=0D +=0D +[LibraryClasses.common.UEFI_DRIVER]=0D + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf=0D + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf=0D + DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf= =0D + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll= ocationLib.inf=0D + ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeRepor= tStatusCodeLib.inf=0D +!ifdef $(DEBUG_ON_SERIAL_PORT)=0D + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.in= f=0D +!else=0D + DebugLib|OvmfPkg/Library/PlatformDebugLibIoPort/PlatformDebugLibIoPort.i= nf=0D +!endif=0D + UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf=0D + PciLib|OvmfPkg/Library/DxePciLibI440FxQ35/DxePciLibI440FxQ35.inf=0D +=0D +[LibraryClasses.common.DXE_DRIVER]=0D + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf=0D + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf=0D + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll= ocationLib.inf=0D + ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeRepor= tStatusCodeLib.inf=0D + UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf=0D +!ifdef $(DEBUG_ON_SERIAL_PORT)=0D + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.in= f=0D +!else=0D + DebugLib|OvmfPkg/Library/PlatformDebugLibIoPort/PlatformDebugLibIoPort.i= nf=0D +!endif=0D + PlatformBootManagerLib|OvmfPkg/Bhyve/Library/PlatformBootManagerLib/Plat= formBootManagerLib.inf=0D + PlatformBmPrintScLib|OvmfPkg/Library/PlatformBmPrintScLib/PlatformBmPrin= tScLib.inf=0D + CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuE= xceptionHandlerLib.inf=0D + LockBoxLib|OvmfPkg/Library/LockBoxLib/LockBoxDxeLib.inf=0D +!if $(SOURCE_DEBUG_ENABLE) =3D=3D TRUE=0D + DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.in= f=0D +!endif=0D + PciLib|OvmfPkg/Library/DxePciLibI440FxQ35/DxePciLibI440FxQ35.inf=0D + MpInitLib|UefiCpuPkg/Library/MpInitLibUp/MpInitLibUp.inf=0D +!if $(TPM_ENABLE) =3D=3D TRUE=0D + Tpm2DeviceLib|SecurityPkg/Library/Tpm2DeviceLibTcg2/Tpm2DeviceLibTcg2.in= f=0D +!endif=0D +=0D +[LibraryClasses.common.UEFI_APPLICATION]=0D + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf=0D + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf=0D + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll= ocationLib.inf=0D + ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeRepor= tStatusCodeLib.inf=0D +!ifdef $(DEBUG_ON_SERIAL_PORT)=0D + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.in= f=0D +!else=0D + DebugLib|OvmfPkg/Library/PlatformDebugLibIoPort/PlatformDebugLibIoPort.i= nf=0D +!endif=0D + PciLib|OvmfPkg/Library/DxePciLibI440FxQ35/DxePciLibI440FxQ35.inf=0D +=0D +[LibraryClasses.common.DXE_SMM_DRIVER]=0D + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf=0D + MemoryAllocationLib|MdePkg/Library/SmmMemoryAllocationLib/SmmMemoryAlloc= ationLib.inf=0D + ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeRepor= tStatusCodeLib.inf=0D + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf=0D + SmmMemLib|MdePkg/Library/SmmMemLib/SmmMemLib.inf=0D + MmServicesTableLib|MdePkg/Library/MmServicesTableLib/MmServicesTableLib.= inf=0D + SmmServicesTableLib|MdePkg/Library/SmmServicesTableLib/SmmServicesTableL= ib.inf=0D +!ifdef $(DEBUG_ON_SERIAL_PORT)=0D + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.in= f=0D +!else=0D + DebugLib|OvmfPkg/Library/PlatformDebugLibIoPort/PlatformDebugLibIoPort.i= nf=0D +!endif=0D + CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuE= xceptionHandlerLib.inf=0D +!if $(SOURCE_DEBUG_ENABLE) =3D=3D TRUE=0D + DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/SmmDebugAgentLib.in= f=0D +!endif=0D + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/SmmCryptLib.inf=0D + PciLib|OvmfPkg/Library/DxePciLibI440FxQ35/DxePciLibI440FxQ35.inf=0D +=0D +[LibraryClasses.common.SMM_CORE]=0D + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf=0D + SmmCorePlatformHookLib|MdeModulePkg/Library/SmmCorePlatformHookLibNull/S= mmCorePlatformHookLibNull.inf=0D + MemoryAllocationLib|MdeModulePkg/Library/PiSmmCoreMemoryAllocationLib/Pi= SmmCoreMemoryAllocationLib.inf=0D + ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeRepor= tStatusCodeLib.inf=0D + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf=0D + SmmMemLib|MdePkg/Library/SmmMemLib/SmmMemLib.inf=0D + SmmServicesTableLib|MdeModulePkg/Library/PiSmmCoreSmmServicesTableLib/Pi= SmmCoreSmmServicesTableLib.inf=0D +!ifdef $(DEBUG_ON_SERIAL_PORT)=0D + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.in= f=0D +!else=0D + DebugLib|OvmfPkg/Library/PlatformDebugLibIoPort/PlatformDebugLibIoPort.i= nf=0D +!endif=0D + PciLib|OvmfPkg/Library/DxePciLibI440FxQ35/DxePciLibI440FxQ35.inf=0D +=0D +##########################################################################= ######=0D +#=0D +# Pcd Section - list of all EDK II PCD Entries defined by this Platform.=0D +#=0D +##########################################################################= ######=0D +[PcdsFeatureFlag]=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdHiiOsRuntimeSupport|FALSE=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSupportUefiDecompress|FALSE=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode|FALSE=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutUgaSupport|FALSE=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE=0D +=0D +[PcdsFixedAtBuild]=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|TRUE=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeMemorySize|1=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FAL= SE=0D + gEfiMdePkgTokenSpaceGuid.PcdMaximumGuidedExtractHandler|0x10=0D +!if ($(FD_SIZE_IN_KB) =3D=3D 1024) || ($(FD_SIZE_IN_KB) =3D=3D 2048)=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxAuthVariableSize|0x2800=0D +!if $(NETWORK_TLS_ENABLE) =3D=3D FALSE=0D + # match PcdFlashNvStorageVariableSize purely for convenience=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdVariableStoreSize|0xe000=0D +!endif=0D +!endif=0D +!if $(FD_SIZE_IN_KB) =3D=3D 4096=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x8400=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxAuthVariableSize|0x8400=0D +!if $(NETWORK_TLS_ENABLE) =3D=3D FALSE=0D + # match PcdFlashNvStorageVariableSize purely for convenience=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdVariableStoreSize|0x40000=0D +!endif=0D +!endif=0D +!if $(NETWORK_TLS_ENABLE) =3D=3D TRUE=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdVariableStoreSize|0x80000=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVolatileVariableSize|0x40000=0D +!endif=0D +=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0=0D +=0D + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07=0D +=0D + # DEBUG_INIT 0x00000001 // Initialization=0D + # DEBUG_WARN 0x00000002 // Warnings=0D + # DEBUG_LOAD 0x00000004 // Load events=0D + # DEBUG_FS 0x00000008 // EFI File system=0D + # DEBUG_POOL 0x00000010 // Alloc & Free (pool)=0D + # DEBUG_PAGE 0x00000020 // Alloc & Free (page)=0D + # DEBUG_INFO 0x00000040 // Informational debug messages=0D + # DEBUG_DISPATCH 0x00000080 // PEI/DXE/SMM Dispatchers=0D + # DEBUG_VARIABLE 0x00000100 // Variable=0D + # DEBUG_BM 0x00000400 // Boot Manager=0D + # DEBUG_BLKIO 0x00001000 // BlkIo Driver=0D + # DEBUG_NET 0x00004000 // SNP Driver=0D + # DEBUG_UNDI 0x00010000 // UNDI Driver=0D + # DEBUG_LOADFILE 0x00020000 // LoadFile=0D + # DEBUG_EVENT 0x00080000 // Event messages=0D + # DEBUG_GCD 0x00100000 // Global Coherency Database changes=0D + # DEBUG_CACHE 0x00200000 // Memory range cachability changes=0D + # DEBUG_VERBOSE 0x00400000 // Detailed debug messages that may=0D + # // significantly impact boot performance=0D + # DEBUG_ERROR 0x80000000 // Error=0D + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8000004F=0D +=0D +!if $(SOURCE_DEBUG_ENABLE) =3D=3D TRUE=0D + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x17=0D +!else=0D + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F=0D +!endif=0D +=0D + # This PCD is used to set the base address of the PCI express hierarchy.= It=0D + # is only consulted when OVMF runs on Q35. In that case it is programmed= into=0D + # the PCIEXBAR register.=0D + #=0D + # On Q35 machine types that QEMU intends to support in the long term, QE= MU=0D + # never lets the RAM below 4 GB exceed 2816 MB.=0D + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xB0000000=0D +=0D +!if $(SOURCE_DEBUG_ENABLE) =3D=3D TRUE=0D + gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2=0D +!endif=0D +=0D + #=0D + # Network Pcds=0D + #=0D +!include NetworkPkg/NetworkPcds.dsc.inc=0D +=0D + # Point to the MdeModulePkg/Application/UiApp/UiApp.inf=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c= , 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0= x31 }=0D +=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdConInConnectOnDemand|FALSE=0D +=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVendor|L"BHYVE"=0D +=0D +##########################################################################= ######=0D +#=0D +# Pcd Dynamic Section - list of all EDK II PCD Entries defined by this Pla= tform=0D +#=0D +##########################################################################= ######=0D +=0D +[PcdsDynamicDefault]=0D + # only set when=0D + # ($(SMM_REQUIRE) =3D=3D FALSE)=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvStoreReserved|0=0D +=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|0=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration|TRUE=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|800=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|600=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiS3Enable|FALSE=0D + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfHostBridgePciDevId|0=0D + gUefiOvmfPkgTokenSpaceGuid.PcdPciIoBase|0x0=0D + gUefiOvmfPkgTokenSpaceGuid.PcdPciIoSize|0x0=0D + gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio32Base|0x0=0D + gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio32Size|0x0=0D + gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio64Base|0x0=0D + gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio64Size|0x800000000=0D +=0D + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|0=0D +=0D + # Set video resolution for text setup.=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|640=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|480=0D +=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0208=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosDocRev|0x0=0D + gUefiOvmfPkgTokenSpaceGuid.PcdQemuSmbiosValidated|FALSE=0D +=0D + # Noexec settings for DXE.=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdSetNxForStack|FALSE=0D +=0D + # UefiCpuPkg PCDs related to initial AP bringup and general AP managemen= t.=0D + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|64=0D + gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|50000=0D +=0D + # Set memory encryption mask=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask|0x0=0D +=0D + gEfiSecurityPkgTokenSpaceGuid.PcdOptionRomImageVerificationPolicy|0x00=0D +=0D +!if $(TPM_ENABLE) =3D=3D TRUE=0D + gEfiSecurityPkgTokenSpaceGuid.PcdTpmInstanceGuid|{0x00, 0x00, 0x00, 0x00= , 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}=0D +!endif=0D +=0D + # MdeModulePkg resolution sets up the system display resolution=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|0=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|0=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|0=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|0=0D +=0D +[PcdsDynamicHii]=0D +!if $(TPM_ENABLE) =3D=3D TRUE && $(TPM_CONFIG_ENABLE) =3D=3D TRUE=0D + gEfiSecurityPkgTokenSpaceGuid.PcdTcgPhysicalPresenceInterfaceVer|L"TCG2_= VERSION"|gTcg2ConfigFormSetGuid|0x0|"1.3"|NV,BS=0D + gEfiSecurityPkgTokenSpaceGuid.PcdTpm2AcpiTableRev|L"TCG2_VERSION"|gTcg2C= onfigFormSetGuid|0x8|3|NV,BS=0D +!endif=0D +=0D +##########################################################################= ######=0D +#=0D +# Components Section - list of all EDK II Modules needed by this Platform.= =0D +#=0D +##########################################################################= ######=0D +[Components]=0D + OvmfPkg/ResetVector/ResetVector.inf=0D +=0D + #=0D + # SEC Phase modules=0D + #=0D + OvmfPkg/Sec/SecMain.inf {=0D + <LibraryClasses>=0D + NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompre= ssLib.inf=0D + }=0D +=0D + #=0D + # PEI Phase modules=0D + #=0D + MdeModulePkg/Core/Pei/PeiMain.inf=0D + MdeModulePkg/Universal/PCD/Pei/Pcd.inf {=0D + <LibraryClasses>=0D + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf=0D + }=0D + MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRouter= Pei.inf {=0D + <LibraryClasses>=0D + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf=0D + }=0D + MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf {= =0D + <LibraryClasses>=0D + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf=0D + }=0D + MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf=0D +=0D + OvmfPkg/Bhyve/PlatformPei/PlatformPei.inf=0D + UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf {=0D + <LibraryClasses>=0D + }=0D +=0D +!if $(TPM_ENABLE) =3D=3D TRUE=0D + OvmfPkg/Bhyve/Tcg/Tcg2Config/Tcg2ConfigPei.inf=0D + SecurityPkg/Tcg/Tcg2Pei/Tcg2Pei.inf {=0D + <LibraryClasses>=0D + HashLib|SecurityPkg/Library/HashLibBaseCryptoRouter/HashLibBaseCrypt= oRouterPei.inf=0D + NULL|SecurityPkg/Library/HashInstanceLibSha1/HashInstanceLibSha1.inf= =0D + NULL|SecurityPkg/Library/HashInstanceLibSha256/HashInstanceLibSha256= .inf=0D + NULL|SecurityPkg/Library/HashInstanceLibSha384/HashInstanceLibSha384= .inf=0D + NULL|SecurityPkg/Library/HashInstanceLibSha512/HashInstanceLibSha512= .inf=0D + NULL|SecurityPkg/Library/HashInstanceLibSm3/HashInstanceLibSm3.inf=0D + }=0D +!endif=0D +=0D + #=0D + # DXE Phase modules=0D + #=0D + MdeModulePkg/Core/Dxe/DxeMain.inf {=0D + <LibraryClasses>=0D + NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompre= ssLib.inf=0D + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf= =0D + }=0D +=0D + MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCod= eRouterRuntimeDxe.inf=0D + MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRun= timeDxe.inf=0D + MdeModulePkg/Universal/PCD/Dxe/Pcd.inf {=0D + <LibraryClasses>=0D + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf=0D + }=0D +=0D + MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf=0D +=0D + MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf {=0D + <LibraryClasses>=0D +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE=0D + NULL|SecurityPkg/Library/DxeImageVerificationLib/DxeImageVerificatio= nLib.inf=0D +!endif=0D +!if $(TPM_ENABLE) =3D=3D TRUE=0D + NULL|SecurityPkg/Library/DxeTpm2MeasureBootLib/DxeTpm2MeasureBootLib= .inf=0D +!endif=0D + }=0D +=0D + MdeModulePkg/Universal/EbcDxe/EbcDxe.inf=0D + UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf=0D + UefiCpuPkg/CpuDxe/CpuDxe.inf=0D + PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf=0D + OvmfPkg/IncompatiblePciDeviceSupportDxe/IncompatiblePciDeviceSupport.inf= =0D + OvmfPkg/PciHotPlugInitDxe/PciHotPlugInit.inf=0D + MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf {=0D + <LibraryClasses>=0D + PciHostBridgeLib|OvmfPkg/Library/PciHostBridgeLib/PciHostBridgeLib.i= nf=0D + NULL|OvmfPkg/Library/PlatformHasIoMmuLib/PlatformHasIoMmuLib.inf=0D + }=0D + MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf {=0D + <LibraryClasses>=0D + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf=0D + }=0D + MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf=0D + MdeModulePkg/Universal/Metronome/Metronome.inf=0D + PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntimeDxe.i= nf=0D + MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.inf= =0D + MdeModulePkg/Universal/BdsDxe/BdsDxe.inf {=0D + <LibraryClasses>=0D +!ifdef $(CSM_ENABLE)=0D + NULL|OvmfPkg/Bhyve/Csm/CsmSupportLib/CsmSupportLib.inf=0D + NULL|OvmfPkg/Csm/LegacyBootManagerLib/LegacyBootManagerLib.inf=0D +!endif=0D + }=0D + MdeModulePkg/Logo/LogoDxe.inf=0D + MdeModulePkg/Application/UiApp/UiApp.inf {=0D + <LibraryClasses>=0D + NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf= =0D + NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf=0D + NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanc= eManagerUiLib.inf=0D +!ifdef $(CSM_ENABLE)=0D + NULL|OvmfPkg/Csm/LegacyBootManagerLib/LegacyBootManagerLib.inf=0D + NULL|OvmfPkg/Csm/LegacyBootMaintUiLib/LegacyBootMaintUiLib.inf=0D +!endif=0D + }=0D + OvmfPkg/VirtioPciDeviceDxe/VirtioPciDeviceDxe.inf=0D + OvmfPkg/Virtio10Dxe/Virtio10.inf=0D + OvmfPkg/VirtioBlkDxe/VirtioBlk.inf=0D + OvmfPkg/VirtioScsiDxe/VirtioScsi.inf=0D + OvmfPkg/VirtioRngDxe/VirtioRng.inf=0D + MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf=0D + MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntim= eDxe.inf=0D + MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf=0D + MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf=0D + MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf=0D + MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf= {=0D + <LibraryClasses>=0D + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf=0D + }=0D + MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf=0D + MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf {=0D + <LibraryClasses>=0D + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf= =0D + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf=0D + }=0D + MdeModulePkg/Universal/PrintDxe/PrintDxe.inf=0D + MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf=0D + MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf=0D + MdeModulePkg/Universal/Disk/RamDiskDxe/RamDiskDxe.inf=0D + MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf=0D + FatPkg/EnhancedFatDxe/Fat.inf=0D + MdeModulePkg/Universal/Disk/UdfDxe/UdfDxe.inf=0D + MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf=0D + MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf=0D + OvmfPkg/SataControllerDxe/SataControllerDxe.inf=0D + MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf=0D + MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf=0D + MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf=0D + MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf=0D + MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf=0D + MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf=0D + MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.in= f=0D +=0D + OvmfPkg/Bhyve/BhyveRfbDxe/BhyveRfbDxe.inf {=0D + <LibraryClasses>=0D + BltLib|MdeModulePkg/Library/FrameBufferBltLib/FrameBufferBltLib.inf= =0D + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf=0D + }=0D +=0D + #=0D + # ISA Support=0D + #=0D + OvmfPkg/SioBusDxe/SioBusDxe.inf=0D + MdeModulePkg/Bus/Pci/PciSioSerialDxe/PciSioSerialDxe.inf=0D + MdeModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2KeyboardDxe.inf=0D + MdeModulePkg/Bus/Isa/Ps2MouseDxe/Ps2MouseDxe.inf=0D +=0D + #=0D + # SMBIOS Support=0D + #=0D + MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf=0D + OvmfPkg/Bhyve/SmbiosPlatformDxe/SmbiosPlatformDxe.inf=0D +=0D + #=0D + # ACPI Support=0D + #=0D + MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf=0D + OvmfPkg/Bhyve/AcpiPlatformDxe/AcpiPlatformDxe.inf=0D + OvmfPkg/Bhyve/AcpiTables/AcpiTables.inf=0D + MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf=0D + MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.= inf=0D + MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsRes= ourceTableDxe.inf=0D +=0D + #=0D + # Network Support=0D + #=0D +!include NetworkPkg/NetworkComponents.dsc.inc=0D +=0D +!if $(NETWORK_TLS_ENABLE) =3D=3D TRUE=0D + NetworkPkg/TlsAuthConfigDxe/TlsAuthConfigDxe.inf {=0D + <LibraryClasses>=0D + NULL|OvmfPkg/Bhyve/Library/TlsAuthConfigLib/TlsAuthConfigLib.inf=0D + }=0D +!endif=0D + OvmfPkg/VirtioNetDxe/VirtioNet.inf=0D +=0D +!ifdef $(CSM_ENABLE)=0D + IntelFrameworkModulePkg/Csm/BiosThunk/VideoDxe/VideoDxe.inf {=0D + <LibraryClasses>=0D + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf=0D + }=0D +!endif=0D +# OvmfPkg/Csm/LegacyBiosDxe/LegacyBiosDxe.inf=0D +!ifdef $(CSM_ENABLE)=0D + OvmfPkg/Bhyve/Csm/BhyveCsm16/BhyveCsm16.inf=0D +!endif=0D +=0D +!if $(TOOL_CHAIN_TAG) !=3D "XCODE5"=0D + ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf {=0D + <PcdsFixedAtBuild>=0D + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE=0D + }=0D +!endif=0D + ShellPkg/Application/Shell/Shell.inf {=0D + <LibraryClasses>=0D + ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellComman= dLib.inf=0D + NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2Comm= andsLib.inf=0D + NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1Comm= andsLib.inf=0D + NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3Comm= andsLib.inf=0D + NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1Co= mmandsLib.inf=0D + NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1Comm= andsLib.inf=0D + NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1= CommandsLib.inf=0D + NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1= CommandsLib.inf=0D +!if $(NETWORK_IP6_ENABLE) =3D=3D TRUE=0D + NULL|ShellPkg/Library/UefiShellNetwork2CommandsLib/UefiShellNetwork2= CommandsLib.inf=0D +!endif=0D + HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandlePar= singLib.inf=0D + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf=0D + BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcf= gCommandLib.inf=0D +=0D + <PcdsFixedAtBuild>=0D + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF=0D + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE=0D + gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000=0D + }=0D +=0D +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE=0D + SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDx= e.inf=0D + OvmfPkg/EnrollDefaultKeys/EnrollDefaultKeys.inf=0D +!endif=0D +=0D + OvmfPkg/PlatformDxe/Platform.inf=0D + OvmfPkg/AmdSevDxe/AmdSevDxe.inf=0D + OvmfPkg/IoMmuDxe/IoMmuDxe.inf=0D +=0D +=0D + #=0D + # Variable driver stack (non-SMM)=0D + #=0D + OvmfPkg/QemuFlashFvbServicesRuntimeDxe/FvbServicesRuntimeDxe.inf=0D + OvmfPkg/EmuVariableFvbRuntimeDxe/Fvb.inf {=0D + <LibraryClasses>=0D + PlatformFvbLib|OvmfPkg/Library/EmuVariableFvbLib/EmuVariableFvbLib.i= nf=0D + }=0D + MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf=0D + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf {=0D + <LibraryClasses>=0D + NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf=0D + }=0D +=0D +=0D + #=0D + # TPM support=0D + #=0D +!if $(TPM_ENABLE) =3D=3D TRUE=0D + SecurityPkg/Tcg/Tcg2Dxe/Tcg2Dxe.inf {=0D + <LibraryClasses>=0D + Tpm2DeviceLib|SecurityPkg/Library/Tpm2DeviceLibRouter/Tpm2DeviceLibR= outerDxe.inf=0D + NULL|SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2InstanceLibDTpm.inf=0D + HashLib|SecurityPkg/Library/HashLibBaseCryptoRouter/HashLibBaseCrypt= oRouterDxe.inf=0D + NULL|SecurityPkg/Library/HashInstanceLibSha1/HashInstanceLibSha1.inf= =0D + NULL|SecurityPkg/Library/HashInstanceLibSha256/HashInstanceLibSha256= .inf=0D + NULL|SecurityPkg/Library/HashInstanceLibSha384/HashInstanceLibSha384= .inf=0D + NULL|SecurityPkg/Library/HashInstanceLibSha512/HashInstanceLibSha512= .inf=0D + NULL|SecurityPkg/Library/HashInstanceLibSm3/HashInstanceLibSm3.inf=0D + }=0D +!if $(TPM_CONFIG_ENABLE) =3D=3D TRUE=0D + SecurityPkg/Tcg/Tcg2Config/Tcg2ConfigDxe.inf=0D +!endif=0D +!endif=0D diff --git a/OvmfPkg/Bhyve/BhyvePkgX64.fdf b/OvmfPkg/Bhyve/BhyvePkgX64.fdf new file mode 100644 index 0000000000..e2852aa5e1 --- /dev/null +++ b/OvmfPkg/Bhyve/BhyvePkgX64.fdf @@ -0,0 +1,490 @@ +#=0D +# Copyright (c) 2020, Rebecca Cran <rebecca@...>=0D +# Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>= =0D +# (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>=0D +# Copyright (c) 2014, Pluribus Networks, Inc.=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +##########################################################################= ######=0D +=0D +[Defines]=0D +!include OvmfPkg/Bhyve/BhyvePkgDefines.fdf.inc=0D +=0D +#=0D +# Build the variable store and the firmware code as one unified flash devi= ce=0D +# image.=0D +#=0D +[FD.BHYVE]=0D +BaseAddress =3D $(FW_BASE_ADDRESS)=0D +Size =3D $(FW_SIZE)=0D +ErasePolarity =3D 1=0D +BlockSize =3D $(BLOCK_SIZE)=0D +NumBlocks =3D $(FW_BLOCKS)=0D +=0D +!include VarStore.fdf.inc=0D +=0D +$(VARS_SIZE)|$(FVMAIN_SIZE)=0D +FV =3D FVMAIN_COMPACT=0D +=0D +$(SECFV_OFFSET)|$(SECFV_SIZE)=0D +FV =3D SECFV=0D +=0D +#=0D +# Build the variable store and the firmware code as separate flash device= =0D +# images.=0D +#=0D +[FD.BHYVE_VARS]=0D +BaseAddress =3D $(FW_BASE_ADDRESS)=0D +Size =3D $(VARS_SIZE)=0D +ErasePolarity =3D 1=0D +BlockSize =3D $(BLOCK_SIZE)=0D +NumBlocks =3D $(VARS_BLOCKS)=0D +=0D +!include VarStore.fdf.inc=0D +=0D +[FD.BHYVE_CODE]=0D +BaseAddress =3D $(CODE_BASE_ADDRESS)=0D +Size =3D $(CODE_SIZE)=0D +ErasePolarity =3D 1=0D +BlockSize =3D $(BLOCK_SIZE)=0D +NumBlocks =3D $(CODE_BLOCKS)=0D +=0D +0x00000000|$(FVMAIN_SIZE)=0D +FV =3D FVMAIN_COMPACT=0D +=0D +$(FVMAIN_SIZE)|$(SECFV_SIZE)=0D +FV =3D SECFV=0D +=0D +##########################################################################= ######=0D +=0D +[FD.MEMFD]=0D +BaseAddress =3D $(MEMFD_BASE_ADDRESS)=0D +Size =3D 0xC00000=0D +ErasePolarity =3D 1=0D +BlockSize =3D 0x10000=0D +NumBlocks =3D 0xC0=0D +=0D +0x000000|0x006000=0D +gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPageTablesBase|gUefiOvmfPkgTokenSpace= Guid.PcdOvmfSecPageTablesSize=0D +=0D +0x006000|0x001000=0D +gUefiOvmfPkgTokenSpaceGuid.PcdOvmfLockBoxStorageBase|gUefiOvmfPkgTokenSpac= eGuid.PcdOvmfLockBoxStorageSize=0D +=0D +0x007000|0x001000=0D +gEfiMdePkgTokenSpaceGuid.PcdGuidedExtractHandlerTableAddress|gUefiOvmfPkgT= okenSpaceGuid.PcdGuidedExtractHandlerTableSize=0D +=0D +0x010000|0x010000=0D +gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamBase|gUefiOvmfPkgTokenSpace= Guid.PcdOvmfSecPeiTempRamSize=0D +=0D +0x020000|0x0E0000=0D +gUefiOvmfPkgTokenSpaceGuid.PcdOvmfPeiMemFvBase|gUefiOvmfPkgTokenSpaceGuid.= PcdOvmfPeiMemFvSize=0D +FV =3D PEIFV=0D +=0D +0x100000|0xB00000=0D +gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvBase|gUefiOvmfPkgTokenSpaceGuid.= PcdOvmfDxeMemFvSize=0D +FV =3D DXEFV=0D +=0D +##########################################################################= ######=0D +=0D +[FV.SECFV]=0D +FvNameGuid =3D 763BED0D-DE9F-48F5-81F1-3E90E1B1A015=0D +BlockSize =3D 0x1000=0D +FvAlignment =3D 16=0D +ERASE_POLARITY =3D 1=0D +MEMORY_MAPPED =3D TRUE=0D +STICKY_WRITE =3D TRUE=0D +LOCK_CAP =3D TRUE=0D +LOCK_STATUS =3D TRUE=0D +WRITE_DISABLED_CAP =3D TRUE=0D +WRITE_ENABLED_CAP =3D TRUE=0D +WRITE_STATUS =3D TRUE=0D +WRITE_LOCK_CAP =3D TRUE=0D +WRITE_LOCK_STATUS =3D TRUE=0D +READ_DISABLED_CAP =3D TRUE=0D +READ_ENABLED_CAP =3D TRUE=0D +READ_STATUS =3D TRUE=0D +READ_LOCK_CAP =3D TRUE=0D +READ_LOCK_STATUS =3D TRUE=0D +=0D +#=0D +# SEC Phase modules=0D +#=0D +# The code in this FV handles the initial firmware startup, and=0D +# decompresses the PEI and DXE FVs which handles the rest of the boot sequ= ence.=0D +#=0D +INF OvmfPkg/Sec/SecMain.inf=0D +=0D +INF RuleOverride=3DRESET_VECTOR OvmfPkg/ResetVector/ResetVector.inf=0D +=0D +##########################################################################= ######=0D +[FV.PEIFV]=0D +FvNameGuid =3D 6938079B-B503-4E3D-9D24-B28337A25806=0D +BlockSize =3D 0x10000=0D +FvAlignment =3D 16=0D +ERASE_POLARITY =3D 1=0D +MEMORY_MAPPED =3D TRUE=0D +STICKY_WRITE =3D TRUE=0D +LOCK_CAP =3D TRUE=0D +LOCK_STATUS =3D TRUE=0D +WRITE_DISABLED_CAP =3D TRUE=0D +WRITE_ENABLED_CAP =3D TRUE=0D +WRITE_STATUS =3D TRUE=0D +WRITE_LOCK_CAP =3D TRUE=0D +WRITE_LOCK_STATUS =3D TRUE=0D +READ_DISABLED_CAP =3D TRUE=0D +READ_ENABLED_CAP =3D TRUE=0D +READ_STATUS =3D TRUE=0D +READ_LOCK_CAP =3D TRUE=0D +READ_LOCK_STATUS =3D TRUE=0D +=0D +APRIORI PEI {=0D + INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf=0D +}=0D +=0D +#=0D +# PEI Phase modules=0D +#=0D +INF MdeModulePkg/Core/Pei/PeiMain.inf=0D +INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf=0D +INF MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRou= terPei.inf=0D +INF MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf= =0D +INF OvmfPkg/Bhyve/PlatformPei/PlatformPei.inf=0D +INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf=0D +INF UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf=0D +!if $(SMM_REQUIRE) =3D=3D TRUE=0D +INF OvmfPkg/Bhyve/SmmAccess/SmmAccessPei.inf=0D +!endif=0D +=0D +!if $(TPM_ENABLE) =3D=3D TRUE=0D +INF OvmfPkg/Bhyve/Tcg/Tcg2Config/Tcg2ConfigPei.inf=0D +INF SecurityPkg/Tcg/Tcg2Pei/Tcg2Pei.inf=0D +!endif=0D +=0D +##########################################################################= ######=0D +=0D +[FV.DXEFV]=0D +FvForceRebase =3D FALSE=0D +FvNameGuid =3D 7CB8BDC9-F8EB-4F34-AAEA-3EE4AF6516A1=0D +BlockSize =3D 0x10000=0D +FvAlignment =3D 16=0D +ERASE_POLARITY =3D 1=0D +MEMORY_MAPPED =3D TRUE=0D +STICKY_WRITE =3D TRUE=0D +LOCK_CAP =3D TRUE=0D +LOCK_STATUS =3D TRUE=0D +WRITE_DISABLED_CAP =3D TRUE=0D +WRITE_ENABLED_CAP =3D TRUE=0D +WRITE_STATUS =3D TRUE=0D +WRITE_LOCK_CAP =3D TRUE=0D +WRITE_LOCK_STATUS =3D TRUE=0D +READ_DISABLED_CAP =3D TRUE=0D +READ_ENABLED_CAP =3D TRUE=0D +READ_STATUS =3D TRUE=0D +READ_LOCK_CAP =3D TRUE=0D +READ_LOCK_STATUS =3D TRUE=0D +=0D +APRIORI DXE {=0D + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf=0D + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf=0D + INF OvmfPkg/AmdSevDxe/AmdSevDxe.inf=0D +!if $(SMM_REQUIRE) =3D=3D FALSE=0D + INF OvmfPkg/QemuFlashFvbServicesRuntimeDxe/FvbServicesRuntimeDxe.inf=0D +!endif=0D +}=0D +=0D +#=0D +# DXE Phase modules=0D +#=0D +INF MdeModulePkg/Core/Dxe/DxeMain.inf=0D +=0D +INF MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatus= CodeRouterRuntimeDxe.inf=0D +INF MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandler= RuntimeDxe.inf=0D +INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf=0D +=0D +INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf=0D +INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf=0D +INF MdeModulePkg/Universal/EbcDxe/EbcDxe.inf=0D +INF UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf=0D +INF UefiCpuPkg/CpuDxe/CpuDxe.inf=0D +INF PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf=0D +INF OvmfPkg/IncompatiblePciDeviceSupportDxe/IncompatiblePciDeviceSupport.= inf=0D +INF OvmfPkg/PciHotPlugInitDxe/PciHotPlugInit.inf=0D +INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf=0D +INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf=0D +INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.in= f=0D +INF MdeModulePkg/Universal/Metronome/Metronome.inf=0D +INF PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntimeDx= e.inf=0D +=0D +INF OvmfPkg/VirtioPciDeviceDxe/VirtioPciDeviceDxe.inf=0D +INF OvmfPkg/Virtio10Dxe/Virtio10.inf=0D +INF OvmfPkg/VirtioBlkDxe/VirtioBlk.inf=0D +INF OvmfPkg/VirtioScsiDxe/VirtioScsi.inf=0D +INF OvmfPkg/VirtioRngDxe/VirtioRng.inf=0D +=0D +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE=0D + INF SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootCon= figDxe.inf=0D +!endif=0D +=0D +INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf=0D +INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRun= timeDxe.inf=0D +INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf=0D +INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf=0D +INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf=0D +INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.= inf=0D +INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf=0D +INF MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.= inf=0D +INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf=0D +INF MdeModulePkg/Application/UiApp/UiApp.inf=0D +INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf=0D +INF MdeModulePkg/Universal/PrintDxe/PrintDxe.inf=0D +INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf=0D +INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf=0D +INF MdeModulePkg/Universal/Disk/RamDiskDxe/RamDiskDxe.inf=0D +INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.in= f=0D +INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf=0D +INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf=0D +INF OvmfPkg/SataControllerDxe/SataControllerDxe.inf=0D +INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf=0D +INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf=0D +INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf=0D +INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf=0D +INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf=0D +INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf=0D +INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe= .inf=0D +=0D +=0D +INF OvmfPkg/SioBusDxe/SioBusDxe.inf=0D +INF MdeModulePkg/Bus/Pci/PciSioSerialDxe/PciSioSerialDxe.inf=0D +INF MdeModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2KeyboardDxe.inf=0D +INF MdeModulePkg/Bus/Isa/Ps2MouseDxe/Ps2MouseDxe.inf=0D +=0D +INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf=0D +INF OvmfPkg/Bhyve/SmbiosPlatformDxe/SmbiosPlatformDxe.inf=0D +=0D +INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf=0D +INF OvmfPkg/Bhyve/AcpiPlatformDxe/AcpiPlatformDxe.inf=0D +INF RuleOverride=3DACPITABLE OvmfPkg/Bhyve/AcpiTables/AcpiTables.inf=0D +INF MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf=0D +INF MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorD= xe.inf=0D +INF MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphics= ResourceTableDxe.inf=0D +=0D +INF FatPkg/EnhancedFatDxe/Fat.inf=0D +INF MdeModulePkg/Universal/Disk/UdfDxe/UdfDxe.inf=0D +=0D +!if $(TOOL_CHAIN_TAG) !=3D "XCODE5"=0D +INF ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf=0D +!endif=0D +INF ShellPkg/Application/Shell/Shell.inf=0D +=0D +INF MdeModulePkg/Logo/LogoDxe.inf=0D +=0D +#=0D +# Network modules=0D +#=0D +!if $(E1000_ENABLE)=0D + FILE DRIVER =3D 5D695E11-9B3F-4b83-B25F-4A8D5D69BE07 {=0D + SECTION PE32 =3D Intel3.5/EFIX64/E3522X2.EFI=0D + }=0D +!endif=0D +!include NetworkPkg/Network.fdf.inc=0D + INF OvmfPkg/VirtioNetDxe/VirtioNet.inf=0D +=0D +!ifdef $(CSM_ENABLE)=0D +INF IntelFrameworkModulePkg/Csm/BiosThunk/VideoDxe/VideoDxe.inf=0D +!endif=0D +#INF OvmfPkg/Csm/LegacyBiosDxe/LegacyBiosDxe.inf=0D +!ifdef $(CSM_ENABLE)=0D +INF RuleOverride=3DCSM OvmfPkg/Bhyve/Csm/BhyveCsm16/BhyveCsm16.inf=0D +!endif=0D +=0D +INF OvmfPkg/PlatformDxe/Platform.inf=0D +INF OvmfPkg/AmdSevDxe/AmdSevDxe.inf=0D +INF OvmfPkg/IoMmuDxe/IoMmuDxe.inf=0D +INF OvmfPkg/Bhyve/BhyveRfbDxe/BhyveRfbDxe.inf=0D +=0D +!if $(SMM_REQUIRE) =3D=3D TRUE=0D +INF OvmfPkg/Bhyve/SmmAccess/SmmAccess2Dxe.inf=0D +INF OvmfPkg/Bhyve/SmmControl2Dxe/SmmControl2Dxe.inf=0D +INF UefiCpuPkg/CpuS3DataDxe/CpuS3DataDxe.inf=0D +INF MdeModulePkg/Core/PiSmmCore/PiSmmIpl.inf=0D +INF MdeModulePkg/Core/PiSmmCore/PiSmmCore.inf=0D +INF UefiCpuPkg/CpuIo2Smm/CpuIo2Smm.inf=0D +INF MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf=0D +INF UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf=0D +=0D +#=0D +# Variable driver stack (SMM)=0D +#=0D +INF OvmfPkg/QemuFlashFvbServicesRuntimeDxe/FvbServicesSmm.inf=0D +INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteSmm.in= f=0D +INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmm.inf=0D +INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmmRuntimeDxe.inf= =0D +=0D +!else=0D +=0D +#=0D +# Variable driver stack (non-SMM)=0D +#=0D +INF OvmfPkg/QemuFlashFvbServicesRuntimeDxe/FvbServicesRuntimeDxe.inf=0D +INF OvmfPkg/EmuVariableFvbRuntimeDxe/Fvb.inf=0D +INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.in= f=0D +INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf=0D +!endif=0D +=0D +#=0D +# TPM support=0D +#=0D +!if $(TPM_ENABLE) =3D=3D TRUE=0D +INF SecurityPkg/Tcg/Tcg2Dxe/Tcg2Dxe.inf=0D +!if $(TPM_CONFIG_ENABLE) =3D=3D TRUE=0D +INF SecurityPkg/Tcg/Tcg2Config/Tcg2ConfigDxe.inf=0D +!endif=0D +!endif=0D +=0D +##########################################################################= ######=0D +=0D +[FV.FVMAIN_COMPACT]=0D +FvNameGuid =3D 48DB5E17-707C-472D-91CD-1613E7EF51B0=0D +FvAlignment =3D 16=0D +ERASE_POLARITY =3D 1=0D +MEMORY_MAPPED =3D TRUE=0D +STICKY_WRITE =3D TRUE=0D +LOCK_CAP =3D TRUE=0D +LOCK_STATUS =3D TRUE=0D +WRITE_DISABLED_CAP =3D TRUE=0D +WRITE_ENABLED_CAP =3D TRUE=0D +WRITE_STATUS =3D TRUE=0D +WRITE_LOCK_CAP =3D TRUE=0D +WRITE_LOCK_STATUS =3D TRUE=0D +READ_DISABLED_CAP =3D TRUE=0D +READ_ENABLED_CAP =3D TRUE=0D +READ_STATUS =3D TRUE=0D +READ_LOCK_CAP =3D TRUE=0D +READ_LOCK_STATUS =3D TRUE=0D +=0D +FILE FV_IMAGE =3D 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {=0D + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED= =3D TRUE {=0D + #=0D + # These firmware volumes will have files placed in them uncompressed,= =0D + # and then both firmware volumes will be compressed in a single=0D + # compression operation in order to achieve better overall compressio= n.=0D + #=0D + SECTION FV_IMAGE =3D PEIFV=0D + SECTION FV_IMAGE =3D DXEFV=0D + }=0D + }=0D +=0D +!include FvmainCompactScratchEnd.fdf.inc=0D +=0D +##########################################################################= ######=0D +=0D +[Rule.Common.SEC]=0D + FILE SEC =3D $(NAMED_GUID) {=0D + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi=0D + UI STRING =3D"$(MODULE_NAME)" Optional=0D + VERSION STRING =3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBE= R)=0D + }=0D +=0D +[Rule.Common.PEI_CORE]=0D + FILE PEI_CORE =3D $(NAMED_GUID) {=0D + PE32 PE32 Align=3DAuto $(INF_OUTPUT)/$(MODULE_NAME).efi=0D + UI STRING =3D"$(MODULE_NAME)" Optional=0D + VERSION STRING =3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBE= R)=0D + }=0D +=0D +[Rule.Common.PEIM]=0D + FILE PEIM =3D $(NAMED_GUID) {=0D + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depe= x=0D + PE32 PE32 Align=3DAuto $(INF_OUTPUT)/$(MODULE_NAME).ef= i=0D + UI STRING=3D"$(MODULE_NAME)" Optional=0D + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBE= R)=0D + }=0D +=0D +[Rule.Common.DXE_CORE]=0D + FILE DXE_CORE =3D $(NAMED_GUID) {=0D + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi=0D + UI STRING=3D"$(MODULE_NAME)" Optional=0D + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBER= )=0D + }=0D +=0D +[Rule.Common.DXE_DRIVER]=0D + FILE DRIVER =3D $(NAMED_GUID) {=0D + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depe= x=0D + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi=0D + UI STRING=3D"$(MODULE_NAME)" Optional=0D + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBER= )=0D + RAW ACPI Optional |.acpi=0D + RAW ASL Optional |.aml=0D + }=0D +=0D +[Rule.Common.DXE_RUNTIME_DRIVER]=0D + FILE DRIVER =3D $(NAMED_GUID) {=0D + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depe= x=0D + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi=0D + UI STRING=3D"$(MODULE_NAME)" Optional=0D + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBER= )=0D + }=0D +=0D +[Rule.Common.UEFI_DRIVER]=0D + FILE DRIVER =3D $(NAMED_GUID) {=0D + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depe= x=0D + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi=0D + UI STRING=3D"$(MODULE_NAME)" Optional=0D + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBER= )=0D + }=0D +=0D +[Rule.Common.UEFI_DRIVER.BINARY]=0D + FILE DRIVER =3D $(NAMED_GUID) {=0D + DXE_DEPEX DXE_DEPEX Optional |.depex=0D + PE32 PE32 |.efi=0D + UI STRING=3D"$(MODULE_NAME)" Optional=0D + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBE= R)=0D + }=0D +=0D +[Rule.Common.UEFI_APPLICATION]=0D + FILE APPLICATION =3D $(NAMED_GUID) {=0D + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi=0D + UI STRING=3D"$(MODULE_NAME)" Optional=0D + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBER= )=0D + }=0D +=0D +[Rule.Common.UEFI_APPLICATION.BINARY]=0D + FILE APPLICATION =3D $(NAMED_GUID) {=0D + PE32 PE32 |.efi=0D + UI STRING=3D"$(MODULE_NAME)" Optional=0D + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBE= R)=0D + }=0D +=0D +[Rule.Common.USER_DEFINED.ACPITABLE]=0D + FILE FREEFORM =3D $(NAMED_GUID) {=0D + RAW ACPI |.acpi=0D + RAW ASL |.aml=0D + }=0D +=0D +[Rule.Common.USER_DEFINED.CSM]=0D + FILE FREEFORM =3D $(NAMED_GUID) {=0D + RAW BIN |.bin=0D + }=0D +=0D +[Rule.Common.SEC.RESET_VECTOR]=0D + FILE RAW =3D $(NAMED_GUID) {=0D + RAW BIN Align =3D 16 |.bin=0D + }=0D +=0D +[Rule.Common.SMM_CORE]=0D + FILE SMM_CORE =3D $(NAMED_GUID) {=0D + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi=0D + UI STRING=3D"$(MODULE_NAME)" Optional=0D + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBER= )=0D + }=0D +=0D +[Rule.Common.DXE_SMM_DRIVER]=0D + FILE SMM =3D $(NAMED_GUID) {=0D + SMM_DEPEX SMM_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depe= x=0D + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi=0D + UI STRING=3D"$(MODULE_NAME)" Optional=0D + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBER= )=0D + }=0D diff --git a/OvmfPkg/Bhyve/BhyveRfbDxe/BhyveRfbDxe.inf b/OvmfPkg/Bhyve/Bhyv= eRfbDxe/BhyveRfbDxe.inf new file mode 100644 index 0000000000..8fd72cb78d --- /dev/null +++ b/OvmfPkg/Bhyve/BhyveRfbDxe/BhyveRfbDxe.inf @@ -0,0 +1,68 @@ +## @file=0D +# GOP driver=0D +#=0D +# Copyright (c) 2020, Rebecca Cran <rebecca@...>=0D +# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>=0D +# Portions copyright (c) 2011, Apple Inc. All rights reserved.=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010005=0D + BASE_NAME =3D EmuGopDxe=0D + FILE_GUID =3D 1b290126-5760-424e-8aa2-3faf4d0d7978= =0D + MODULE_TYPE =3D UEFI_DRIVER=0D + VERSION_STRING =3D 1.0=0D +=0D + ENTRY_POINT =3D InitializeEmuGop=0D +=0D +#=0D +# The following information is for reference only and not required by the = build tools.=0D +#=0D +# VALID_ARCHITECTURES =3D IA32 X64 EBC=0D +#=0D +# DRIVER_BINDING =3D gEmuGopDriverBinding=0D +# COMPONENT_NAME =3D gEmuGopComponentName=0D +#=0D +=0D +[Sources]=0D + ComponentName.c=0D + GopScreen.c=0D + GopDriver.c=0D + Gop.h=0D + VbeShim.c=0D +=0D +=0D +[Packages]=0D + MdePkg/MdePkg.dec=0D + OvmfPkg/Bhyve/BhyvePkg.dec=0D + MdeModulePkg/MdeModulePkg.dec=0D +=0D +=0D +[LibraryClasses]=0D + BaseLib=0D + BaseMemoryLib=0D + BltLib=0D + DebugLib=0D + DevicePathLib=0D + MemoryAllocationLib=0D + PciLib=0D + PcdLib=0D + PrintLib=0D + UefiLib=0D + UefiBootServicesTableLib=0D + UefiDriverEntryPoint=0D +=0D +=0D +[Protocols]=0D + gEfiGraphicsOutputProtocolGuid # PROTOCOL BY_START=0D + gEfiDevicePathProtocolGuid # PROTOCOL TO_START=0D + gEfiPciIoProtocolGuid # PROTOCOL TO_START=0D +=0D +[Pcd]=0D +# gOptionRomPkgTokenSpaceGuid.PcdDriverSupportedEfiVersion=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution=0D +=0D diff --git a/OvmfPkg/Bhyve/BhyveRfbDxe/ComponentName.c b/OvmfPkg/Bhyve/Bhyv= eRfbDxe/ComponentName.c new file mode 100644 index 0000000000..673cd235a1 --- /dev/null +++ b/OvmfPkg/Bhyve/BhyveRfbDxe/ComponentName.c @@ -0,0 +1,201 @@ +/** @file=0D +=0D +Copyright (c) 2020, Rebecca Cran <rebecca@...>=0D +Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>=0D +Portions copyright (c) 2010,Apple Inc. All rights reserved.<BR>=0D +=0D +SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +Module Name:=0D +=0D + ComponentName.c=0D +=0D +Abstract:=0D +=0D +**/=0D +=0D +#include "Gop.h"=0D +=0D +//=0D +// EFI Component Name Functions=0D +//=0D +EFI_STATUS=0D +EFIAPI=0D +EmuGopComponentNameGetDriverName (=0D + IN EFI_COMPONENT_NAME_PROTOCOL *This,=0D + IN CHAR8 *Language,=0D + OUT CHAR16 **DriverName=0D + );=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +EmuGopComponentNameGetControllerName (=0D + IN EFI_COMPONENT_NAME_PROTOCOL *This,=0D + IN EFI_HANDLE ControllerHandle,=0D + IN EFI_HANDLE ChildHandle O= PTIONAL,=0D + IN CHAR8 *Language,=0D + OUT CHAR16 **ControllerName=0D + );=0D +=0D +//=0D +// EFI Component Name Protocol=0D +//=0D +EFI_COMPONENT_NAME_PROTOCOL gEmuGopComponentName =3D {=0D + EmuGopComponentNameGetDriverName,=0D + EmuGopComponentNameGetControllerName,=0D + "eng"=0D +};=0D +=0D +//=0D +// EFI Component Name 2 Protocol=0D +//=0D +GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME2_PROTOCOL gEmuGopComponen= tName2 =3D {=0D + (EFI_COMPONENT_NAME2_GET_DRIVER_NAME) EmuGopComponentNameGetDriverName,= =0D + (EFI_COMPONENT_NAME2_GET_CONTROLLER_NAME) EmuGopComponentNameGetControll= erName,=0D + "en"=0D +};=0D +=0D +=0D +EFI_UNICODE_STRING_TABLE mEmuGopDriverNameTable[] =3D {=0D + { "eng", L"Emulator GOP Driver" },=0D + { NULL , NULL }=0D +};=0D +=0D +=0D +/**=0D + Retrieves a Unicode string that is the user readable name of the driver.= =0D +=0D + This function retrieves the user readable name of a driver in the form o= f a=0D + Unicode string. If the driver specified by This has a user readable name= in=0D + the language specified by Language, then a pointer to the driver name is= =0D + returned in DriverName, and EFI_SUCCESS is returned. If the driver speci= fied=0D + by This does not support the language specified by Language,=0D + then EFI_UNSUPPORTED is returned.=0D +=0D + @param This[in] A pointer to the EFI_COMPONENT_NAME2_PROTO= COL or=0D + EFI_COMPONENT_NAME_PROTOCOL instance.=0D +=0D + @param Language[in] A pointer to a Null-terminated ASCII strin= g=0D + array indicating the language. This is the= =0D + language of the driver name that the calle= r is=0D + requesting, and it must match one of the=0D + languages specified in SupportedLanguages.= The=0D + number of languages supported by a driver = is up=0D + to the driver writer. Language is specifie= d=0D + in RFC 4646 or ISO 639-2 language code for= mat.=0D +=0D + @param DriverName[out] A pointer to the Unicode string to return.= =0D + This Unicode string is the name of the=0D + driver specified by This in the language=0D + specified by Language.=0D +=0D + @retval EFI_SUCCESS The Unicode string for the Driver specifie= d by=0D + This and the language specified by Languag= e was=0D + returned in DriverName.=0D +=0D + @retval EFI_INVALID_PARAMETER Language is NULL.=0D +=0D + @retval EFI_INVALID_PARAMETER DriverName is NULL.=0D +=0D + @retval EFI_UNSUPPORTED The driver specified by This does not supp= ort=0D + the language specified by Language.=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +EmuGopComponentNameGetDriverName (=0D + IN EFI_COMPONENT_NAME_PROTOCOL *This,=0D + IN CHAR8 *Language,=0D + OUT CHAR16 **DriverName=0D + )=0D +{=0D + return LookupUnicodeString2 (=0D + Language,=0D + This->SupportedLanguages,=0D + mEmuGopDriverNameTable,=0D + DriverName,=0D + (BOOLEAN)(This =3D=3D &gEmuGopComponentName)=0D + );=0D +}=0D +=0D +=0D +/**=0D + Retrieves a Unicode string that is the user readable name of the control= ler=0D + that is being managed by a driver.=0D +=0D + This function retrieves the user readable name of the controller specifi= ed by=0D + ControllerHandle and ChildHandle in the form of a Unicode string. If the= =0D + driver specified by This has a user readable name in the language specif= ied by=0D + Language, then a pointer to the controller name is returned in Controlle= rName,=0D + and EFI_SUCCESS is returned. If the driver specified by This is not cur= rently=0D + managing the controller specified by ControllerHandle and ChildHandle,=0D + then EFI_UNSUPPORTED is returned. If the driver specified by This does = not=0D + support the language specified by Language, then EFI_UNSUPPORTED is retu= rned.=0D +=0D + @param This[in] A pointer to the EFI_COMPONENT_NAME2_PROTO= COL or=0D + EFI_COMPONENT_NAME_PROTOCOL instance.=0D +=0D + @param ControllerHandle[in] The handle of a controller that the driver= =0D + specified by This is managing. This handl= e=0D + specifies the controller whose name is to = be=0D + returned.=0D +=0D + @param ChildHandle[in] The handle of the child controller to retr= ieve=0D + the name of. This is an optional paramete= r that=0D + may be NULL. It will be NULL for device=0D + drivers. It will also be NULL for a bus d= rivers=0D + that wish to retrieve the name of the bus= =0D + controller. It will not be NULL for a bus= =0D + driver that wishes to retrieve the name of= a=0D + child controller.=0D +=0D + @param Language[in] A pointer to a Null-terminated ASCII strin= g=0D + array indicating the language. This is th= e=0D + language of the driver name that the calle= r is=0D + requesting, and it must match one of the=0D + languages specified in SupportedLanguages.= The=0D + number of languages supported by a driver = is up=0D + to the driver writer. Language is specifie= d in=0D + RFC 4646 or ISO 639-2 language code format= .=0D +=0D + @param ControllerName[out] A pointer to the Unicode string to return.= =0D + This Unicode string is the name of the=0D + controller specified by ControllerHandle a= nd=0D + ChildHandle in the language specified by=0D + Language from the point of view of the dri= ver=0D + specified by This.=0D +=0D + @retval EFI_SUCCESS The Unicode string for the user readable n= ame in=0D + the language specified by Language for the= =0D + driver specified by This was returned in=0D + DriverName.=0D +=0D + @retval EFI_INVALID_PARAMETER ControllerHandle is not a valid EFI_HANDLE= .=0D +=0D + @retval EFI_INVALID_PARAMETER ChildHandle is not NULL and it is not a va= lid=0D + EFI_HANDLE.=0D +=0D + @retval EFI_INVALID_PARAMETER Language is NULL.=0D +=0D + @retval EFI_INVALID_PARAMETER ControllerName is NULL.=0D +=0D + @retval EFI_UNSUPPORTED The driver specified by This is not curren= tly=0D + managing the controller specified by=0D + ControllerHandle and ChildHandle.=0D +=0D + @retval EFI_UNSUPPORTED The driver specified by This does not supp= ort=0D + the language specified by Language.=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +EmuGopComponentNameGetControllerName (=0D + IN EFI_COMPONENT_NAME_PROTOCOL *This,=0D + IN EFI_HANDLE ControllerHandle,=0D + IN EFI_HANDLE ChildHandle O= PTIONAL,=0D + IN CHAR8 *Language,=0D + OUT CHAR16 **ControllerName=0D + )=0D +{=0D + return EFI_UNSUPPORTED;=0D +}=0D diff --git a/OvmfPkg/Bhyve/BhyveRfbDxe/Gop.h b/OvmfPkg/Bhyve/BhyveRfbDxe/Go= p.h new file mode 100644 index 0000000000..d196a8e6cf --- /dev/null +++ b/OvmfPkg/Bhyve/BhyveRfbDxe/Gop.h @@ -0,0 +1,149 @@ +/*++ @file=0D +=0D +Copyright (c) 2020, Rebecca Cran <rebecca@...>=0D +Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>=0D +Portions copyright (c) 2010,Apple Inc. All rights reserved.<BR>=0D +=0D +SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#ifndef __UGA_H_=0D +#define __UGA_H_=0D +=0D +#include <Uefi.h>=0D +#include <Protocol/GraphicsOutput.h>=0D +#include <Protocol/PciIo.h>=0D +#include <Protocol/DriverSupportedEfiVersion.h>=0D +#include <Protocol/DevicePath.h>=0D +=0D +#include <Guid/EventGroup.h>=0D +=0D +#include <Library/DebugLib.h>=0D +#include <Library/BaseLib.h>=0D +#include <Library/PcdLib.h>=0D +#include <Library/UefiDriverEntryPoint.h>=0D +#include <Library/UefiLib.h>=0D +#include <Library/BaseMemoryLib.h>=0D +#include <Library/MemoryAllocationLib.h>=0D +#include <Library/UefiBootServicesTableLib.h>=0D +#include <Library/DevicePathLib.h>=0D +=0D +#include <IndustryStandard/Pci.h>=0D +=0D +#define GRAPHICS_OUTPUT_INVALID_MODE_NUMBER 0xffff=0D +=0D +typedef struct {=0D + UINT32 HorizontalResolution;=0D + UINT32 VerticalResolution;=0D + UINT32 ColorDepth;=0D + UINT32 RefreshRate;=0D +} GOP_MODE_DATA;=0D +=0D +#define PIXEL_RED_SHIFT 0=0D +#define PIXEL_GREEN_SHIFT 3=0D +#define PIXEL_BLUE_SHIFT 6=0D +=0D +#define PIXEL_RED_MASK (BIT7 | BIT6 | BIT5)=0D +#define PIXEL_GREEN_MASK (BIT4 | BIT3 | BIT2)=0D +#define PIXEL_BLUE_MASK (BIT1 | BIT0)=0D +=0D +#define PIXEL_TO_COLOR_BYTE(pixel, mask, shift) ((UINT8) ((pixel & mask) <= < shift))=0D +#define PIXEL_TO_RED_BYTE(pixel) PIXEL_TO_COLOR_BYTE(pixel, PIXEL_RED_MASK= , PIXEL_RED_SHIFT)=0D +#define PIXEL_TO_GREEN_BYTE(pixel) PIXEL_TO_COLOR_BYTE(pixel, PIXEL_GREEN_= MASK, PIXEL_GREEN_SHIFT)=0D +#define PIXEL_TO_BLUE_BYTE(pixel) PIXEL_TO_COLOR_BYTE(pixel, PIXEL_BLUE_MA= SK, PIXEL_BLUE_SHIFT)=0D +=0D +#define RGB_BYTES_TO_PIXEL(Red, Green, Blue) \=0D + (UINT8) ( (((Red) >> PIXEL_RED_SHIFT) & PIXEL_RED_MASK) | \=0D + (((Green) >> PIXEL_GREEN_SHIFT) & PIXEL_GREEN_MASK) | \=0D + (((Blue) >> PIXEL_BLUE_SHIFT) & PIXEL_BLUE_MASK) )=0D +=0D +#define PIXEL24_RED_MASK 0x00ff0000=0D +#define PIXEL24_GREEN_MASK 0x0000ff00=0D +#define PIXEL24_BLUE_MASK 0x000000ff=0D +=0D +extern EFI_DRIVER_BINDING_PROTOCOL gEmuGopDriverBinding;=0D +extern EFI_COMPONENT_NAME_PROTOCOL gEmuGopComponentName;=0D +=0D +#define EMU_UGA_CLASS_NAME L"EmuGopWindow"=0D +=0D +#define GOP_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('G', 'o', 'p', 'N')=0D +typedef struct {=0D + UINT64 Signature;=0D +=0D + EFI_HANDLE Handle;=0D + EFI_PCI_IO_PROTOCOL *PciIo;=0D + EFI_GRAPHICS_OUTPUT_PROTOCOL GraphicsOutput;=0D + EFI_DEVICE_PATH_PROTOCOL *GopDevicePath;=0D +=0D + EFI_UNICODE_STRING_TABLE *ControllerNameTable;=0D +=0D + //=0D + // GOP Private Data for QueryMode ()=0D + //=0D + GOP_MODE_DATA *ModeData;=0D +=0D + UINT64 FbAddr;=0D + UINT32 FbSize;=0D +} GOP_PRIVATE_DATA;=0D +=0D +=0D +#define GOP_PRIVATE_DATA_FROM_THIS(a) \=0D + CR(a, GOP_PRIVATE_DATA, GraphicsOutput, GOP_PRIVATE_DATA_SIGNATUR= E)=0D +=0D +typedef struct {=0D + UINT32 FbSize;=0D + UINT16 Width;=0D + UINT16 Height;=0D + UINT16 Depth;=0D + UINT16 RefreshRate;=0D +} BHYVE_FBUF_MEMREGS;=0D +=0D +//=0D +// Global Protocol Variables=0D +//=0D +extern EFI_DRIVER_BINDING_PROTOCOL gEmuGopDriverBinding;=0D +extern EFI_COMPONENT_NAME_PROTOCOL gEmuGopComponentName;=0D +extern EFI_COMPONENT_NAME2_PROTOCOL gEmuGopComponentName2;=0D +=0D +//=0D +// Gop Hardware abstraction internal worker functions=0D +//=0D +EFI_STATUS=0D +EmuGopConstructor (=0D + IN GOP_PRIVATE_DATA *Private=0D + );=0D +=0D +EFI_STATUS=0D +EmuGopDestructor (=0D + IN GOP_PRIVATE_DATA *Private=0D + );=0D +=0D +VOID=0D +EFIAPI=0D +ShutdownGopEvent (=0D + IN EFI_EVENT Event,=0D + IN VOID *Context=0D + );=0D +=0D +VOID=0D +BhyveSetGraphicsMode (=0D + GOP_PRIVATE_DATA *Private,=0D + UINT16 Width,=0D + UINT16 Height,=0D + UINT16 Depth=0D + );=0D +=0D +VOID=0D +BhyveGetMemregs (=0D + GOP_PRIVATE_DATA *Private,=0D + BHYVE_FBUF_MEMREGS *Memregs=0D + );=0D +=0D +VOID=0D +InstallVbeShim (=0D + IN CONST CHAR16 *CardName,=0D + IN EFI_PHYSICAL_ADDRESS FrameBufferBase=0D + );=0D +=0D +#endif=0D diff --git a/OvmfPkg/Bhyve/BhyveRfbDxe/GopDriver.c b/OvmfPkg/Bhyve/BhyveRfb= Dxe/GopDriver.c new file mode 100644 index 0000000000..bab4fbda53 --- /dev/null +++ b/OvmfPkg/Bhyve/BhyveRfbDxe/GopDriver.c @@ -0,0 +1,543 @@ +/*++ @file=0D +=0D +Copyright (c) 2020, Rebecca Cran <rebecca@...>=0D +Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>=0D +Portions copyright (c) 2010,Apple Inc. All rights reserved.<BR>=0D +=0D +SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include "Gop.h"=0D +#include <IndustryStandard/Acpi.h>=0D +=0D +STATIC VOID=0D +BhyveGetGraphicsMode (=0D + EFI_PCI_IO_PROTOCOL *PciIo,=0D + UINT16 *Width,=0D + UINT16 *Height,=0D + UINT16 *Depth=0D + );=0D +=0D +=0D +/**=0D + Tests to see if this driver supports a given controller. If a child devi= ce is provided,=0D + it further tests to see if this driver supports creating a handle for th= e specified child device.=0D +=0D + This function checks to see if the driver specified by This supports the= device specified by=0D + ControllerHandle. Drivers will typically use the device path attached to= =0D + ControllerHandle and/or the services from the bus I/O abstraction attach= ed to=0D + ControllerHandle to determine if the driver supports ControllerHandle. T= his function=0D + may be called many times during platform initialization. In order to red= uce boot times, the tests=0D + performed by this function must be very small, and take as little time a= s possible to execute. This=0D + function must not change the state of any hardware devices, and this fun= ction must be aware that the=0D + device specified by ControllerHandle may already be managed by the same = driver or a=0D + different driver. This function must match its calls to AllocatePages() = with FreePages(),=0D + AllocatePool() with FreePool(), and OpenProtocol() with CloseProtocol().= =0D + Because ControllerHandle may have been previously started by the same dr= iver, if a protocol is=0D + already in the opened state, then it must not be closed with CloseProtoc= ol(). This is required=0D + to guarantee the state of ControllerHandle is not modified by this funct= ion.=0D +=0D + @param[in] This A pointer to the EFI_DRIVER_BINDING_PRO= TOCOL instance.=0D + @param[in] ControllerHandle The handle of the controller to test. T= his handle=0D + must support a protocol interface that = supplies=0D + an I/O abstraction to the driver.=0D + @param[in] RemainingDevicePath A pointer to the remaining portion of a= device path. This=0D + parameter is ignored by device drivers,= and is optional for bus=0D + drivers. For bus drivers, if this param= eter is not NULL, then=0D + the bus driver must determine if the bu= s controller specified=0D + by ControllerHandle and the child contr= oller specified=0D + by RemainingDevicePath are both support= ed by this=0D + bus driver.=0D +=0D + @retval EFI_SUCCESS The device specified by ControllerHandl= e and=0D + RemainingDevicePath is supported by the= driver specified by This.=0D + @retval EFI_ALREADY_STARTED The device specified by ControllerHandl= e and=0D + RemainingDevicePath is already being ma= naged by the driver=0D + specified by This.=0D + @retval EFI_ACCESS_DENIED The device specified by ControllerHandl= e and=0D + RemainingDevicePath is already being ma= naged by a different=0D + driver or an application that requires = exclusive access.=0D + Currently not implemented.=0D + @retval EFI_UNSUPPORTED The device specified by ControllerHandl= e and=0D + RemainingDevicePath is not supported by= the driver specified by This.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +EmuGopDriverBindingSupported (=0D + IN EFI_DRIVER_BINDING_PROTOCOL *This,=0D + IN EFI_HANDLE Handle,=0D + IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath=0D + )=0D +{=0D + EFI_STATUS Status;=0D + EFI_PCI_IO_PROTOCOL *PciIo;=0D + PCI_TYPE00 Pci;=0D + UINT16 Width, Height, Depth;=0D +=0D + //=0D + // Open the IO Abstraction(s) needed to perform the supported test=0D + //=0D + Status =3D gBS->OpenProtocol (=0D + Handle,=0D + &gEfiPciIoProtocolGuid,=0D + (VOID **) &PciIo,=0D + This->DriverBindingHandle,=0D + Handle,=0D + EFI_OPEN_PROTOCOL_BY_DRIVER=0D + );=0D + if (EFI_ERROR (Status)) {=0D + return Status;=0D + }=0D +=0D + //=0D + // See if this is a PCI Framebuffer Controller by looking at the Command= register and=0D + // Class Code Register=0D + //=0D + Status =3D PciIo->Pci.Read (=0D + PciIo,=0D + EfiPciIoWidthUint32,=0D + PCI_BAR_IDX0,=0D + sizeof (Pci) / sizeof (UINT32),=0D + &Pci=0D + );=0D + if (EFI_ERROR (Status)) {=0D + Status =3D EFI_UNSUPPORTED;=0D + goto Done;=0D + }=0D +=0D + Status =3D EFI_UNSUPPORTED;=0D + if (Pci.Hdr.VendorId =3D=3D 0xFB5D && Pci.Hdr.DeviceId =3D=3D 0x40FB) {= =0D + DEBUG((DEBUG_INFO, "BHYVE framebuffer device detected\n"));=0D + Status =3D EFI_SUCCESS;=0D +=0D + BhyveGetGraphicsMode(PciIo, &Width, &Height, &Depth);=0D + PcdSet32S (PcdVideoHorizontalResolution, Width);=0D + PcdSet32S (PcdVideoVerticalResolution, Height);=0D + }=0D +=0D +Done:=0D + //=0D + // Close the PCI I/O Protocol=0D + //=0D + gBS->CloseProtocol (=0D + Handle,=0D + &gEfiPciIoProtocolGuid,=0D + This->DriverBindingHandle,=0D + Handle=0D + );=0D +=0D + return Status;=0D +}=0D +=0D +=0D +/**=0D + Starts a device controller or a bus controller.=0D +=0D + The Start() function is designed to be invoked from the EFI boot service= ConnectController().=0D + As a result, much of the error checking on the parameters to Start() has= been moved into this=0D + common boot service. It is legal to call Start() from other locations,=0D + but the following calling restrictions must be followed, or the system b= ehavior will not be deterministic.=0D + 1. ControllerHandle must be a valid EFI_HANDLE.=0D + 2. If RemainingDevicePath is not NULL, then it must be a pointer to a na= turally aligned=0D + EFI_DEVICE_PATH_PROTOCOL.=0D + 3. Prior to calling Start(), the Supported() function for the driver spe= cified by This must=0D + have been called with the same calling parameters, and Supported() mu= st have returned EFI_SUCCESS.=0D +=0D + @param[in] This A pointer to the EFI_DRIVER_BINDING_PRO= TOCOL instance.=0D + @param[in] ControllerHandle The handle of the controller to start. = This handle=0D + must support a protocol interface that = supplies=0D + an I/O abstraction to the driver.=0D + @param[in] RemainingDevicePath A pointer to the remaining portion of a= device path. This=0D + parameter is ignored by device drivers,= and is optional for bus=0D + drivers. For a bus driver, if this para= meter is NULL, then handles=0D + for all the children of Controller are = created by this driver.=0D + If this parameter is not NULL and the f= irst Device Path Node is=0D + not the End of Device Path Node, then o= nly the handle for the=0D + child device specified by the first Dev= ice Path Node of=0D + RemainingDevicePath is created by this = driver.=0D + If the first Device Path Node of Remain= ingDevicePath is=0D + the End of Device Path Node, no child h= andle is created by this=0D + driver.=0D +=0D + @retval EFI_SUCCESS The device was started.=0D + @retval EFI_DEVICE_ERROR The device could not be started due to = a device error.Currently not implemented.=0D + @retval EFI_OUT_OF_RESOURCES The request could not be completed due = to a lack of resources.=0D + @retval Others The driver failded to start the device.= =0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +EmuGopDriverBindingStart (=0D + IN EFI_DRIVER_BINDING_PROTOCOL *This,=0D + IN EFI_HANDLE Handle,=0D + IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath=0D + )=0D +{=0D + BHYVE_FBUF_MEMREGS Memregs;=0D + GOP_PRIVATE_DATA *Private;=0D + EFI_STATUS Status;=0D + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *MmioDesc;=0D +=0D + //=0D + // Allocate Private context data for SGO inteface.=0D + //=0D + Private =3D NULL;=0D + Status =3D gBS->AllocatePool (=0D + EfiBootServicesData,=0D + sizeof (GOP_PRIVATE_DATA),=0D + (VOID **)&Private=0D + );=0D + if (EFI_ERROR (Status)) {=0D + goto Done;=0D + }=0D +=0D + // Set up context record=0D + //=0D + Private->Signature =3D GOP_PRIVATE_DATA_SIGNATURE;=0D + Private->Handle =3D Handle;=0D + Private->ControllerNameTable =3D NULL;=0D +=0D + //=0D + // Open PCI I/O Protocol=0D + //=0D + Status =3D gBS->OpenProtocol (=0D + Handle,=0D + &gEfiPciIoProtocolGuid,=0D + (VOID **) &Private->PciIo,=0D + This->DriverBindingHandle,=0D + Handle,=0D + EFI_OPEN_PROTOCOL_BY_DRIVER=0D + );=0D + if (EFI_ERROR (Status)) {=0D + goto Done;=0D + }=0D +=0D + //=0D + // Check if fbuf mmio BAR is present=0D + //=0D + MmioDesc =3D NULL;=0D + Status =3D Private->PciIo->GetBarAttributes (=0D + Private->PciIo,=0D + PCI_BAR_IDX0,=0D + NULL,=0D + (VOID**) &MmioDesc=0D + );=0D + if (EFI_ERROR (Status) ||=0D + MmioDesc->ResType !=3D ACPI_ADDRESS_SPACE_TYPE_MEM) {=0D + DEBUG ((DEBUG_INFO, "BHYVE GOP: No mmio bar\n"));=0D + } else {=0D + DEBUG ((DEBUG_INFO, "BHYVE GOP: Using mmio bar @ 0x%lx\n",=0D + MmioDesc->AddrRangeMin));=0D + BhyveGetMemregs(Private, &Memregs);=0D + Private->FbSize =3D Memregs.FbSize;=0D + }=0D + if (MmioDesc !=3D NULL) {=0D + FreePool (MmioDesc);=0D + }=0D + if (EFI_ERROR (Status)) {=0D + goto Done;=0D + }=0D +=0D + //=0D + // Check if fbuf frame-buffer BAR is present=0D + //=0D + MmioDesc =3D NULL;=0D + Status =3D Private->PciIo->GetBarAttributes (=0D + Private->PciIo,=0D + PCI_BAR_IDX1,=0D + NULL,=0D + (VOID**) &MmioDesc=0D + );=0D + if (EFI_ERROR (Status) ||=0D + MmioDesc->ResType !=3D ACPI_ADDRESS_SPACE_TYPE_MEM) {=0D + DEBUG ((DEBUG_INFO, "BHYVE GOP: No frame-buffer bar\n"));=0D + } else {=0D + DEBUG ((DEBUG_INFO, "BHYVE GOP: Using frame-buffer bar @ 0x%lx\n",=0D + MmioDesc->AddrRangeMin));=0D + Private->FbAddr =3D MmioDesc->AddrRangeMin;=0D + // XXX assert BAR is >=3D size=0D + }=0D +=0D + if (MmioDesc !=3D NULL) {=0D + FreePool (MmioDesc);=0D + }=0D + if (EFI_ERROR (Status)) {=0D + goto Done;=0D + }=0D +=0D + DEBUG ((DEBUG_INFO, "BHYVE GOP: Framebuf addr 0x%lx, size %x\n",=0D + Private->FbAddr, Private->FbSize));=0D +=0D + Status =3D EmuGopConstructor (Private);=0D + if (EFI_ERROR (Status)) {=0D + goto Done;=0D + }=0D +=0D + //=0D + // Publish the Gop interface to the world=0D + //=0D + Status =3D gBS->InstallMultipleProtocolInterfaces (=0D + &Private->Handle,=0D + &gEfiGraphicsOutputProtocolGuid, &Private->GraphicsOu= tput,=0D + NULL=0D + );=0D +=0D + DEBUG((DEBUG_INFO, "BHYVE framebuffer device started\n"));=0D +=0D + //=0D + // Install int10 handler=0D + //=0D +#ifndef CSM_ENABLE=0D + InstallVbeShim (L"Framebuffer", Private->FbAddr);=0D +#endif=0D +=0D +Done:=0D + if (EFI_ERROR (Status)) {=0D + if (Private !=3D NULL) {=0D + //=0D + // On Error Free back private data=0D + //=0D + if (Private->ControllerNameTable !=3D NULL) {=0D + FreeUnicodeStringTable (Private->ControllerNameTable);=0D + }=0D +=0D + gBS->FreePool (Private);=0D + }=0D + }=0D +=0D + return Status;=0D +}=0D +=0D +=0D +=0D +/**=0D + Stops a device controller or a bus controller.=0D +=0D + The Stop() function is designed to be invoked from the EFI boot service = DisconnectController().=0D + As a result, much of the error checking on the parameters to Stop() has = been moved=0D + into this common boot service. It is legal to call Stop() from other loc= ations,=0D + but the following calling restrictions must be followed, or the system b= ehavior will not be deterministic.=0D + 1. ControllerHandle must be a valid EFI_HANDLE that was used on a previo= us call to this=0D + same driver's Start() function.=0D + 2. The first NumberOfChildren handles of ChildHandleBuffer must all be a= valid=0D + EFI_HANDLE. In addition, all of these handles must have been created = in this driver's=0D + Start() function, and the Start() function must have called OpenProto= col() on=0D + ControllerHandle with an Attribute of EFI_OPEN_PROTOCOL_BY_CHILD_CONT= ROLLER.=0D +=0D + @param[in] This A pointer to the EFI_DRIVER_BINDING_PROTOC= OL instance.=0D + @param[in] ControllerHandle A handle to the device being stopped. The = handle must=0D + support a bus specific I/O protocol for th= e driver=0D + to use to stop the device.=0D + @param[in] NumberOfChildren The number of child device handles in Chil= dHandleBuffer.=0D + @param[in] ChildHandleBuffer An array of child handles to be freed. May= be NULL=0D + if NumberOfChildren is 0.=0D +=0D + @retval EFI_SUCCESS The device was stopped.=0D + @retval EFI_DEVICE_ERROR The device could not be stopped due to a d= evice error.=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +EmuGopDriverBindingStop (=0D + IN EFI_DRIVER_BINDING_PROTOCOL *This,=0D + IN EFI_HANDLE Handle,=0D + IN UINTN NumberOfChildren,=0D + IN EFI_HANDLE *ChildHandleBuffer=0D + )=0D +{=0D + EFI_GRAPHICS_OUTPUT_PROTOCOL *GraphicsOutput;=0D + EFI_STATUS Status;=0D + GOP_PRIVATE_DATA *Private;=0D +=0D + DEBUG((DEBUG_INFO, "BHYVE framebuffer device stopping\n"));=0D +=0D + Status =3D gBS->OpenProtocol (=0D + Handle,=0D + &gEfiGraphicsOutputProtocolGuid,=0D + (VOID **)&GraphicsOutput,=0D + This->DriverBindingHandle,=0D + Handle,=0D + EFI_OPEN_PROTOCOL_GET_PROTOCOL=0D + );=0D + if (EFI_ERROR (Status)) {=0D + //=0D + // If the GOP interface does not exist the driver is not started=0D + //=0D + return EFI_NOT_STARTED;=0D + }=0D +=0D + //=0D + // Get our private context information=0D + //=0D + Private =3D GOP_PRIVATE_DATA_FROM_THIS (GraphicsOutput);=0D +=0D + //=0D + // Remove the SGO interface from the system=0D + //=0D + Status =3D gBS->UninstallMultipleProtocolInterfaces (=0D + Private->Handle,=0D + &gEfiGraphicsOutputProtocolGuid, &Private->GraphicsOu= tput,=0D + NULL=0D + );=0D + if (!EFI_ERROR (Status)) {=0D + //=0D + // Shutdown the hardware=0D + //=0D + Status =3D EmuGopDestructor (Private);=0D + if (EFI_ERROR (Status)) {=0D + return EFI_DEVICE_ERROR;=0D + }=0D +=0D + gBS->CloseProtocol (=0D + Handle,=0D + &gEfiPciIoProtocolGuid,=0D + This->DriverBindingHandle,=0D + Private->Handle=0D + );=0D +=0D + //=0D + // Free our instance data=0D + //=0D + FreeUnicodeStringTable (Private->ControllerNameTable);=0D +=0D + gBS->FreePool (Private);=0D +=0D + }=0D +=0D + return Status;=0D +}=0D +=0D +=0D +///=0D +/// This protocol provides the services required to determine if a driver = supports a given controller.=0D +/// If a controller is supported, then it also provides routines to start = and stop the controller.=0D +///=0D +EFI_DRIVER_BINDING_PROTOCOL gEmuGopDriverBinding =3D {=0D + EmuGopDriverBindingSupported,=0D + EmuGopDriverBindingStart,=0D + EmuGopDriverBindingStop,=0D + 0xa,=0D + NULL,=0D + NULL=0D +};=0D +=0D +=0D +=0D +/**=0D + The user Entry Point for module EmuGop. The user code starts with this f= unction.=0D +=0D + @param[in] ImageHandle The firmware allocated handle for the EFI imag= e.=0D + @param[in] SystemTable A pointer to the EFI System Table.=0D +=0D + @retval EFI_SUCCESS The entry point is executed successfully.=0D + @retval other Some error occurs when executing this entry po= int.=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +InitializeEmuGop (=0D + IN EFI_HANDLE ImageHandle,=0D + IN EFI_SYSTEM_TABLE *SystemTable=0D + )=0D +{=0D + EFI_STATUS Status;=0D +=0D + Status =3D EfiLibInstallDriverBindingComponentName2 (=0D + ImageHandle,=0D + SystemTable,=0D + &gEmuGopDriverBinding,=0D + ImageHandle,=0D + &gEmuGopComponentName,=0D + &gEmuGopComponentName2=0D + );=0D + ASSERT_EFI_ERROR (Status);=0D +=0D +=0D + return Status;=0D +}=0D +=0D +STATIC VOID=0D +BhyveGetGraphicsMode (=0D + EFI_PCI_IO_PROTOCOL *PciIo,=0D + UINT16 *Width,=0D + UINT16 *Height,=0D + UINT16 *Depth=0D + )=0D +{=0D + BHYVE_FBUF_MEMREGS BhyveRegs;=0D + UINT64 Offset;=0D + EFI_STATUS Status;=0D +=0D +=0D + Offset =3D (UINT64)&BhyveRegs.Width - (UINT64)&BhyveRegs;=0D +=0D + Status =3D PciIo->Mem.Read (=0D + PciIo,=0D + EfiPciIoWidthUint16,=0D + PCI_BAR_IDX0,=0D + Offset,=0D + 3,=0D + &BhyveRegs.Width=0D + );=0D +=0D + *Width =3D BhyveRegs.Width;=0D + *Height =3D BhyveRegs.Height;=0D + *Depth =3D BhyveRegs.Depth;=0D +=0D + DEBUG ((DEBUG_INFO, "BHYVE Get Graphics Mode: w %d, h %d\n", *Width, *He= ight));=0D +=0D + ASSERT_EFI_ERROR (Status);=0D +}=0D +=0D +VOID=0D +BhyveSetGraphicsMode (=0D + GOP_PRIVATE_DATA *Private,=0D + UINT16 Width,=0D + UINT16 Height,=0D + UINT16 Depth=0D + )=0D +{=0D + BHYVE_FBUF_MEMREGS BhyveRegs;=0D + UINT64 Offset;=0D + EFI_STATUS Status;=0D +=0D + DEBUG ((DEBUG_INFO, "BHYVE Set Graphics Mode: w %d, h %d\n", Width, Heig= ht));=0D +=0D + BhyveRegs.Width =3D Width;=0D + BhyveRegs.Height =3D Height;=0D + BhyveRegs.Depth =3D Depth;=0D + Offset =3D (UINT64)&BhyveRegs.Width - (UINT64)&BhyveRegs;=0D +=0D + Status =3D Private->PciIo->Mem.Write (=0D + Private->PciIo,=0D + EfiPciIoWidthUint16,=0D + PCI_BAR_IDX0,=0D + Offset,=0D + 3,=0D + &BhyveRegs.Width=0D + );=0D + ASSERT_EFI_ERROR (Status);=0D +}=0D +=0D +VOID=0D +BhyveGetMemregs (=0D + GOP_PRIVATE_DATA *Private,=0D + BHYVE_FBUF_MEMREGS *Memregs=0D + )=0D +{=0D + EFI_STATUS Status;=0D +=0D + Status =3D Private->PciIo->Mem.Read (=0D + Private->PciIo,=0D + EfiPciIoWidthUint32,=0D + PCI_BAR_IDX0,=0D + 0,=0D + 3,=0D + Memregs=0D + );=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + DEBUG ((DEBUG_INFO, "BHYVE Get Memregs, size %d width %d height %d\n",=0D + Memregs->FbSize, Memregs->Width, Memregs->Height));=0D +}=0D diff --git a/OvmfPkg/Bhyve/BhyveRfbDxe/GopScreen.c b/OvmfPkg/Bhyve/BhyveRfb= Dxe/GopScreen.c new file mode 100644 index 0000000000..0760ffb722 --- /dev/null +++ b/OvmfPkg/Bhyve/BhyveRfbDxe/GopScreen.c @@ -0,0 +1,393 @@ +/*++ @file=0D +=0D +Copyright (c) 2020, Rebecca Cran <rebecca@...>=0D +Copyright (c) 2015, Nahanni Systems, Inc.=0D +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>=0D +Portions copyright (c) 2010 - 2011, Apple Inc. All rights reserved.=0D +=0D +SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +Module Name:=0D +=0D + EmuGopScreen.c=0D +=0D +Abstract:=0D +=0D + This file produces the graphics abstration of UGA. It is called by=0D + EmuGopDriver.c file which deals with the EFI 1.1 driver model.=0D + This file just does graphics.=0D +=0D +**/=0D +=0D +#include "Gop.h"=0D +#include <Library/FrameBufferBltLib.h>=0D +=0D +=0D +EFI_EVENT mGopScreenExitBootServicesEvent;=0D +=0D +GOP_MODE_DATA mGopModeData[] =3D {=0D + { 0, 0, 32, 0 }, // Filled in with user-spec'd resolution=0D + { 1024, 768, 32, 0 },=0D + { 800, 600, 32, 0 },=0D + { 640, 480, 32, 0 }=0D + };=0D +=0D +STATIC=0D +VOID=0D +BhyveGopCompleteModeInfo (=0D + IN GOP_MODE_DATA *ModeData,=0D + OUT EFI_GRAPHICS_OUTPUT_MODE_INFORMATION *Info=0D + )=0D +{=0D + Info->Version =3D 0;=0D + if (ModeData->ColorDepth =3D=3D 8) {=0D + Info->PixelFormat =3D PixelBitMask;=0D + Info->PixelInformation.RedMask =3D PIXEL_RED_MASK;=0D + Info->PixelInformation.GreenMask =3D PIXEL_GREEN_MASK;=0D + Info->PixelInformation.BlueMask =3D PIXEL_BLUE_MASK;=0D + Info->PixelInformation.ReservedMask =3D 0;=0D + } else if (ModeData->ColorDepth =3D=3D 24) {=0D + Info->PixelFormat =3D PixelBitMask;=0D + Info->PixelInformation.RedMask =3D PIXEL24_RED_MASK;=0D + Info->PixelInformation.GreenMask =3D PIXEL24_GREEN_MASK;=0D + Info->PixelInformation.BlueMask =3D PIXEL24_BLUE_MASK;=0D + Info->PixelInformation.ReservedMask =3D 0;=0D + } else if (ModeData->ColorDepth =3D=3D 32) {=0D + DEBUG ((DEBUG_INFO, "%dx%d PixelBlueGreenRedReserved8BitPerColor\n",=0D + ModeData->HorizontalResolution, ModeData->VerticalResolution));=0D + Info->PixelFormat =3D PixelBlueGreenRedReserved8BitPerColor;=0D + }=0D + Info->PixelsPerScanLine =3D Info->HorizontalResolution;=0D +}=0D +=0D +=0D +/**=0D + Returns information for an available graphics mode that the graphics dev= ice=0D + and the set of active video output devices supports.=0D +=0D + @param This The EFI_GRAPHICS_OUTPUT_PROTOCOL instance.= =0D + @param ModeNumber The mode number to return information on.= =0D + @param SizeOfInfo A pointer to the size, in bytes, of the In= fo buffer.=0D + @param Info A pointer to callee allocated buffer that = returns information about ModeNumber.=0D +=0D + @retval EFI_SUCCESS Mode information returned.=0D + @retval EFI_BUFFER_TOO_SMALL The Info buffer was too small.=0D + @retval EFI_DEVICE_ERROR A hardware error occurred trying to retrie= ve the video mode.=0D + @retval EFI_NOT_STARTED Video display is not initialized. Call Set= Mode ()=0D + @retval EFI_INVALID_PARAMETER One of the input args was NULL.=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +EmuGopQuerytMode (=0D + IN EFI_GRAPHICS_OUTPUT_PROTOCOL *This,=0D + IN UINT32 ModeNumber,=0D + OUT UINTN *SizeOfInfo,=0D + OUT EFI_GRAPHICS_OUTPUT_MODE_INFORMATION **Info=0D + )=0D +{=0D + GOP_PRIVATE_DATA *Private;=0D + GOP_MODE_DATA *ModeData;=0D +=0D + Private =3D GOP_PRIVATE_DATA_FROM_THIS (This);=0D +=0D + if (Info =3D=3D NULL || SizeOfInfo =3D=3D NULL || (UINTN) ModeNumber >= =3D This->Mode->MaxMode) {=0D + return EFI_INVALID_PARAMETER;=0D + }=0D +=0D + *Info =3D AllocatePool (sizeof (EFI_GRAPHICS_OUTPUT_MODE_INFORMATION));= =0D + if (*Info =3D=3D NULL) {=0D + return EFI_OUT_OF_RESOURCES;=0D + }=0D +=0D + *SizeOfInfo =3D sizeof (EFI_GRAPHICS_OUTPUT_MODE_INFORMATION);=0D +=0D + ModeData =3D &Private->ModeData[ModeNumber];=0D + (*Info)->Version =3D 0;=0D + (*Info)->HorizontalResolution =3D ModeData->HorizontalResolution;=0D + (*Info)->VerticalResolution =3D ModeData->VerticalResolution;=0D + (*Info)->PixelFormat =3D PixelBitMask;=0D + (*Info)->PixelsPerScanLine =3D (*Info)->HorizontalResolution;=0D + BhyveGopCompleteModeInfo(ModeData, *Info);=0D + return EFI_SUCCESS;=0D +}=0D +=0D +=0D +=0D +/**=0D + Set the video device into the specified mode and clears the visible port= ions of=0D + the output display to black.=0D +=0D + @param This The EFI_GRAPHICS_OUTPUT_PROTOCOL instance.=0D + @param ModeNumber Abstraction that defines the current video mod= e.=0D +=0D + @retval EFI_SUCCESS The graphics mode specified by ModeNumber was = selected.=0D + @retval EFI_DEVICE_ERROR The device had an error and could not complete= the request.=0D + @retval EFI_UNSUPPORTED ModeNumber is not supported by this device.=0D +=0D +**/=0D +=0D +FRAME_BUFFER_CONFIGURE *fbconf;=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +EmuGopSetMode (=0D + IN EFI_GRAPHICS_OUTPUT_PROTOCOL *This,=0D + IN UINT32 ModeNumber=0D + )=0D +{=0D + GOP_PRIVATE_DATA *Private;=0D + GOP_MODE_DATA *ModeData;=0D + EFI_GRAPHICS_OUTPUT_BLT_PIXEL Fill;=0D + EFI_GRAPHICS_OUTPUT_MODE_INFORMATION *Info;=0D +=0D + UINTN confsize =3D 0;=0D + fbconf =3D NULL;=0D +=0D + Private =3D GOP_PRIVATE_DATA_FROM_THIS (This);=0D +=0D + if (ModeNumber >=3D This->Mode->MaxMode) {=0D + // Tell bhyve that we are switching out of vesa=0D + BhyveSetGraphicsMode(Private, 0, 0, 0);=0D + return EFI_UNSUPPORTED;=0D + }=0D +=0D + DEBUG ((DEBUG_INFO, "BHYVE GopSetMode %d\n", ModeNumber));=0D +=0D + ModeData =3D &Private->ModeData[ModeNumber];=0D + This->Mode->Mode =3D ModeNumber;=0D + Private->GraphicsOutput.Mode->Info->HorizontalResolution =3D ModeData->H= orizontalResolution;=0D + Private->GraphicsOutput.Mode->Info->VerticalResolution =3D ModeData->Ver= ticalResolution;=0D + Private->GraphicsOutput.Mode->Info->PixelsPerScanLine =3D ModeData->Hori= zontalResolution;=0D +=0D + Info =3D This->Mode->Info;=0D + BhyveGopCompleteModeInfo(ModeData, Info);=0D +=0D + This->Mode->Info->HorizontalResolution =3D ModeData->HorizontalResolutio= n;=0D + This->Mode->Info->VerticalResolution =3D ModeData->VerticalResolution;=0D + This->Mode->SizeOfInfo =3D sizeof(EFI_GRAPHICS_OUTPUT_MODE_INFORMATION);= =0D + This->Mode->FrameBufferBase =3D Private->GraphicsOutput.Mode->FrameBuffe= rBase;=0D +=0D + /*=0D + This->Mode->FrameBufferSize =3D Info->HorizontalResolution * Info->Verti= calResolution=0D + * ((ModeData->ColorDepth + 7) / 8);=0D + */=0D + This->Mode->FrameBufferSize =3D Private->FbSize;=0D + DEBUG ((DEBUG_INFO, "BHYVE GOP FrameBufferBase: 0x%x, FrameBufferSize: 0= x%x\n", This->Mode->FrameBufferBase, This->Mode->FrameBufferSize));=0D +=0D + BhyveSetGraphicsMode(Private, (UINT16)ModeData->HorizontalResolution, (U= INT16)ModeData->VerticalResolution, (UINT16)ModeData->ColorDepth);=0D +=0D + RETURN_STATUS ret =3D FrameBufferBltConfigure (=0D + (VOID*)(UINTN) This->Mode->FrameBufferBase,=0D + This->Mode->Info, fbconf, &confsize=0D + );=0D + if (ret =3D=3D EFI_BUFFER_TOO_SMALL || ret =3D=3D EFI_INVALID_PARAMETER)= {=0D + fbconf =3D AllocatePool(confsize);=0D + ret =3D FrameBufferBltConfigure(=0D + (VOID*)(UINTN)This->Mode->FrameBufferBase,=0D + This->Mode->Info, fbconf, &confsize);=0D + ASSERT(ret =3D=3D EFI_SUCCESS);=0D + }=0D +=0D + Fill.Red =3D 0;=0D + Fill.Green =3D 0;=0D + Fill.Blue =3D 0;=0D + This->Blt (=0D + This,=0D + &Fill,=0D + EfiBltVideoFill,=0D + 0,=0D + 0,=0D + 0,=0D + 0,=0D + ModeData->HorizontalResolution,=0D + ModeData->VerticalResolution,=0D + ModeData->HorizontalResolution * sizeof (EFI_GRAPHICS_OUTPUT_BLT= _PIXEL)=0D + );=0D + return EFI_SUCCESS;=0D +}=0D +=0D +=0D +=0D +/**=0D + Blt a rectangle of pixels on the graphics screen. Blt stands for BLock T= ransfer.=0D +=0D + @param This Protocol instance pointer.=0D + @param BltBuffer Buffer containing data to blit into video buffer. T= his=0D + buffer has a size of Width*Height*sizeof(EFI_GRAPHI= CS_OUTPUT_BLT_PIXEL)=0D + @param BltOperation Operation to perform on BlitBuffer and video memory= =0D + @param SourceX X coordinate of source for the BltBuffer.=0D + @param SourceY Y coordinate of source for the BltBuffer.=0D + @param DestinationX X coordinate of destination for the BltBuffer.=0D + @param DestinationY Y coordinate of destination for the BltBuffer.=0D + @param Width Width of rectangle in BltBuffer in pixels.=0D + @param Height Hight of rectangle in BltBuffer in pixels.=0D + @param Delta OPTIONAL=0D +=0D + @retval EFI_SUCCESS The Blt operation completed.=0D + @retval EFI_INVALID_PARAMETER BltOperation is not valid.=0D + @retval EFI_DEVICE_ERROR A hardware error occured writting to the v= ideo buffer.=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +EmuGopBlt (=0D + IN EFI_GRAPHICS_OUTPUT_PROTOCOL *This,=0D + IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL *BltBuffer, OPTIONAL=0D + IN EFI_GRAPHICS_OUTPUT_BLT_OPERATION BltOperation,=0D + IN UINTN SourceX,=0D + IN UINTN SourceY,=0D + IN UINTN DestinationX,=0D + IN UINTN DestinationY,=0D + IN UINTN Width,=0D + IN UINTN Height,=0D + IN UINTN Delta OPTIONAL=0D + )=0D +{=0D + EFI_TPL OriginalTPL;=0D + EFI_STATUS Status;=0D +=0D + if ((UINT32)BltOperation >=3D EfiGraphicsOutputBltOperationMax) {=0D + return EFI_INVALID_PARAMETER;=0D + }=0D +=0D + if (Width =3D=3D 0 || Height =3D=3D 0) {=0D + return EFI_INVALID_PARAMETER;=0D + }=0D +=0D + //=0D + // We have to raise to TPL Notify, so we make an atomic write the frame = buffer.=0D + // We would not want a timer based event (Cursor, ...) to come in while = we are=0D + // doing this operation.=0D + //=0D + OriginalTPL =3D gBS->RaiseTPL (TPL_NOTIFY);=0D +=0D + switch (BltOperation) {=0D + case EfiBltVideoToBltBuffer:=0D + case EfiBltBufferToVideo:=0D + case EfiBltVideoFill:=0D + case EfiBltVideoToVideo:=0D + Status =3D FrameBufferBlt (=0D + fbconf,=0D + BltBuffer,=0D + BltOperation,=0D + SourceX,=0D + SourceY,=0D + DestinationX,=0D + DestinationY,=0D + Width,=0D + Height,=0D + Delta=0D + );=0D + break;=0D +=0D + default:=0D + Status =3D EFI_INVALID_PARAMETER;=0D + ASSERT (FALSE);=0D + }=0D +=0D + gBS->RestoreTPL (OriginalTPL);=0D +=0D + return Status;=0D +}=0D +=0D +=0D +//=0D +// Construction and Destruction functions=0D +//=0D +=0D +EFI_STATUS=0D +EmuGopConstructor (=0D + GOP_PRIVATE_DATA *Private=0D + )=0D +{=0D + // Set mode 0 to be the requested resolution=0D + mGopModeData[0].HorizontalResolution =3D PcdGet32 ( PcdVideoHorizontalRe= solution);=0D + mGopModeData[0].VerticalResolution =3D PcdGet32 ( PcdVideoVerticalResolu= tion );=0D +=0D + Private->ModeData =3D mGopModeData;=0D +=0D + Private->GraphicsOutput.QueryMode =3D EmuGopQuerytMode;=0D + Private->GraphicsOutput.SetMode =3D EmuGopSetMode;=0D + Private->GraphicsOutput.Blt =3D EmuGopBlt;=0D +=0D + //=0D + // Allocate buffer for Graphics Output Protocol mode information=0D + //=0D + Private->GraphicsOutput.Mode =3D AllocatePool (sizeof (EFI_GRAPHICS_OUTP= UT_PROTOCOL_MODE));=0D + if (Private->GraphicsOutput.Mode =3D=3D NULL) {=0D + return EFI_OUT_OF_RESOURCES;=0D + }=0D + Private->GraphicsOutput.Mode->Info =3D AllocatePool (sizeof (EFI_GRAPHIC= S_OUTPUT_MODE_INFORMATION));=0D + if (Private->GraphicsOutput.Mode->Info =3D=3D NULL) {=0D + return EFI_OUT_OF_RESOURCES;=0D + }=0D +=0D +=0D + DEBUG ((DEBUG_INFO, "BHYVE Gop Constructor\n"));=0D +=0D + Private->GraphicsOutput.Mode->MaxMode =3D sizeof(mGopModeData) / sizeof(= GOP_MODE_DATA);=0D + //=0D + // Till now, we have no idea about the window size.=0D + //=0D + Private->GraphicsOutput.Mode->Mode =3D GRAPHICS_OUTPUT_INVALID_MODE_NUMB= ER;=0D + Private->GraphicsOutput.Mode->Info->Version =3D 0;=0D + Private->GraphicsOutput.Mode->Info->HorizontalResolution =3D 0;=0D + Private->GraphicsOutput.Mode->Info->VerticalResolution =3D 0;=0D + Private->GraphicsOutput.Mode->Info->PixelFormat =3D PixelBitMask;=0D + Private->GraphicsOutput.Mode->SizeOfInfo =3D sizeof (EFI_GRAPHICS_OUTPUT= _MODE_INFORMATION);=0D + Private->GraphicsOutput.Mode->FrameBufferBase =3D (EFI_PHYSICAL_ADDRESS)= Private->FbAddr;=0D + Private->GraphicsOutput.Mode->FrameBufferSize =3D Private->FbSize;=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D +=0D +=0D +EFI_STATUS=0D +EmuGopDestructor (=0D + GOP_PRIVATE_DATA *Private=0D + )=0D +{=0D + //=0D + // Free graphics output protocol occupied resource=0D + //=0D + if (Private->GraphicsOutput.Mode !=3D NULL) {=0D + if (Private->GraphicsOutput.Mode->Info !=3D NULL) {=0D + FreePool (Private->GraphicsOutput.Mode->Info);=0D + }=0D + FreePool (Private->GraphicsOutput.Mode);=0D + Private->GraphicsOutput.Mode =3D NULL;=0D + }=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D +=0D +VOID=0D +EFIAPI=0D +ShutdownGopEvent (=0D + IN EFI_EVENT Event,=0D + IN VOID *Context=0D + )=0D +/*++=0D +=0D +Routine Description:=0D +=0D + This is the UGA screen's callback notification function for exit-boot-se= rvices.=0D + All we do here is call EmuGopDestructor().=0D +=0D +Arguments:=0D +=0D + Event - not used=0D + Context - pointer to the Private structure.=0D +=0D +Returns:=0D +=0D + None.=0D +=0D +**/=0D +{=0D + EmuGopDestructor (Context);=0D +}=0D +=0D diff --git a/OvmfPkg/Bhyve/BhyveRfbDxe/VbeShim.asm b/OvmfPkg/Bhyve/BhyveRfb= Dxe/VbeShim.asm new file mode 100644 index 0000000000..f7a1ec297f --- /dev/null +++ b/OvmfPkg/Bhyve/BhyveRfbDxe/VbeShim.asm @@ -0,0 +1,342 @@ +;-------------------------------------------------------------------------= -----=0D +; @file=0D +; A minimal Int10h stub that allows the Windows 2008 R2 SP1 UEFI guest's b= uggy,=0D +; default VGA driver to switch to 1024x768x32.=0D +;=0D +; Copyright (C) 2020, Rebecca Cran <rebecca@...>=0D +; Copyright (C) 2015, Nahanni Systems, Inc.=0D +; Copyright (C) 2014, Red Hat, Inc.=0D +; Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved.<BR>=0D +;=0D +; SPDX-License-Identifier: BSD-2-Clause-Patent=0D +;=0D +;-------------------------------------------------------------------------= -----=0D +=0D +; enable this macro for debug messages=0D +%define DEBUG=0D +=0D +%macro DebugLog 1=0D +%ifdef DEBUG=0D + push si=0D + mov si, %1=0D + call PrintStringSi=0D + pop si=0D +%endif=0D +%endmacro=0D +=0D +=0D +BITS 16=0D +ORG 0=0D +=0D +VbeInfo:=0D +TIMES 256 nop=0D +=0D +VbeModeInfo:=0D +VbeMode1:=0D +TIMES 50 nop=0D +VbeMode2:=0D +TIMES 50 nop=0D +VbeMode3:=0D +TIMES 50 nop=0D +VbeMode4:=0D +TIMES 50 nop=0D +TIMES 56 nop ; filler for 256 bytes=0D +=0D +Handler:=0D + cmp ax, 0x4f00=0D + je GetInfo=0D + cmp ax, 0x4f01=0D + je GetModeInfo=0D + cmp ax, 0x4f02=0D + je SetMode=0D + cmp ax, 0x4f03=0D + je GetMode=0D + cmp ax, 0x4f10=0D + je GetPmCapabilities=0D + cmp ax, 0x4f15=0D + je ReadEdid=0D + cmp ah, 0x00=0D + je SetModeLegacy=0D + DebugLog StrUnkownFunction=0D +Hang:=0D + jmp Hang=0D +=0D +=0D +GetInfo:=0D + push es=0D + push di=0D + push ds=0D + push si=0D + push cx=0D +=0D + DebugLog StrEnterGetInfo=0D +=0D + ; target (es:di) set on input=0D + push cs=0D + pop ds=0D + mov si, VbeInfo=0D + ; source (ds:si) set now=0D +=0D + mov cx, 256=0D + cld=0D + rep movsb=0D +=0D + pop cx=0D + pop si=0D + pop ds=0D + pop di=0D + pop es=0D + jmp Success=0D +=0D +=0D +GetModeInfo:=0D + push es=0D + push di=0D + push ds=0D + push si=0D + push cx=0D +=0D + DebugLog StrEnterGetModeInfo=0D +=0D + and cx, ~0x4000 ; clear potentially set LFB bit in mode number=0D +=0D + cmp cx, 0x013f=0D + je gKnownMode1=0D + cmp cx, 0x0140=0D + je gKnownMode2=0D + cmp cx, 0x0141=0D + je gKnownMode3=0D +=0D + DebugLog StrUnkownMode=0D + jmp Hang=0D +gKnownMode1:=0D + DebugLog StrMode1=0D + mov si, VbeMode1=0D + jmp CopyModeInfo=0D +gKnownMode2:=0D + DebugLog StrMode2=0D + mov si, VbeMode2=0D + jmp CopyModeInfo=0D +gKnownMode3:=0D + DebugLog StrMode3=0D + mov si, VbeMode3=0D + jmp CopyModeInfo=0D +gKnownMode4:=0D + DebugLog StrMode4=0D + mov si, VbeMode4=0D + jmp CopyModeInfo=0D +=0D +CopyModeInfo:=0D + ; target (es:di) set on input=0D + push cs=0D + pop ds=0D + ;mov si, VbeModeInfo=0D + ; source (ds:si) set now=0D +=0D + ;mov cx, 256=0D + mov cx, 50=0D + cld=0D + rep movsb=0D +=0D + pop cx=0D + pop si=0D + pop ds=0D + pop di=0D + pop es=0D + jmp Success=0D +=0D +=0D +SetMode:=0D + push dx=0D + push ax=0D +=0D + DebugLog StrEnterSetMode=0D +=0D + and bx, ~0x4000 ; clear potentially set LFB bit in mode number=0D + cmp bx, 0x013f=0D + je KnownMode1=0D + cmp bx, 0x0140=0D + je KnownMode2=0D + cmp bx, 0x0141=0D + je KnownMode3=0D + DebugLog StrUnkownMode=0D + jmp Hang=0D +KnownMode1:=0D + DebugLog StrMode1=0D + jmp SetModeDone=0D +KnownMode2:=0D + DebugLog StrMode2=0D + jmp SetModeDone=0D +KnownMode3:=0D + DebugLog StrMode3=0D + jmp SetModeDone=0D +KnownMode4:=0D + DebugLog StrMode4=0D +=0D +SetModeDone:=0D + mov [CurMode], bl=0D + mov [CurMode+1], bh=0D + pop ax=0D + pop dx=0D + jmp Success=0D +=0D +=0D +GetMode:=0D + DebugLog StrEnterGetMode=0D + mov bl, [CurMode]=0D + mov bh, [CurMode+1]=0D + jmp Success=0D +=0D +=0D +GetPmCapabilities:=0D + DebugLog StrGetPmCapabilities=0D + mov bx, 0x0080=0D + jmp Success=0D +=0D +=0D +ReadEdid:=0D + push es=0D + push di=0D + push ds=0D + push si=0D + push cx=0D +=0D + DebugLog StrReadEdid=0D +=0D + ; target (es:di) set on input=0D + push cs=0D + pop ds=0D + mov si, Edid=0D + ; source (ds:si) set now=0D +=0D + mov cx, 128=0D + cld=0D + rep movsb=0D +=0D + pop cx=0D + pop si=0D + pop ds=0D + pop di=0D + pop es=0D + jmp Success=0D +=0D +=0D +SetModeLegacy:=0D + DebugLog StrEnterSetModeLegacy=0D +=0D + cmp al, 0x03=0D + je sKnownMode3=0D + cmp al, 0x12=0D + je sKnownMode4=0D + DebugLog StrUnkownMode=0D + jmp Hang=0D +sKnownMode3:=0D + DebugLog StrLegacyMode3=0D + mov al, 0 ; 0x30=0D + jmp SetModeLegacyDone=0D +sKnownMode4:=0D + mov al, 0 ;0x20=0D +SetModeLegacyDone:=0D + DebugLog StrExitSuccess=0D + iret=0D +=0D +=0D +Success:=0D + DebugLog StrExitSuccess=0D + mov ax, 0x004f=0D + iret=0D +=0D +=0D +Unsupported:=0D + DebugLog StrExitUnsupported=0D + mov ax, 0x024f=0D + iret=0D +=0D +=0D +%ifdef DEBUG=0D +PrintStringSi:=0D + pusha=0D + push ds ; save original=0D + push cs=0D + pop ds=0D + mov dx, 0x220 ; bhyve debug cons port=0D + mov ax, 0=0D +PrintStringSiLoop:=0D + lodsb=0D + cmp al, 0=0D + je PrintStringSiDone=0D + out dx, al=0D + jmp PrintStringSiLoop=0D +PrintStringSiDone:=0D + pop ds ; restore original=0D + popa=0D + ret=0D +=0D +=0D +StrExitSuccess:=0D + db 'vOk', 0x0d, 0x0a, 0=0D +=0D +StrExitUnsupported:=0D + db 'vUnsupported', 0x0d, 0x0a, 0=0D +=0D +StrUnkownFunction:=0D + db 'vUnknown Function', 0x0d, 0x0a, 0=0D +=0D +StrEnterGetInfo:=0D + db 'vGetInfo', 0x0d, 0x0a, 0=0D +=0D +StrEnterGetModeInfo:=0D + db 'vGetModeInfo', 0x0d, 0x0a, 0=0D +=0D +StrEnterGetMode:=0D + db 'vGetMode', 0x0d, 0x0a, 0=0D +=0D +StrEnterSetMode:=0D + db 'vSetMode', 0x0d, 0x0a, 0=0D +=0D +StrEnterSetModeLegacy:=0D + db 'vSetModeLegacy', 0x0d, 0x0a, 0=0D +=0D +StrUnkownMode:=0D + db 'vUnkown Mode', 0x0d, 0x0a, 0=0D +=0D +StrGetPmCapabilities:=0D + db 'vGetPmCapabilities', 0x0d, 0x0a, 0=0D +=0D +StrReadEdid:=0D + db 'vReadEdid', 0x0d, 0x0a, 0=0D +=0D +StrLegacyMode3:=0D + db 'vLegacyMode3', 0x0d, 0x0a, 0=0D +=0D +=0D +StrMode1:=0D + db 'mode_640x480x32', 0x0d, 0x0a, 0=0D +StrMode2:=0D + db 'mode_800x600x32', 0x0d, 0x0a, 0=0D +StrMode3:=0D + db 'mode_1024x768x32', 0x0d, 0x0a, 0=0D +StrMode4:=0D + db 'mode_unused', 0x0d, 0x0a, 0=0D +%endif=0D +=0D +CurMode:=0D + db 0x00, 0x00=0D +=0D +;=0D +; EDID stores monitor information. For now, just send back an null item.=0D +;=0D +Edid:=0D + db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00=0D + db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00=0D + db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00=0D + db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00=0D + db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00=0D + db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00=0D + db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00=0D + db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00=0D + db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00=0D + db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00=0D + db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00=0D + db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00=0D + db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00=0D diff --git a/OvmfPkg/Bhyve/BhyveRfbDxe/VbeShim.c b/OvmfPkg/Bhyve/BhyveRfbDx= e/VbeShim.c new file mode 100644 index 0000000000..740b966794 --- /dev/null +++ b/OvmfPkg/Bhyve/BhyveRfbDxe/VbeShim.c @@ -0,0 +1,259 @@ +/** @file=0D + Install a fake VGABIOS service handler (real mode Int10h) for the buggy= =0D + Windows 2008 R2 SP1 UEFI guest.=0D +=0D + The handler is never meant to be directly executed by a VCPU; it's there= for=0D + the internal real mode emulator of Windows 2008 R2 SP1.=0D +=0D + The code is based on Ralf Brown's Interrupt List:=0D + <http://www.cs.cmu.edu/~ralf/files.html>=0D + <http://www.ctyme.com/rbrown.htm>=0D +=0D + Copyright (C) 2020, Rebecca Cran <rebecca@...>=0D + Copyright (C) 2015, Nahanni Systems, Inc.=0D + Copyright (C) 2014, Red Hat, Inc.=0D + Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved.<BR>=0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include <IndustryStandard/LegacyVgaBios.h>=0D +#include <Library/DebugLib.h>=0D +#include <Library/PciLib.h>=0D +#include <Library/PrintLib.h>=0D +=0D +#include "Gop.h"=0D +#include "VbeShim.h"=0D +=0D +#pragma pack (1)=0D +typedef struct {=0D + UINT16 Offset;=0D + UINT16 Segment;=0D +} IVT_ENTRY;=0D +#pragma pack ()=0D +=0D +//=0D +// This string is displayed by Windows 2008 R2 SP1 in the Screen Resolutio= n,=0D +// Advanced Settings dialog. It should be short.=0D +//=0D +STATIC CONST CHAR8 mProductRevision[] =3D "2.0";=0D +=0D +#define NUM_VBE_MODES 3=0D +STATIC CONST UINT16 vbeModeIds[] =3D {=0D + 0x13f, // 640x480x32=0D + 0x140, // 800x600x32=0D + 0x141 // 1024x768x32=0D +};=0D +=0D +// Modes can be toggled with bit-0=0D +#define VBE_MODE_ENABLED 0x00BB=0D +#define VBE_MODE_DISABLED 0x00BA=0D +=0D +STATIC VBE2_MODE_INFO vbeModes[] =3D {=0D + { // 0x13f 640x480x32=0D +=0D + // ModeAttr - BytesPerScanLine=0D + VBE_MODE_DISABLED, 0x07, 0x00, 0x40, 0x40, 0xA000, 0x00, 0x0000, 640*4= ,=0D + // Width, Height..., Vbe3=0D + 640, 480, 16, 8, 1, 32, 1, 0x06, 0, 0, 1,=0D + // Masks=0D + 0x08, 0x10, 0x08, 0x08, 0x08, 0x00, 0x08, 0x18, 0x00,=0D + // Framebuffer=0D + 0xdeadbeef, 0x0000, 0x0000=0D + },=0D + { // 0x140 800x600x32=0D +=0D + // ModeAttr - BytesPerScanLine=0D + VBE_MODE_DISABLED, 0x07, 0x00, 0x40, 0x40, 0xA000, 0x00, 0x0000, 800*4= ,=0D + // Width, Height..., Vbe3=0D + 800, 600, 16, 8, 1, 32, 1, 0x06, 0, 0, 1,=0D + // Masks=0D + 0x08, 0x10, 0x08, 0x08, 0x08, 0x00, 0x08, 0x18, 0x00,=0D + // Framebuffer=0D + 0xdeadbeef, 0x0000, 0x0000=0D + },=0D + { // 0x141 1024x768x32=0D +=0D + // ModeAttr - BytesPerScanLine=0D + VBE_MODE_ENABLED, 0x07, 0x00, 0x40, 0x40, 0xA000, 0x00, 0x0000, 1024*4= ,=0D + // Width, Height..., Vbe3=0D + 1024, 768, 16, 8, 1, 32, 1, 0x06, 0, 0, 1,=0D + // Masks=0D + 0x08, 0x10, 0x08, 0x08, 0x08, 0x00, 0x08, 0x18, 0x00,=0D + // Framebuffer=0D + 0xdeadbeef, 0x0000, 0x0000=0D + }=0D +};=0D +=0D +/**=0D + Install the VBE Info and VBE Mode Info structures, and the VBE service=0D + handler routine in the C segment. Point the real-mode Int10h interrupt v= ector=0D + to the handler. The only advertised mode is 1024x768x32.=0D +=0D + @param[in] CardName Name of the video card to be exposed in the= =0D + Product Name field of the VBE Info structure= .=0D + @param[in] FrameBufferBase Guest-physical base address of the video car= d's=0D + frame buffer.=0D +**/=0D +VOID=0D +InstallVbeShim (=0D + IN CONST CHAR16 *CardName,=0D + IN EFI_PHYSICAL_ADDRESS FrameBufferBase=0D + )=0D +{=0D + EFI_PHYSICAL_ADDRESS Segment0, SegmentC, SegmentF;=0D + UINTN Segment0Pages;=0D + IVT_ENTRY *Int0x10;=0D + EFI_STATUS Status;=0D + UINTN Pam1Address;=0D + UINT8 Pam1;=0D + UINTN SegmentCPages;=0D + VBE_INFO *VbeInfoFull;=0D + VBE_INFO_BASE *VbeInfo;=0D + UINT8 *Ptr;=0D + UINTN Printed;=0D + VBE_MODE_INFO *VbeModeInfo;=0D + UINTN i;=0D +=0D + Segment0 =3D 0x00000;=0D + SegmentC =3D 0xC0000;=0D + SegmentF =3D 0xF0000;=0D +=0D + //=0D + // Attempt to cover the real mode IVT with an allocation. This is a UEFI= =0D + // driver, hence the arch protocols have been installed previously. Amon= g=0D + // those, the CPU arch protocol has configured the IDT, so we can overwr= ite=0D + // the IVT used in real mode.=0D + //=0D + // The allocation request may fail, eg. if LegacyBiosDxe has already run= .=0D + //=0D + Segment0Pages =3D 1;=0D + Int0x10 =3D (IVT_ENTRY *)(UINTN)Segment0 + 0x10;=0D + Status =3D gBS->AllocatePages (AllocateAddress, EfiBootServicesCode,=0D + Segment0Pages, &Segment0);=0D +=0D + if (EFI_ERROR (Status)) {=0D + EFI_PHYSICAL_ADDRESS Handler;=0D +=0D + //=0D + // Check if a video BIOS handler has been installed previously -- we=0D + // shouldn't override a real video BIOS with our shim, nor our own shi= m if=0D + // it's already present.=0D + //=0D + Handler =3D (Int0x10->Segment << 4) + Int0x10->Offset;=0D + if (Handler >=3D SegmentC && Handler < SegmentF) {=0D + DEBUG ((DEBUG_VERBOSE, "%a: Video BIOS handler found at %04x:%04x\n"= ,=0D + __FUNCTION__, Int0x10->Segment, Int0x10->Offset));=0D + return;=0D + }=0D +=0D + //=0D + // Otherwise we'll overwrite the Int10h vector, even though we may not= own=0D + // the page at zero.=0D + //=0D + DEBUG ((DEBUG_VERBOSE, "%a: failed to allocate page at zero: %r\n",=0D + __FUNCTION__, Status));=0D + } else {=0D + //=0D + // We managed to allocate the page at zero. SVN r14218 guarantees that= it=0D + // is NUL-filled.=0D + //=0D + ASSERT (Int0x10->Segment =3D=3D 0x0000);=0D + ASSERT (Int0x10->Offset =3D=3D 0x0000);=0D + }=0D +=0D + //=0D + // Put the shim in place first.=0D + //=0D + Pam1Address =3D PCI_LIB_ADDRESS (0, 0, 0, 0x5A);=0D + //=0D + // low nibble covers 0xC0000 to 0xC3FFF=0D + // high nibble covers 0xC4000 to 0xC7FFF=0D + // bit1 in each nibble is Write Enable=0D + // bit0 in each nibble is Read Enable=0D + //=0D + Pam1 =3D PciRead8 (Pam1Address);=0D + PciWrite8 (Pam1Address, Pam1 | (BIT1 | BIT0));=0D +=0D + //=0D + // We never added memory space durig PEI or DXE for the C segment, so we= =0D + // don't need to (and can't) allocate from there. Also, guest operating= =0D + // systems will see a hole in the UEFI memory map there.=0D + //=0D + SegmentCPages =3D 4;=0D +=0D + ASSERT (sizeof mVbeShim <=3D EFI_PAGES_TO_SIZE (SegmentCPages));=0D + CopyMem ((VOID *)(UINTN)SegmentC, mVbeShim, sizeof mVbeShim);=0D +=0D + //=0D + // Fill in the VBE INFO structure.=0D + //=0D + VbeInfoFull =3D (VBE_INFO *)(UINTN)SegmentC;=0D + VbeInfo =3D &VbeInfoFull->Base;=0D + Ptr =3D VbeInfoFull->Buffer;=0D +=0D + CopyMem (VbeInfo->Signature, "VESA", 4);=0D + VbeInfo->VesaVersion =3D 0x0200;=0D +=0D + VbeInfo->OemNameAddress =3D (UINT32)SegmentC << 12 | (UINT16)((UINTN)Ptr= -SegmentC);=0D + CopyMem (Ptr, "FBSD", 5);=0D + Ptr +=3D 5;=0D +=0D + VbeInfo->Capabilities =3D BIT1 | BIT0; // DAC can be switched into 8-bit= mode=0D +=0D + VbeInfo->ModeListAddress =3D (UINT32)SegmentC << 12 | (UINT16)((UINTN)Pt= r-SegmentC);=0D + for (i =3D 0; i < NUM_VBE_MODES; i ++) {=0D + *(UINT16*)Ptr =3D vbeModeIds[i]; // mode number=0D + Ptr +=3D 2;=0D + }=0D + *(UINT16*)Ptr =3D 0xFFFF; // mode list terminator=0D + Ptr +=3D 2;=0D +=0D + VbeInfo->VideoMem64K =3D (UINT16)((1024 * 768 * 4 + 65535) / 65536);=0D + VbeInfo->OemSoftwareVersion =3D 0x0200;=0D +=0D + VbeInfo->VendorNameAddress =3D (UINT32)SegmentC << 12 | (UINT16)((UINTN)= Ptr-SegmentC);=0D + CopyMem (Ptr, "FBSD", 5);=0D + Ptr +=3D 5;=0D +=0D + VbeInfo->ProductNameAddress =3D (UINT32)SegmentC << 12 | (UINT16)((UINTN= )Ptr-SegmentC);=0D + Printed =3D AsciiSPrint ((CHAR8 *)Ptr,=0D + sizeof VbeInfoFull->Buffer - (Ptr - VbeInfoFull->Buffer), "%= s",=0D + CardName);=0D + Ptr +=3D Printed + 1;=0D +=0D + VbeInfo->ProductRevAddress =3D (UINT32)SegmentC << 12 | (UINT16)((UINTN)= Ptr-SegmentC);=0D + CopyMem (Ptr, mProductRevision, sizeof mProductRevision);=0D + Ptr +=3D sizeof mProductRevision;=0D +=0D + ASSERT (sizeof VbeInfoFull->Buffer >=3D Ptr - VbeInfoFull->Buffer);=0D + ZeroMem (Ptr, sizeof VbeInfoFull->Buffer - (Ptr - VbeInfoFull->Buffer));= =0D +=0D + //=0D + // Fill in the VBE MODE INFO structure list=0D + //=0D + VbeModeInfo =3D (VBE_MODE_INFO *)(VbeInfoFull + 1);=0D + Ptr =3D (UINT8 *)VbeModeInfo;=0D + for (i =3D 0; i < NUM_VBE_MODES; i++) {=0D + vbeModes[i].LfbAddress =3D (UINT32)FrameBufferBase;=0D + CopyMem (Ptr, &vbeModes[i], 0x32);=0D + Ptr +=3D 0x32;=0D + }=0D +=0D + ZeroMem (Ptr, 56); // Clear remaining bytes=0D +=0D + //=0D + // Clear Write Enable (bit1), keep Read Enable (bit0) set=0D + //=0D + PciWrite8 (Pam1Address, (Pam1 & ~BIT1) | BIT0);=0D +=0D + //=0D + // Second, point the Int10h vector at the shim.=0D + //=0D + Int0x10->Segment =3D (UINT16) ((UINT32)SegmentC >> 4);=0D + Int0x10->Offset =3D (UINT16) ((UINTN) (VbeModeInfo + 1) - SegmentC);=0D +=0D + DEBUG ((DEBUG_INFO, "%a: VBE shim installed to %x:%x\n",=0D + __FUNCTION__, Int0x10->Segment, Int0x10->Offset));=0D +}=0D diff --git a/OvmfPkg/Bhyve/BhyveRfbDxe/VbeShim.h b/OvmfPkg/Bhyve/BhyveRfbDx= e/VbeShim.h new file mode 100644 index 0000000000..72b8a3f25f --- /dev/null +++ b/OvmfPkg/Bhyve/BhyveRfbDxe/VbeShim.h @@ -0,0 +1,912 @@ +//=0D +// THIS FILE WAS GENERATED BY "VbeShim.sh". DO NOT EDIT.=0D +//=0D +#ifndef _VBE_SHIM_H_=0D +#define _VBE_SHIM_H_=0D +STATIC CONST UINT8 mVbeShim[] =3D {=0D + /* 00000000 nop */ 0x90,=0D + /* 00000001 nop */ 0x90,=0D + /* 00000002 nop */ 0x90,=0D + /* 00000003 nop */ 0x90,=0D + /* 00000004 nop */ 0x90,=0D + /* 00000005 nop */ 0x90,=0D + /* 00000006 nop */ 0x90,=0D + /* 00000007 nop */ 0x90,=0D + /* 00000008 nop */ 0x90,=0D + /* 00000009 nop */ 0x90,=0D + /* 0000000A nop */ 0x90,=0D + /* 0000000B nop */ 0x90,=0D + /* 0000000C nop */ 0x90,=0D + /* 0000000D nop */ 0x90,=0D + /* 0000000E nop */ 0x90,=0D + /* 0000000F nop */ 0x90,=0D + /* 00000010 nop */ 0x90,=0D + /* 00000011 nop */ 0x90,=0D + /* 00000012 nop */ 0x90,=0D + /* 00000013 nop */ 0x90,=0D + /* 00000014 nop */ 0x90,=0D + /* 00000015 nop */ 0x90,=0D + /* 00000016 nop */ 0x90,=0D + /* 00000017 nop */ 0x90,=0D + /* 00000018 nop */ 0x90,=0D + /* 00000019 nop */ 0x90,=0D + /* 0000001A nop */ 0x90,=0D + /* 0000001B nop */ 0x90,=0D + /* 0000001C nop */ 0x90,=0D + /* 0000001D nop */ 0x90,=0D + /* 0000001E nop */ 0x90,=0D + /* 0000001F nop */ 0x90,=0D + /* 00000020 nop */ 0x90,=0D + /* 00000021 nop */ 0x90,=0D + /* 00000022 nop */ 0x90,=0D + /* 00000023 nop */ 0x90,=0D + /* 00000024 nop */ 0x90,=0D + /* 00000025 nop */ 0x90,=0D + /* 00000026 nop */ 0x90,=0D + /* 00000027 nop */ 0x90,=0D + /* 00000028 nop */ 0x90,=0D + /* 00000029 nop */ 0x90,=0D + /* 0000002A nop */ 0x90,=0D + /* 0000002B nop */ 0x90,=0D + /* 0000002C nop */ 0x90,=0D + /* 0000002D nop */ 0x90,=0D + /* 0000002E nop */ 0x90,=0D + /* 0000002F nop */ 0x90,=0D + /* 00000030 nop */ 0x90,=0D + /* 00000031 nop */ 0x90,=0D + /* 00000032 nop */ 0x90,=0D + /* 00000033 nop */ 0x90,=0D + /* 00000034 nop */ 0x90,=0D + /* 00000035 nop */ 0x90,=0D + /* 00000036 nop */ 0x90,=0D + /* 00000037 nop */ 0x90,=0D + /* 00000038 nop */ 0x90,=0D + /* 00000039 nop */ 0x90,=0D + /* 0000003A nop */ 0x90,=0D + /* 0000003B nop */ 0x90,=0D + /* 0000003C nop */ 0x90,=0D + /* 0000003D nop */ 0x90,=0D + /* 0000003E nop */ 0x90,=0D + /* 0000003F nop */ 0x90,=0D + /* 00000040 nop */ 0x90,=0D + /* 00000041 nop */ 0x90,=0D + /* 00000042 nop */ 0x90,=0D + /* 00000043 nop */ 0x90,=0D + /* 00000044 nop */ 0x90,=0D + /* 00000045 nop */ 0x90,=0D + /* 00000046 nop */ 0x90,=0D + /* 00000047 nop */ 0x90,=0D + /* 00000048 nop */ 0x90,=0D + /* 00000049 nop */ 0x90,=0D + /* 0000004A nop */ 0x90,=0D + /* 0000004B nop */ 0x90,=0D + /* 0000004C nop */ 0x90,=0D + /* 0000004D nop */ 0x90,=0D + /* 0000004E nop */ 0x90,=0D + /* 0000004F nop */ 0x90,=0D + /* 00000050 nop */ 0x90,=0D + /* 00000051 nop */ 0x90,=0D + /* 00000052 nop */ 0x90,=0D + /* 00000053 nop */ 0x90,=0D + /* 00000054 nop */ 0x90,=0D + /* 00000055 nop */ 0x90,=0D + /* 00000056 nop */ 0x90,=0D + /* 00000057 nop */ 0x90,=0D + /* 00000058 nop */ 0x90,=0D + /* 00000059 nop */ 0x90,=0D + /* 0000005A nop */ 0x90,=0D + /* 0000005B nop */ 0x90,=0D + /* 0000005C nop */ 0x90,=0D + /* 0000005D nop */ 0x90,=0D + /* 0000005E nop */ 0x90,=0D + /* 0000005F nop */ 0x90,=0D + /* 00000060 nop */ 0x90,=0D + /* 00000061 nop */ 0x90,=0D + /* 00000062 nop */ 0x90,=0D + /* 00000063 nop */ 0x90,=0D + /* 00000064 nop */ 0x90,=0D + /* 00000065 nop */ 0x90,=0D + /* 00000066 nop */ 0x90,=0D + /* 00000067 nop */ 0x90,=0D + /* 00000068 nop */ 0x90,=0D + /* 00000069 nop */ 0x90,=0D + /* 0000006A nop */ 0x90,=0D + /* 0000006B nop */ 0x90,=0D + /* 0000006C nop */ 0x90,=0D + /* 0000006D nop */ 0x90,=0D + /* 0000006E nop */ 0x90,=0D + /* 0000006F nop */ 0x90,=0D + /* 00000070 nop */ 0x90,=0D + /* 00000071 nop */ 0x90,=0D + /* 00000072 nop */ 0x90,=0D + /* 00000073 nop */ 0x90,=0D + /* 00000074 nop */ 0x90,=0D + /* 00000075 nop */ 0x90,=0D + /* 00000076 nop */ 0x90,=0D + /* 00000077 nop */ 0x90,=0D + /* 00000078 nop */ 0x90,=0D + /* 00000079 nop */ 0x90,=0D + /* 0000007A nop */ 0x90,=0D + /* 0000007B nop */ 0x90,=0D + /* 0000007C nop */ 0x90,=0D + /* 0000007D nop */ 0x90,=0D + /* 0000007E nop */ 0x90,=0D + /* 0000007F nop */ 0x90,=0D + /* 00000080 nop */ 0x90,=0D + /* 00000081 nop */ 0x90,=0D + /* 00000082 nop */ 0x90,=0D + /* 00000083 nop */ 0x90,=0D + /* 00000084 nop */ 0x90,=0D + /* 00000085 nop */ 0x90,=0D + /* 00000086 nop */ 0x90,=0D + /* 00000087 nop */ 0x90,=0D + /* 00000088 nop */ 0x90,=0D + /* 00000089 nop */ 0x90,=0D + /* 0000008A nop */ 0x90,=0D + /* 0000008B nop */ 0x90,=0D + /* 0000008C nop */ 0x90,=0D + /* 0000008D nop */ 0x90,=0D + /* 0000008E nop */ 0x90,=0D + /* 0000008F nop */ 0x90,=0D + /* 00000090 nop */ 0x90,=0D + /* 00000091 nop */ 0x90,=0D + /* 00000092 nop */ 0x90,=0D + /* 00000093 nop */ 0x90,=0D + /* 00000094 nop */ 0x90,=0D + /* 00000095 nop */ 0x90,=0D + /* 00000096 nop */ 0x90,=0D + /* 00000097 nop */ 0x90,=0D + /* 00000098 nop */ 0x90,=0D + /* 00000099 nop */ 0x90,=0D + /* 0000009A nop */ 0x90,=0D + /* 0000009B nop */ 0x90,=0D + /* 0000009C nop */ 0x90,=0D + /* 0000009D nop */ 0x90,=0D + /* 0000009E nop */ 0x90,=0D + /* 0000009F nop */ 0x90,=0D + /* 000000A0 nop */ 0x90,=0D + /* 000000A1 nop */ 0x90,=0D + /* 000000A2 nop */ 0x90,=0D + /* 000000A3 nop */ 0x90,=0D + /* 000000A4 nop */ 0x90,=0D + /* 000000A5 nop */ 0x90,=0D + /* 000000A6 nop */ 0x90,=0D + /* 000000A7 nop */ 0x90,=0D + /* 000000A8 nop */ 0x90,=0D + /* 000000A9 nop */ 0x90,=0D + /* 000000AA nop */ 0x90,=0D + /* 000000AB nop */ 0x90,=0D + /* 000000AC nop */ 0x90,=0D + /* 000000AD nop */ 0x90,=0D + /* 000000AE nop */ 0x90,=0D + /* 000000AF nop */ 0x90,=0D + /* 000000B0 nop */ 0x90,=0D + /* 000000B1 nop */ 0x90,=0D + /* 000000B2 nop */ 0x90,=0D + /* 000000B3 nop */ 0x90,=0D + /* 000000B4 nop */ 0x90,=0D + /* 000000B5 nop */ 0x90,=0D + /* 000000B6 nop */ 0x90,=0D + /* 000000B7 nop */ 0x90,=0D + /* 000000B8 nop */ 0x90,=0D + /* 000000B9 nop */ 0x90,=0D + /* 000000BA nop */ 0x90,=0D + /* 000000BB nop */ 0x90,=0D + /* 000000BC nop */ 0x90,=0D + /* 000000BD nop */ 0x90,=0D + /* 000000BE nop */ 0x90,=0D + /* 000000BF nop */ 0x90,=0D + /* 000000C0 nop */ 0x90,=0D + /* 000000C1 nop */ 0x90,=0D + /* 000000C2 nop */ 0x90,=0D + /* 000000C3 nop */ 0x90,=0D + /* 000000C4 nop */ 0x90,=0D + /* 000000C5 nop */ 0x90,=0D + /* 000000C6 nop */ 0x90,=0D + /* 000000C7 nop */ 0x90,=0D + /* 000000C8 nop */ 0x90,=0D + /* 000000C9 nop */ 0x90,=0D + /* 000000CA nop */ 0x90,=0D + /* 000000CB nop */ 0x90,=0D + /* 000000CC nop */ 0x90,=0D + /* 000000CD nop */ 0x90,=0D + /* 000000CE nop */ 0x90,=0D + /* 000000CF nop */ 0x90,=0D + /* 000000D0 nop */ 0x90,=0D + /* 000000D1 nop */ 0x90,=0D + /* 000000D2 nop */ 0x90,=0D + /* 000000D3 nop */ 0x90,=0D + /* 000000D4 nop */ 0x90,=0D + /* 000000D5 nop */ 0x90,=0D + /* 000000D6 nop */ 0x90,=0D + /* 000000D7 nop */ 0x90,=0D + /* 000000D8 nop */ 0x90,=0D + /* 000000D9 nop */ 0x90,=0D + /* 000000DA nop */ 0x90,=0D + /* 000000DB nop */ 0x90,=0D + /* 000000DC nop */ 0x90,=0D + /* 000000DD nop */ 0x90,=0D + /* 000000DE nop */ 0x90,=0D + /* 000000DF nop */ 0x90,=0D + /* 000000E0 nop */ 0x90,=0D + /* 000000E1 nop */ 0x90,=0D + /* 000000E2 nop */ 0x90,=0D + /* 000000E3 nop */ 0x90,=0D + /* 000000E4 nop */ 0x90,=0D + /* 000000E5 nop */ 0x90,=0D + /* 000000E6 nop */ 0x90,=0D + /* 000000E7 nop */ 0x90,=0D + /* 000000E8 nop */ 0x90,=0D + /* 000000E9 nop */ 0x90,=0D + /* 000000EA nop */ 0x90,=0D + /* 000000EB nop */ 0x90,=0D + /* 000000EC nop */ 0x90,=0D + /* 000000ED nop */ 0x90,=0D + /* 000000EE nop */ 0x90,=0D + /* 000000EF nop */ 0x90,=0D + /* 000000F0 nop */ 0x90,=0D + /* 000000F1 nop */ 0x90,=0D + /* 000000F2 nop */ 0x90,=0D + /* 000000F3 nop */ 0x90,=0D + /* 000000F4 nop */ 0x90,=0D + /* 000000F5 nop */ 0x90,=0D + /* 000000F6 nop */ 0x90,=0D + /* 000000F7 nop */ 0x90,=0D + /* 000000F8 nop */ 0x90,=0D + /* 000000F9 nop */ 0x90,=0D + /* 000000FA nop */ 0x90,=0D + /* 000000FB nop */ 0x90,=0D + /* 000000FC nop */ 0x90,=0D + /* 000000FD nop */ 0x90,=0D + /* 000000FE nop */ 0x90,=0D + /* 000000FF nop */ 0x90,=0D + /* 00000100 nop */ 0x90,=0D + /* 00000101 nop */ 0x90,=0D + /* 00000102 nop */ 0x90,=0D + /* 00000103 nop */ 0x90,=0D + /* 00000104 nop */ 0x90,=0D + /* 00000105 nop */ 0x90,=0D + /* 00000106 nop */ 0x90,=0D + /* 00000107 nop */ 0x90,=0D + /* 00000108 nop */ 0x90,=0D + /* 00000109 nop */ 0x90,=0D + /* 0000010A nop */ 0x90,=0D + /* 0000010B nop */ 0x90,=0D + /* 0000010C nop */ 0x90,=0D + /* 0000010D nop */ 0x90,=0D + /* 0000010E nop */ 0x90,=0D + /* 0000010F nop */ 0x90,=0D + /* 00000110 nop */ 0x90,=0D + /* 00000111 nop */ 0x90,=0D + /* 00000112 nop */ 0x90,=0D + /* 00000113 nop */ 0x90,=0D + /* 00000114 nop */ 0x90,=0D + /* 00000115 nop */ 0x90,=0D + /* 00000116 nop */ 0x90,=0D + /* 00000117 nop */ 0x90,=0D + /* 00000118 nop */ 0x90,=0D + /* 00000119 nop */ 0x90,=0D + /* 0000011A nop */ 0x90,=0D + /* 0000011B nop */ 0x90,=0D + /* 0000011C nop */ 0x90,=0D + /* 0000011D nop */ 0x90,=0D + /* 0000011E nop */ 0x90,=0D + /* 0000011F nop */ 0x90,=0D + /* 00000120 nop */ 0x90,=0D + /* 00000121 nop */ 0x90,=0D + /* 00000122 nop */ 0x90,=0D + /* 00000123 nop */ 0x90,=0D + /* 00000124 nop */ 0x90,=0D + /* 00000125 nop */ 0x90,=0D + /* 00000126 nop */ 0x90,=0D + /* 00000127 nop */ 0x90,=0D + /* 00000128 nop */ 0x90,=0D + /* 00000129 nop */ 0x90,=0D + /* 0000012A nop */ 0x90,=0D + /* 0000012B nop */ 0x90,=0D + /* 0000012C nop */ 0x90,=0D + /* 0000012D nop */ 0x90,=0D + /* 0000012E nop */ 0x90,=0D + /* 0000012F nop */ 0x90,=0D + /* 00000130 nop */ 0x90,=0D + /* 00000131 nop */ 0x90,=0D + /* 00000132 nop */ 0x90,=0D + /* 00000133 nop */ 0x90,=0D + /* 00000134 nop */ 0x90,=0D + /* 00000135 nop */ 0x90,=0D + /* 00000136 nop */ 0x90,=0D + /* 00000137 nop */ 0x90,=0D + /* 00000138 nop */ 0x90,=0D + /* 00000139 nop */ 0x90,=0D + /* 0000013A nop */ 0x90,=0D + /* 0000013B nop */ 0x90,=0D + /* 0000013C nop */ 0x90,=0D + /* 0000013D nop */ 0x90,=0D + /* 0000013E nop */ 0x90,=0D + /* 0000013F nop */ 0x90,=0D + /* 00000140 nop */ 0x90,=0D + /* 00000141 nop */ 0x90,=0D + /* 00000142 nop */ 0x90,=0D + /* 00000143 nop */ 0x90,=0D + /* 00000144 nop */ 0x90,=0D + /* 00000145 nop */ 0x90,=0D + /* 00000146 nop */ 0x90,=0D + /* 00000147 nop */ 0x90,=0D + /* 00000148 nop */ 0x90,=0D + /* 00000149 nop */ 0x90,=0D + /* 0000014A nop */ 0x90,=0D + /* 0000014B nop */ 0x90,=0D + /* 0000014C nop */ 0x90,=0D + /* 0000014D nop */ 0x90,=0D + /* 0000014E nop */ 0x90,=0D + /* 0000014F nop */ 0x90,=0D + /* 00000150 nop */ 0x90,=0D + /* 00000151 nop */ 0x90,=0D + /* 00000152 nop */ 0x90,=0D + /* 00000153 nop */ 0x90,=0D + /* 00000154 nop */ 0x90,=0D + /* 00000155 nop */ 0x90,=0D + /* 00000156 nop */ 0x90,=0D + /* 00000157 nop */ 0x90,=0D + /* 00000158 nop */ 0x90,=0D + /* 00000159 nop */ 0x90,=0D + /* 0000015A nop */ 0x90,=0D + /* 0000015B nop */ 0x90,=0D + /* 0000015C nop */ 0x90,=0D + /* 0000015D nop */ 0x90,=0D + /* 0000015E nop */ 0x90,=0D + /* 0000015F nop */ 0x90,=0D + /* 00000160 nop */ 0x90,=0D + /* 00000161 nop */ 0x90,=0D + /* 00000162 nop */ 0x90,=0D + /* 00000163 nop */ 0x90,=0D + /* 00000164 nop */ 0x90,=0D + /* 00000165 nop */ 0x90,=0D + /* 00000166 nop */ 0x90,=0D + /* 00000167 nop */ 0x90,=0D + /* 00000168 nop */ 0x90,=0D + /* 00000169 nop */ 0x90,=0D + /* 0000016A nop */ 0x90,=0D + /* 0000016B nop */ 0x90,=0D + /* 0000016C nop */ 0x90,=0D + /* 0000016D nop */ 0x90,=0D + /* 0000016E nop */ 0x90,=0D + /* 0000016F nop */ 0x90,=0D + /* 00000170 nop */ 0x90,=0D + /* 00000171 nop */ 0x90,=0D + /* 00000172 nop */ 0x90,=0D + /* 00000173 nop */ 0x90,=0D + /* 00000174 nop */ 0x90,=0D + /* 00000175 nop */ 0x90,=0D + /* 00000176 nop */ 0x90,=0D + /* 00000177 nop */ 0x90,=0D + /* 00000178 nop */ 0x90,=0D + /* 00000179 nop */ 0x90,=0D + /* 0000017A nop */ 0x90,=0D + /* 0000017B nop */ 0x90,=0D + /* 0000017C nop */ 0x90,=0D + /* 0000017D nop */ 0x90,=0D + /* 0000017E nop */ 0x90,=0D + /* 0000017F nop */ 0x90,=0D + /* 00000180 nop */ 0x90,=0D + /* 00000181 nop */ 0x90,=0D + /* 00000182 nop */ 0x90,=0D + /* 00000183 nop */ 0x90,=0D + /* 00000184 nop */ 0x90,=0D + /* 00000185 nop */ 0x90,=0D + /* 00000186 nop */ 0x90,=0D + /* 00000187 nop */ 0x90,=0D + /* 00000188 nop */ 0x90,=0D + /* 00000189 nop */ 0x90,=0D + /* 0000018A nop */ 0x90,=0D + /* 0000018B nop */ 0x90,=0D + /* 0000018C nop */ 0x90,=0D + /* 0000018D nop */ 0x90,=0D + /* 0000018E nop */ 0x90,=0D + /* 0000018F nop */ 0x90,=0D + /* 00000190 nop */ 0x90,=0D + /* 00000191 nop */ 0x90,=0D + /* 00000192 nop */ 0x90,=0D + /* 00000193 nop */ 0x90,=0D + /* 00000194 nop */ 0x90,=0D + /* 00000195 nop */ 0x90,=0D + /* 00000196 nop */ 0x90,=0D + /* 00000197 nop */ 0x90,=0D + /* 00000198 nop */ 0x90,=0D + /* 00000199 nop */ 0x90,=0D + /* 0000019A nop */ 0x90,=0D + /* 0000019B nop */ 0x90,=0D + /* 0000019C nop */ 0x90,=0D + /* 0000019D nop */ 0x90,=0D + /* 0000019E nop */ 0x90,=0D + /* 0000019F nop */ 0x90,=0D + /* 000001A0 nop */ 0x90,=0D + /* 000001A1 nop */ 0x90,=0D + /* 000001A2 nop */ 0x90,=0D + /* 000001A3 nop */ 0x90,=0D + /* 000001A4 nop */ 0x90,=0D + /* 000001A5 nop */ 0x90,=0D + /* 000001A6 nop */ 0x90,=0D + /* 000001A7 nop */ 0x90,=0D + /* 000001A8 nop */ 0x90,=0D + /* 000001A9 nop */ 0x90,=0D + /* 000001AA nop */ 0x90,=0D + /* 000001AB nop */ 0x90,=0D + /* 000001AC nop */ 0x90,=0D + /* 000001AD nop */ 0x90,=0D + /* 000001AE nop */ 0x90,=0D + /* 000001AF nop */ 0x90,=0D + /* 000001B0 nop */ 0x90,=0D + /* 000001B1 nop */ 0x90,=0D + /* 000001B2 nop */ 0x90,=0D + /* 000001B3 nop */ 0x90,=0D + /* 000001B4 nop */ 0x90,=0D + /* 000001B5 nop */ 0x90,=0D + /* 000001B6 nop */ 0x90,=0D + /* 000001B7 nop */ 0x90,=0D + /* 000001B8 nop */ 0x90,=0D + /* 000001B9 nop */ 0x90,=0D + /* 000001BA nop */ 0x90,=0D + /* 000001BB nop */ 0x90,=0D + /* 000001BC nop */ 0x90,=0D + /* 000001BD nop */ 0x90,=0D + /* 000001BE nop */ 0x90,=0D + /* 000001BF nop */ 0x90,=0D + /* 000001C0 nop */ 0x90,=0D + /* 000001C1 nop */ 0x90,=0D + /* 000001C2 nop */ 0x90,=0D + /* 000001C3 nop */ 0x90,=0D + /* 000001C4 nop */ 0x90,=0D + /* 000001C5 nop */ 0x90,=0D + /* 000001C6 nop */ 0x90,=0D + /* 000001C7 nop */ 0x90,=0D + /* 000001C8 nop */ 0x90,=0D + /* 000001C9 nop */ 0x90,=0D + /* 000001CA nop */ 0x90,=0D + /* 000001CB nop */ 0x90,=0D + /* 000001CC nop */ 0x90,=0D + /* 000001CD nop */ 0x90,=0D + /* 000001CE nop */ 0x90,=0D + /* 000001CF nop */ 0x90,=0D + /* 000001D0 nop */ 0x90,=0D + /* 000001D1 nop */ 0x90,=0D + /* 000001D2 nop */ 0x90,=0D + /* 000001D3 nop */ 0x90,=0D + /* 000001D4 nop */ 0x90,=0D + /* 000001D5 nop */ 0x90,=0D + /* 000001D6 nop */ 0x90,=0D + /* 000001D7 nop */ 0x90,=0D + /* 000001D8 nop */ 0x90,=0D + /* 000001D9 nop */ 0x90,=0D + /* 000001DA nop */ 0x90,=0D + /* 000001DB nop */ 0x90,=0D + /* 000001DC nop */ 0x90,=0D + /* 000001DD nop */ 0x90,=0D + /* 000001DE nop */ 0x90,=0D + /* 000001DF nop */ 0x90,=0D + /* 000001E0 nop */ 0x90,=0D + /* 000001E1 nop */ 0x90,=0D + /* 000001E2 nop */ 0x90,=0D + /* 000001E3 nop */ 0x90,=0D + /* 000001E4 nop */ 0x90,=0D + /* 000001E5 nop */ 0x90,=0D + /* 000001E6 nop */ 0x90,=0D + /* 000001E7 nop */ 0x90,=0D + /* 000001E8 nop */ 0x90,=0D + /* 000001E9 nop */ 0x90,=0D + /* 000001EA nop */ 0x90,=0D + /* 000001EB nop */ 0x90,=0D + /* 000001EC nop */ 0x90,=0D + /* 000001ED nop */ 0x90,=0D + /* 000001EE nop */ 0x90,=0D + /* 000001EF nop */ 0x90,=0D + /* 000001F0 nop */ 0x90,=0D + /* 000001F1 nop */ 0x90,=0D + /* 000001F2 nop */ 0x90,=0D + /* 000001F3 nop */ 0x90,=0D + /* 000001F4 nop */ 0x90,=0D + /* 000001F5 nop */ 0x90,=0D + /* 000001F6 nop */ 0x90,=0D + /* 000001F7 nop */ 0x90,=0D + /* 000001F8 nop */ 0x90,=0D + /* 000001F9 nop */ 0x90,=0D + /* 000001FA nop */ 0x90,=0D + /* 000001FB nop */ 0x90,=0D + /* 000001FC nop */ 0x90,=0D + /* 000001FD nop */ 0x90,=0D + /* 000001FE nop */ 0x90,=0D + /* 000001FF nop */ 0x90,=0D + /* 00000200 cmp ax,0x4f00 */ 0x3D, 0x00, 0x4F,=0D + /* 00000203 jz 0x237 */ 0x74, 0x32,=0D + /* 00000205 cmp ax,0x4f01 */ 0x3D, 0x01, 0x4F,=0D + /* 00000208 jz 0x257 */ 0x74, 0x4D,=0D + /* 0000020A cmp ax,0x4f02 */ 0x3D, 0x02, 0x4F,=0D + /* 0000020D jz word 0x2c8 */ 0x0F, 0x84, 0xB7, 0x00,=0D + /* 00000211 cmp ax,0x4f03 */ 0x3D, 0x03, 0x4F,=0D + /* 00000214 jz word 0x325 */ 0x0F, 0x84, 0x0D, 0x01,=0D + /* 00000218 cmp ax,0x4f10 */ 0x3D, 0x10, 0x4F,=0D + /* 0000021B jz word 0x337 */ 0x0F, 0x84, 0x18, 0x01,=0D + /* 0000021F cmp ax,0x4f15 */ 0x3D, 0x15, 0x4F,=0D + /* 00000222 jz word 0x344 */ 0x0F, 0x84, 0x1E, 0x01,=0D + /* 00000226 cmp ah,0x0 */ 0x80, 0xFC, 0x00,=0D + /* 00000229 jz word 0x363 */ 0x0F, 0x84, 0x36, 0x01,=0D + /* 0000022D push si */ 0x56,=0D + /* 0000022E mov si,0x3d7 */ 0xBE, 0xD7, 0x03,=0D + /* 00000231 call word 0x3ad */ 0xE8, 0x79, 0x01,=0D + /* 00000234 pop si */ 0x5E,=0D + /* 00000235 jmp short 0x235 */ 0xEB, 0xFE,=0D + /* 00000237 push es */ 0x06,=0D + /* 00000238 push di */ 0x57,=0D + /* 00000239 push ds */ 0x1E,=0D + /* 0000023A push si */ 0x56,=0D + /* 0000023B push cx */ 0x51,=0D + /* 0000023C push si */ 0x56,=0D + /* 0000023D mov si,0x3eb */ 0xBE, 0xEB, 0x03,=0D + /* 00000240 call word 0x3ad */ 0xE8, 0x6A, 0x01,=0D + /* 00000243 pop si */ 0x5E,=0D + /* 00000244 push cs */ 0x0E,=0D + /* 00000245 pop ds */ 0x1F,=0D + /* 00000246 mov si,0x0 */ 0xBE, 0x00, 0x00,=0D + /* 00000249 mov cx,0x100 */ 0xB9, 0x00, 0x01,=0D + /* 0000024C cld */ 0xFC,=0D + /* 0000024D rep movsb */ 0xF3, 0xA4,=0D + /* 0000024F pop cx */ 0x59,=0D + /* 00000250 pop si */ 0x5E,=0D + /* 00000251 pop ds */ 0x1F,=0D + /* 00000252 pop di */ 0x5F,=0D + /* 00000253 pop es */ 0x07,=0D + /* 00000254 jmp word 0x395 */ 0xE9, 0x3E, 0x01,=0D + /* 00000257 push es */ 0x06,=0D + /* 00000258 push di */ 0x57,=0D + /* 00000259 push ds */ 0x1E,=0D + /* 0000025A push si */ 0x56,=0D + /* 0000025B push cx */ 0x51,=0D + /* 0000025C push si */ 0x56,=0D + /* 0000025D mov si,0x3f6 */ 0xBE, 0xF6, 0x03,=0D + /* 00000260 call word 0x3ad */ 0xE8, 0x4A, 0x01,=0D + /* 00000263 pop si */ 0x5E,=0D + /* 00000264 and cx,0xbfff */ 0x81, 0xE1, 0xFF, 0xBF,=0D + /* 00000268 cmp cx,0x13f */ 0x81, 0xF9, 0x3F, 0x01,=0D + /* 0000026C jz 0x284 */ 0x74, 0x16,=0D + /* 0000026E cmp cx,0x140 */ 0x81, 0xF9, 0x40, 0x01,=0D + /* 00000272 jz 0x291 */ 0x74, 0x1D,=0D + /* 00000274 cmp cx,0x141 */ 0x81, 0xF9, 0x41, 0x01,=0D + /* 00000278 jz 0x29e */ 0x74, 0x24,=0D + /* 0000027A push si */ 0x56,=0D + /* 0000027B mov si,0x42c */ 0xBE, 0x2C, 0x04,=0D + /* 0000027E call word 0x3ad */ 0xE8, 0x2C, 0x01,=0D + /* 00000281 pop si */ 0x5E,=0D + /* 00000282 jmp short 0x235 */ 0xEB, 0xB1,=0D + /* 00000284 push si */ 0x56,=0D + /* 00000285 mov si,0x46b */ 0xBE, 0x6B, 0x04,=0D + /* 00000288 call word 0x3ad */ 0xE8, 0x22, 0x01,=0D + /* 0000028B pop si */ 0x5E,=0D + /* 0000028C mov si,0x100 */ 0xBE, 0x00, 0x01,=0D + /* 0000028F jmp short 0x2b8 */ 0xEB, 0x27,=0D + /* 00000291 push si */ 0x56,=0D + /* 00000292 mov si,0x47d */ 0xBE, 0x7D, 0x04,=0D + /* 00000295 call word 0x3ad */ 0xE8, 0x15, 0x01,=0D + /* 00000298 pop si */ 0x5E,=0D + /* 00000299 mov si,0x132 */ 0xBE, 0x32, 0x01,=0D + /* 0000029C jmp short 0x2b8 */ 0xEB, 0x1A,=0D + /* 0000029E push si */ 0x56,=0D + /* 0000029F mov si,0x48f */ 0xBE, 0x8F, 0x04,=0D + /* 000002A2 call word 0x3ad */ 0xE8, 0x08, 0x01,=0D + /* 000002A5 pop si */ 0x5E,=0D + /* 000002A6 mov si,0x164 */ 0xBE, 0x64, 0x01,=0D + /* 000002A9 jmp short 0x2b8 */ 0xEB, 0x0D,=0D + /* 000002AB push si */ 0x56,=0D + /* 000002AC mov si,0x4a2 */ 0xBE, 0xA2, 0x04,=0D + /* 000002AF call word 0x3ad */ 0xE8, 0xFB, 0x00,=0D + /* 000002B2 pop si */ 0x5E,=0D + /* 000002B3 mov si,0x196 */ 0xBE, 0x96, 0x01,=0D + /* 000002B6 jmp short 0x2b8 */ 0xEB, 0x00,=0D + /* 000002B8 push cs */ 0x0E,=0D + /* 000002B9 pop ds */ 0x1F,=0D + /* 000002BA mov cx,0x32 */ 0xB9, 0x32, 0x00,=0D + /* 000002BD cld */ 0xFC,=0D + /* 000002BE rep movsb */ 0xF3, 0xA4,=0D + /* 000002C0 pop cx */ 0x59,=0D + /* 000002C1 pop si */ 0x5E,=0D + /* 000002C2 pop ds */ 0x1F,=0D + /* 000002C3 pop di */ 0x5F,=0D + /* 000002C4 pop es */ 0x07,=0D + /* 000002C5 jmp word 0x395 */ 0xE9, 0xCD, 0x00,=0D + /* 000002C8 push dx */ 0x52,=0D + /* 000002C9 push ax */ 0x50,=0D + /* 000002CA push si */ 0x56,=0D + /* 000002CB mov si,0x410 */ 0xBE, 0x10, 0x04,=0D + /* 000002CE call word 0x3ad */ 0xE8, 0xDC, 0x00,=0D + /* 000002D1 pop si */ 0x5E,=0D + /* 000002D2 and bx,0xbfff */ 0x81, 0xE3, 0xFF, 0xBF,=0D + /* 000002D6 cmp bx,0x13f */ 0x81, 0xFB, 0x3F, 0x01,=0D + /* 000002DA jz 0x2f3 */ 0x74, 0x17,=0D + /* 000002DC cmp bx,0x140 */ 0x81, 0xFB, 0x40, 0x01,=0D + /* 000002E0 jz 0x2fd */ 0x74, 0x1B,=0D + /* 000002E2 cmp bx,0x141 */ 0x81, 0xFB, 0x41, 0x01,=0D + /* 000002E6 jz 0x307 */ 0x74, 0x1F,=0D + /* 000002E8 push si */ 0x56,=0D + /* 000002E9 mov si,0x42c */ 0xBE, 0x2C, 0x04,=0D + /* 000002EC call word 0x3ad */ 0xE8, 0xBE, 0x00,=0D + /* 000002EF pop si */ 0x5E,=0D + /* 000002F0 jmp word 0x235 */ 0xE9, 0x42, 0xFF,=0D + /* 000002F3 push si */ 0x56,=0D + /* 000002F4 mov si,0x46b */ 0xBE, 0x6B, 0x04,=0D + /* 000002F7 call word 0x3ad */ 0xE8, 0xB3, 0x00,=0D + /* 000002FA pop si */ 0x5E,=0D + /* 000002FB jmp short 0x319 */ 0xEB, 0x1C,=0D + /* 000002FD push si */ 0x56,=0D + /* 000002FE mov si,0x47d */ 0xBE, 0x7D, 0x04,=0D + /* 00000301 call word 0x3ad */ 0xE8, 0xA9, 0x00,=0D + /* 00000304 pop si */ 0x5E,=0D + /* 00000305 jmp short 0x319 */ 0xEB, 0x12,=0D + /* 00000307 push si */ 0x56,=0D + /* 00000308 mov si,0x48f */ 0xBE, 0x8F, 0x04,=0D + /* 0000030B call word 0x3ad */ 0xE8, 0x9F, 0x00,=0D + /* 0000030E pop si */ 0x5E,=0D + /* 0000030F jmp short 0x319 */ 0xEB, 0x08,=0D + /* 00000311 push si */ 0x56,=0D + /* 00000312 mov si,0x4a2 */ 0xBE, 0xA2, 0x04,=0D + /* 00000315 call word 0x3ad */ 0xE8, 0x95, 0x00,=0D + /* 00000318 pop si */ 0x5E,=0D + /* 00000319 mov [0x4b0],bl */ 0x88, 0x1E, 0xB0, 0x04,=0D + /* 0000031D mov [0x4b1],bh */ 0x88, 0x3E, 0xB1, 0x04,=0D + /* 00000321 pop ax */ 0x58,=0D + /* 00000322 pop dx */ 0x5A,=0D + /* 00000323 jmp short 0x395 */ 0xEB, 0x70,=0D + /* 00000325 push si */ 0x56,=0D + /* 00000326 mov si,0x405 */ 0xBE, 0x05, 0x04,=0D + /* 00000329 call word 0x3ad */ 0xE8, 0x81, 0x00,=0D + /* 0000032C pop si */ 0x5E,=0D + /* 0000032D mov bl,[0x4b0] */ 0x8A, 0x1E, 0xB0, 0x04,=0D + /* 00000331 mov bh,[0x4b1] */ 0x8A, 0x3E, 0xB1, 0x04,=0D + /* 00000335 jmp short 0x395 */ 0xEB, 0x5E,=0D + /* 00000337 push si */ 0x56,=0D + /* 00000338 mov si,0x43b */ 0xBE, 0x3B, 0x04,=0D + /* 0000033B call word 0x3ad */ 0xE8, 0x6F, 0x00,=0D + /* 0000033E pop si */ 0x5E,=0D + /* 0000033F mov bx,0x80 */ 0xBB, 0x80, 0x00,=0D + /* 00000342 jmp short 0x395 */ 0xEB, 0x51,=0D + /* 00000344 push es */ 0x06,=0D + /* 00000345 push di */ 0x57,=0D + /* 00000346 push ds */ 0x1E,=0D + /* 00000347 push si */ 0x56,=0D + /* 00000348 push cx */ 0x51,=0D + /* 00000349 push si */ 0x56,=0D + /* 0000034A mov si,0x450 */ 0xBE, 0x50, 0x04,=0D + /* 0000034D call word 0x3ad */ 0xE8, 0x5D, 0x00,=0D + /* 00000350 pop si */ 0x5E,=0D + /* 00000351 push cs */ 0x0E,=0D + /* 00000352 pop ds */ 0x1F,=0D + /* 00000353 mov si,0x4b2 */ 0xBE, 0xB2, 0x04,=0D + /* 00000356 mov cx,0x80 */ 0xB9, 0x80, 0x00,=0D + /* 00000359 cld */ 0xFC,=0D + /* 0000035A rep movsb */ 0xF3, 0xA4,=0D + /* 0000035C pop cx */ 0x59,=0D + /* 0000035D pop si */ 0x5E,=0D + /* 0000035E pop ds */ 0x1F,=0D + /* 0000035F pop di */ 0x5F,=0D + /* 00000360 pop es */ 0x07,=0D + /* 00000361 jmp short 0x395 */ 0xEB, 0x32,=0D + /* 00000363 push si */ 0x56,=0D + /* 00000364 mov si,0x41b */ 0xBE, 0x1B, 0x04,=0D + /* 00000367 call word 0x3ad */ 0xE8, 0x43, 0x00,=0D + /* 0000036A pop si */ 0x5E,=0D + /* 0000036B cmp al,0x3 */ 0x3C, 0x03,=0D + /* 0000036D jz 0x37e */ 0x74, 0x0F,=0D + /* 0000036F cmp al,0x12 */ 0x3C, 0x12,=0D + /* 00000371 jz 0x38a */ 0x74, 0x17,=0D + /* 00000373 push si */ 0x56,=0D + /* 00000374 mov si,0x42c */ 0xBE, 0x2C, 0x04,=0D + /* 00000377 call word 0x3ad */ 0xE8, 0x33, 0x00,=0D + /* 0000037A pop si */ 0x5E,=0D + /* 0000037B jmp word 0x235 */ 0xE9, 0xB7, 0xFE,=0D + /* 0000037E push si */ 0x56,=0D + /* 0000037F mov si,0x45c */ 0xBE, 0x5C, 0x04,=0D + /* 00000382 call word 0x3ad */ 0xE8, 0x28, 0x00,=0D + /* 00000385 pop si */ 0x5E,=0D + /* 00000386 mov al,0x0 */ 0xB0, 0x00,=0D + /* 00000388 jmp short 0x38c */ 0xEB, 0x02,=0D + /* 0000038A mov al,0x0 */ 0xB0, 0x00,=0D + /* 0000038C push si */ 0x56,=0D + /* 0000038D mov si,0x3c2 */ 0xBE, 0xC2, 0x03,=0D + /* 00000390 call word 0x3ad */ 0xE8, 0x1A, 0x00,=0D + /* 00000393 pop si */ 0x5E,=0D + /* 00000394 iretw */ 0xCF,=0D + /* 00000395 push si */ 0x56,=0D + /* 00000396 mov si,0x3c2 */ 0xBE, 0xC2, 0x03,=0D + /* 00000399 call word 0x3ad */ 0xE8, 0x11, 0x00,=0D + /* 0000039C pop si */ 0x5E,=0D + /* 0000039D mov ax,0x4f */ 0xB8, 0x4F, 0x00,=0D + /* 000003A0 iretw */ 0xCF,=0D + /* 000003A1 push si */ 0x56,=0D + /* 000003A2 mov si,0x3c8 */ 0xBE, 0xC8, 0x03,=0D + /* 000003A5 call word 0x3ad */ 0xE8, 0x05, 0x00,=0D + /* 000003A8 pop si */ 0x5E,=0D + /* 000003A9 mov ax,0x24f */ 0xB8, 0x4F, 0x02,=0D + /* 000003AC iretw */ 0xCF,=0D + /* 000003AD pushaw */ 0x60,=0D + /* 000003AE push ds */ 0x1E,=0D + /* 000003AF push cs */ 0x0E,=0D + /* 000003B0 pop ds */ 0x1F,=0D + /* 000003B1 mov dx,0x220 */ 0xBA, 0x20, 0x02,=0D + /* 000003B4 mov ax,0x0 */ 0xB8, 0x00, 0x00,=0D + /* 000003B7 lodsb */ 0xAC,=0D + /* 000003B8 cmp al,0x0 */ 0x3C, 0x00,=0D + /* 000003BA jz 0x3bf */ 0x74, 0x03,=0D + /* 000003BC out dx,al */ 0xEE,=0D + /* 000003BD jmp short 0x3b7 */ 0xEB, 0xF8,=0D + /* 000003BF pop ds */ 0x1F,=0D + /* 000003C0 popaw */ 0x61,=0D + /* 000003C1 ret */ 0xC3,=0D + /* 000003C2 jna 0x413 */ 0x76, 0x4F,=0D + /* 000003C4 imul cx,[di],byte +0xa */ 0x6B, 0x0D, 0x0A,=0D + /* 000003C7 add [bp+0x55],dh */ 0x00, 0x76, 0x55,=0D + /* 000003CA outsb */ 0x6E,=0D + /* 000003CB jnc 0x442 */ 0x73, 0x75,=0D + /* 000003CD jo 0x43f */ 0x70, 0x70,=0D + /* 000003CF outsw */ 0x6F,=0D + /* 000003D0 jc 0x446 */ 0x72, 0x74,=0D + /* 000003D2 fs or ax,0xa */ 0x65, 0x64, 0x0D, 0x0A, 0= x00,=0D + /* 000003D7 jna 0x42e */ 0x76, 0x55,=0D + /* 000003D9 outsb */ 0x6E,=0D + /* 000003DA imul bp,[bp+0x6f],byte +0x77 */ 0x6B, 0x6E, 0x6F, 0x77,=0D + /* 000003DE outsb */ 0x6E,=0D + /* 000003DF and [bp+0x75],al */ 0x20, 0x46, 0x75,=0D + /* 000003E2 outsb */ 0x6E,=0D + /* 000003E3 arpl [si+0x69],si */ 0x63, 0x74, 0x69,=0D + /* 000003E6 outsw */ 0x6F,=0D + /* 000003E7 outsb */ 0x6E,=0D + /* 000003E8 or ax,0xa */ 0x0D, 0x0A, 0x00,=0D + /* 000003EB jna 0x434 */ 0x76, 0x47,=0D + /* 000003ED gs jz 0x439 */ 0x65, 0x74, 0x49,=0D + /* 000003F0 outsb */ 0x6E,=0D + /* 000003F1 outsd */ 0x66, 0x6F,=0D + /* 000003F3 or ax,0xa */ 0x0D, 0x0A, 0x00,=0D + /* 000003F6 jna 0x43f */ 0x76, 0x47,=0D + /* 000003F8 gs jz 0x448 */ 0x65, 0x74, 0x4D,=0D + /* 000003FB outsw */ 0x6F,=0D + /* 000003FC gs dec cx */ 0x64, 0x65, 0x49,=0D + /* 000003FF outsb */ 0x6E,=0D + /* 00000400 outsd */ 0x66, 0x6F,=0D + /* 00000402 or ax,0xa */ 0x0D, 0x0A, 0x00,=0D + /* 00000405 jna 0x44e */ 0x76, 0x47,=0D + /* 00000407 gs jz 0x457 */ 0x65, 0x74, 0x4D,=0D + /* 0000040A outsw */ 0x6F,=0D + /* 0000040B gs or ax,0xa */ 0x64, 0x65, 0x0D, 0x0A, 0= x00,=0D + /* 00000410 jna 0x465 */ 0x76, 0x53,=0D + /* 00000412 gs jz 0x462 */ 0x65, 0x74, 0x4D,=0D + /* 00000415 outsw */ 0x6F,=0D + /* 00000416 gs or ax,0xa */ 0x64, 0x65, 0x0D, 0x0A, 0= x00,=0D + /* 0000041B jna 0x470 */ 0x76, 0x53,=0D + /* 0000041D gs jz 0x46d */ 0x65, 0x74, 0x4D,=0D + /* 00000420 outsw */ 0x6F,=0D + /* 00000421 gs dec sp */ 0x64, 0x65, 0x4C,=0D + /* 00000424 gs a32 popaw */ 0x65, 0x67, 0x61,=0D + /* 00000427 arpl [bx+di+0xd],di */ 0x63, 0x79, 0x0D,=0D + /* 0000042A or al,[bx+si] */ 0x0A, 0x00,=0D + /* 0000042C jna 0x483 */ 0x76, 0x55,=0D + /* 0000042E outsb */ 0x6E,=0D + /* 0000042F imul bp,[bx+0x77],byte +0x6e */ 0x6B, 0x6F, 0x77, 0x6E,=0D + /* 00000433 and [di+0x6f],cl */ 0x20, 0x4D, 0x6F,=0D + /* 00000436 gs or ax,0xa */ 0x64, 0x65, 0x0D, 0x0A, 0= x00,=0D + /* 0000043B jna 0x484 */ 0x76, 0x47,=0D + /* 0000043D gs jz 0x490 */ 0x65, 0x74, 0x50,=0D + /* 00000440 insw */ 0x6D,=0D + /* 00000441 inc bx */ 0x43,=0D + /* 00000442 popaw */ 0x61,=0D + /* 00000443 jo 0x4a6 */ 0x70, 0x61,=0D + /* 00000445 bound bp,[bx+di+0x6c] */ 0x62, 0x69, 0x6C,=0D + /* 00000448 imul si,[si+0x69],word 0x7365 */ 0x69, 0x74, 0x69, 0x65, 0= x73,=0D + /* 0000044D or ax,0xa */ 0x0D, 0x0A, 0x00,=0D + /* 00000450 jna 0x4a4 */ 0x76, 0x52,=0D + /* 00000452 gs popaw */ 0x65, 0x61,=0D + /* 00000454 fs inc bp */ 0x64, 0x45,=0D + /* 00000456 imul sp,[fs:si+0xd],word 0xa */ 0x64, 0x69, 0x64, 0x0D, 0= x0A, 0x00,=0D + /* 0000045C jna 0x4aa */ 0x76, 0x4C,=0D + /* 0000045E gs a32 popaw */ 0x65, 0x67, 0x61,=0D + /* 00000461 arpl [bx+di+0x4d],di */ 0x63, 0x79, 0x4D,=0D + /* 00000464 outsw */ 0x6F,=0D + /* 00000465 xor cx,[gs:di] */ 0x64, 0x65, 0x33, 0x0D,=0D + /* 00000469 or al,[bx+si] */ 0x0A, 0x00,=0D + /* 0000046B insw */ 0x6D,=0D + /* 0000046C outsw */ 0x6F,=0D + /* 0000046D gs pop di */ 0x64, 0x65, 0x5F,=0D + /* 00000470 ss xor al,0x30 */ 0x36, 0x34, 0x30,=0D + /* 00000473 js 0x4a9 */ 0x78, 0x34,=0D + /* 00000475 cmp [bx+si],dh */ 0x38, 0x30,=0D + /* 00000477 js 0x4ac */ 0x78, 0x33,=0D + /* 00000479 xor cl,[di] */ 0x32, 0x0D,=0D + /* 0000047B or al,[bx+si] */ 0x0A, 0x00,=0D + /* 0000047D insw */ 0x6D,=0D + /* 0000047E outsw */ 0x6F,=0D + /* 0000047F gs pop di */ 0x64, 0x65, 0x5F,=0D + /* 00000482 cmp [bx+si],dh */ 0x38, 0x30,=0D + /* 00000484 xor [bx+si+0x36],bh */ 0x30, 0x78, 0x36,=0D + /* 00000487 xor [bx+si],dh */ 0x30, 0x30,=0D + /* 00000489 js 0x4be */ 0x78, 0x33,=0D + /* 0000048B xor cl,[di] */ 0x32, 0x0D,=0D + /* 0000048D or al,[bx+si] */ 0x0A, 0x00,=0D + /* 0000048F insw */ 0x6D,=0D + /* 00000490 outsw */ 0x6F,=0D + /* 00000491 gs pop di */ 0x64, 0x65, 0x5F,=0D + /* 00000494 xor [bx+si],si */ 0x31, 0x30,=0D + /* 00000496 xor dh,[si] */ 0x32, 0x34,=0D + /* 00000498 js 0x4d1 */ 0x78, 0x37,=0D + /* 0000049A cmp [ss:bx+si+0x33],bh */ 0x36, 0x38, 0x78, 0x33,=0D + /* 0000049E xor cl,[di] */ 0x32, 0x0D,=0D + /* 000004A0 or al,[bx+si] */ 0x0A, 0x00,=0D + /* 000004A2 insw */ 0x6D,=0D + /* 000004A3 outsw */ 0x6F,=0D + /* 000004A4 gs pop di */ 0x64, 0x65, 0x5F,=0D + /* 000004A7 jnz 0x517 */ 0x75, 0x6E,=0D + /* 000004A9 jnz 0x51e */ 0x75, 0x73,=0D + /* 000004AB fs or ax,0xa */ 0x65, 0x64, 0x0D, 0x0A, 0= x00,=0D + /* 000004B0 add [bx+si],al */ 0x00, 0x00,=0D + /* 000004B2 add [bx+si],al */ 0x00, 0x00,=0D + /* 000004B4 add [bx+si],al */ 0x00, 0x00,=0D + /* 000004B6 add [bx+si],al */ 0x00, 0x00,=0D + /* 000004B8 add [bx+si],al */ 0x00, 0x00,=0D + /* 000004BA add [bx+si],al */ 0x00, 0x00,=0D + /* 000004BC add [bx+si],al */ 0x00, 0x00,=0D + /* 000004BE add [bx+si],al */ 0x00, 0x00,=0D + /* 000004C0 add [bx+si],al */ 0x00, 0x00,=0D + /* 000004C2 add [bx+si],al */ 0x00, 0x00,=0D + /* 000004C4 add [bx+si],al */ 0x00, 0x00,=0D + /* 000004C6 add [bx+si],al */ 0x00, 0x00,=0D + /* 000004C8 add [bx+si],al */ 0x00, 0x00,=0D + /* 000004CA add [bx+si],al */ 0x00, 0x00,=0D + /* 000004CC add [bx+si],al */ 0x00, 0x00,=0D + /* 000004CE add [bx+si],al */ 0x00, 0x00,=0D + /* 000004D0 add [bx+si],al */ 0x00, 0x00,=0D + /* 000004D2 add [bx+si],al */ 0x00, 0x00,=0D + /* 000004D4 add [bx+si],al */ 0x00, 0x00,=0D + /* 000004D6 add [bx+si],al */ 0x00, 0x00,=0D + /* 000004D8 add [bx+si],al */ 0x00, 0x00,=0D + /* 000004DA add [bx+si],al */ 0x00, 0x00,=0D + /* 000004DC add [bx+si],al */ 0x00, 0x00,=0D + /* 000004DE add [bx+si],al */ 0x00, 0x00,=0D + /* 000004E0 add [bx+si],al */ 0x00, 0x00,=0D + /* 000004E2 add [bx+si],al */ 0x00, 0x00,=0D + /* 000004E4 add [bx+si],al */ 0x00, 0x00,=0D + /* 000004E6 add [bx+si],al */ 0x00, 0x00,=0D + /* 000004E8 add [bx+si],al */ 0x00, 0x00,=0D + /* 000004EA add [bx+si],al */ 0x00, 0x00,=0D + /* 000004EC add [bx+si],al */ 0x00, 0x00,=0D + /* 000004EE add [bx+si],al */ 0x00, 0x00,=0D + /* 000004F0 add [bx+si],al */ 0x00, 0x00,=0D + /* 000004F2 add [bx+si],al */ 0x00, 0x00,=0D + /* 000004F4 add [bx+si],al */ 0x00, 0x00,=0D + /* 000004F6 add [bx+si],al */ 0x00, 0x00,=0D + /* 000004F8 add [bx+si],al */ 0x00, 0x00,=0D + /* 000004FA add [bx+si],al */ 0x00, 0x00,=0D + /* 000004FC add [bx+si],al */ 0x00, 0x00,=0D + /* 000004FE add [bx+si],al */ 0x00, 0x00,=0D + /* 00000500 add [bx+si],al */ 0x00, 0x00,=0D + /* 00000502 add [bx+si],al */ 0x00, 0x00,=0D + /* 00000504 add [bx+si],al */ 0x00, 0x00,=0D + /* 00000506 add [bx+si],al */ 0x00, 0x00,=0D + /* 00000508 add [bx+si],al */ 0x00, 0x00,=0D + /* 0000050A add [bx+si],al */ 0x00, 0x00,=0D + /* 0000050C add [bx+si],al */ 0x00, 0x00,=0D + /* 0000050E add [bx+si],al */ 0x00, 0x00,=0D + /* 00000510 add [bx+si],al */ 0x00, 0x00,=0D + /* 00000512 add [bx+si],al */ 0x00, 0x00,=0D + /* 00000514 add [bx+si],al */ 0x00, 0x00,=0D + /* 00000516 add [bx+si],al */ 0x00, 0x00,=0D + /* 00000518 add [bx+si],al */ 0x00, 0x00,=0D + /* 0000051A add [bx+si],al */ 0x00, 0x00,=0D + /* 0000051C add [bx+si],al */ 0x00, 0x00,=0D + /* 0000051E add [bx+si],al */ 0x00, 0x00,=0D + /* 00000520 add [bx+si],al */ 0x00, 0x00,=0D + /* 00000522 add [bx+si],al */ 0x00, 0x00,=0D + /* 00000524 add [bx+si],al */ 0x00, 0x00,=0D + /* 00000526 add [bx+si],al */ 0x00, 0x00,=0D + /* 00000528 add [bx+si],al */ 0x00, 0x00,=0D + /* 0000052A add [bx+si],al */ 0x00, 0x00,=0D + /* 0000052C add [bx+si],al */ 0x00, 0x00,=0D + /* 0000052E add [bx+si],al */ 0x00, 0x00,=0D + /* 00000530 add [bx+si],al */ 0x00, 0x00,=0D + /* 00000532 add [bx+si],al */ 0x00, 0x00,=0D +};=0D +#endif=0D diff --git a/OvmfPkg/Bhyve/BhyveRfbDxe/VbeShim.sh b/OvmfPkg/Bhyve/BhyveRfbD= xe/VbeShim.sh new file mode 100644 index 0000000000..358b568338 --- /dev/null +++ b/OvmfPkg/Bhyve/BhyveRfbDxe/VbeShim.sh @@ -0,0 +1,80 @@ +#!/bin/sh=0D +###=0D +# @file=0D +# Shell script to assemble and dump the fake Int10h handler from NASM sour= ce to=0D +# a C array.=0D +#=0D +# Copyright (C) 2020, Rebecca Cran <rebecca@...>=0D +# Copyright (C) 2014, Red Hat, Inc.=0D +# Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved.<BR>=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +###=0D +=0D +set -e -u=0D +=0D +STEM=3D$(dirname -- "$0")/$(basename -- "$0" .sh)=0D +=0D +#=0D +# Install exit handler -- remove temporary files.=0D +#=0D +exit_handler()=0D +{=0D + rm -f -- "$STEM".bin "$STEM".disasm "$STEM".offsets "$STEM".insns \=0D + "$STEM".bytes=0D +}=0D +trap exit_handler EXIT=0D +=0D +#=0D +# Assemble the source file.=0D +#=0D +nasm -o "$STEM".bin -- "$STEM".asm=0D +=0D +#=0D +# Disassemble it, in order to get a binary dump associated with the source= .=0D +# (ndisasm doesn't recognize the "--" end-of-options delimiter.)=0D +#=0D +ndisasm "$STEM".bin >"$STEM".disasm=0D +=0D +#=0D +# Create three files, each with one column of the disassembly.=0D +#=0D +# The first column contains the offsets, and it starts the comment.=0D +#=0D +cut -c 1-8 -- "$STEM".disasm \=0D +| sed -e 's,^, /* ,' >"$STEM".offsets=0D +=0D +#=0D +# The second column contains the assembly-language instructions, and it cl= oses=0D +# the comment. We first pad it to 30 characters.=0D +#=0D +cut -c 29- -- "$STEM".disasm \=0D +| sed -e 's,$, ,' \=0D + -e 's,^\(.\{30\}\).*$,\1 */,' >"$STEM".insns=0D +=0D +#=0D +# The third column contains the bytes corresponding to the instruction,=0D +# represented as C integer constants. First strip trailing whitespace from= the=0D +# middle column of the input disassembly, then process pairs of nibbles.=0D +#=0D +cut -c 11-28 -- "$STEM".disasm \=0D +| sed -e 's, \+$,,' -e 's/\(..\)/ 0x\1,/g' | sed 's/0x ,//g' >"$STEM".byt= es=0D +=0D +#=0D +# Write the output file, recombining the columns. The output should have C= RLF=0D +# line endings.=0D +#=0D +{=0D + printf '//\n'=0D + printf '// THIS FILE WAS GENERATED BY "%s". DO NOT EDIT.\n' \=0D + "$(basename -- "$0")"=0D + printf '//\n'=0D + printf '#ifndef _VBE_SHIM_H_\n'=0D + printf '#define _VBE_SHIM_H_\n'=0D + printf 'STATIC CONST UINT8 mVbeShim[] =3D {\n'=0D + paste -d ' ' -- "$STEM".offsets "$STEM".insns "$STEM".bytes=0D + printf '};\n'=0D + printf '#endif\n'=0D +} \=0D +| unix2dos >"$STEM".h=0D diff --git a/OvmfPkg/Bhyve/FvmainCompactScratchEnd.fdf.inc b/OvmfPkg/Bhyve/= FvmainCompactScratchEnd.fdf.inc new file mode 100644 index 0000000000..46f5258329 --- /dev/null +++ b/OvmfPkg/Bhyve/FvmainCompactScratchEnd.fdf.inc @@ -0,0 +1,65 @@ +## @file=0D +# This FDF include file computes the end of the scratch buffer used in=0D +# DecompressMemFvs() [OvmfPkg/Sec/SecMain.c]. It is based on the decompre= ssed=0D +# (ie. original) size of the LZMA-compressed section of the one FFS file = in=0D +# the FVMAIN_COMPACT firmware volume.=0D +#=0D +# Copyright (C) 2015, Red Hat, Inc.=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +##=0D +=0D +# The GUID EE4E5898-3914-4259-9D6E-DC7BD79403CF means "LzmaCustomDecompres= s".=0D +# The decompressed output will have the following structure (see the file= =0D +# "9E21FD93-9C72-4c15-8C4B-E77F1DB2D792SEC1.guided.dummy" in the=0D +# Build/Ovmf*/*/FV/Ffs/9E21FD93-9C72-4c15-8C4B-E77F1DB2D792/ directory):=0D +#=0D +# Size Contents=0D +# ------------------- ---------------------------------------------------= -----=0D +# 4 EFI_COMMON_SECTION_HEADER, stating size 124 (0x7C) = and=0D +# type 0x19 (EFI_SECTION_RAW). The purpose of this se= ction=0D +# is to pad the start of PEIFV to 128 bytes.=0D +# 120 Zero bytes (padding).=0D +#=0D +# 4 EFI_COMMON_SECTION_HEADER, stating size=0D +# (PcdOvmfPeiMemFvSize + 4), and type 0x17=0D +# (EFI_SECTION_FIRMWARE_VOLUME_IMAGE).=0D +# PcdOvmfPeiMemFvSize PEIFV. Note that the above sizes pad the offset of = this=0D +# object to 128 bytes. See also the "guided.dummy.txt= "=0D +# file in the same directory.=0D +#=0D +# 4 EFI_COMMON_SECTION_HEADER, stating size 12 (0xC) an= d=0D +# type 0x19 (EFI_SECTION_RAW). The purpose of this se= ction=0D +# is to pad the start of DXEFV to 16 bytes.=0D +# 8 Zero bytes (padding).=0D +#=0D +# 4 EFI_COMMON_SECTION_HEADER, stating size=0D +# (PcdOvmfDxeMemFvSize + 4), and type 0x17=0D +# (EFI_SECTION_FIRMWARE_VOLUME_IMAGE).=0D +# PcdOvmfDxeMemFvSize DXEFV. Note that the above sizes pad the offset of = this=0D +# object to 16 bytes. See also the "guided.dummy.txt"= file=0D +# in the same directory.=0D +#=0D +# The total size after decompression is (128 + PcdOvmfPeiMemFvSize + 16 += =0D +# PcdOvmfDxeMemFvSize).=0D +=0D +DEFINE OUTPUT_SIZE =3D (128 + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfPeiMemFvSi= ze + 16 + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvSize)=0D +=0D +# LzmaCustomDecompressLib uses a constant scratch buffer size of 64KB; see= =0D +# SCRATCH_BUFFER_REQUEST_SIZE in=0D +# "MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaDecompress.c".=0D +=0D +DEFINE DECOMP_SCRATCH_SIZE =3D 0x00010000=0D +=0D +# Note: when we use PcdOvmfDxeMemFvBase in this context, BaseTools have no= t yet=0D +# offset it with MEMFD's base address. For that reason we have to do it ma= nually.=0D +#=0D +# The calculation below mirrors DecompressMemFvs() [OvmfPkg/Sec/SecMain.c]= .=0D +=0D +DEFINE OUTPUT_BASE =3D ($(MEMFD_BASE_ADDRESS) + gUefiOvm= fPkgTokenSpaceGuid.PcdOvmfDxeMemFvBase + 0x00100000)=0D +DEFINE DECOMP_SCRATCH_BASE_UNALIGNED =3D ($(OUTPUT_BASE) + $(OUTPUT_SIZE))= =0D +DEFINE DECOMP_SCRATCH_BASE_ALIGNMENT =3D 0x000FFFFF=0D +DEFINE DECOMP_SCRATCH_BASE_MASK =3D 0xFFF00000=0D +DEFINE DECOMP_SCRATCH_BASE =3D (($(DECOMP_SCRATCH_BASE_UNALIGNED= ) + $(DECOMP_SCRATCH_BASE_ALIGNMENT)) & $(DECOMP_SCRATCH_BASE_MASK))=0D +=0D +SET gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDecompressionScratchEnd =3D $(DECOMP= _SCRATCH_BASE) + $(DECOMP_SCRATCH_SIZE)=0D diff --git a/OvmfPkg/Bhyve/Include/Library/BhyveFwCtlLib.h b/OvmfPkg/Bhyve/= Include/Library/BhyveFwCtlLib.h new file mode 100644 index 0000000000..13028ec4b5 --- /dev/null +++ b/OvmfPkg/Bhyve/Include/Library/BhyveFwCtlLib.h @@ -0,0 +1,47 @@ +/** @file=0D + bhyve firmware configuration access=0D +=0D + Copyright (c) 2020, Rebecca Cran <rebecca@...>=0D + Copyright (c) 2015 Nahanni Systems=0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#ifndef __BHYVE_FW_CTL_LIB__=0D +#define __BHYVE_FW_CTL_LIB__=0D +=0D +/**=0D + Sysctl-like interface to read host information via a dot-separated=0D + ASCII OID.=0D +=0D + The information is copied into the buffer specified by Item. The=0D + size of the buffer is given by the location specified by Size=0D + before the call, and that location gives the amount of data copied=0D + after a successfull call, and after a call that returns a truncated=0D + value with an error return of RETURN_BUFFER_TOO_SMALL.=0D +=0D + The size of the available data can be determined by passing a NULL=0D + argument for Item. The size will be returned in the location pointed=0D + to by Size.=0D +=0D + @param[] Name - ASCII OID name=0D + @param[] Data - return buffer pointer=0D + @param[] Size - pointer to length=0D +=0D + @return RETURN_SUCCESS Valid data/len returned.=0D + RETURN_UNSUPPORTED f/w interface not present.=0D + RETURN_NOT_FOUND OID not found.=0D + RETURN_BUFFER_TOO_SMALL Return message truncated.=0D + RETURN_INVALID_PARAMETER Buffer too large=0D + RETURN_PROTOCOL_ERROR Unknown error from host=0D + **/=0D +RETURN_STATUS=0D +EFIAPI=0D +BhyveFwCtlGet (=0D + IN CONST CHAR8 *Name,=0D + OUT VOID *Item,=0D + IN OUT UINTN *Size=0D + );=0D +=0D +#endif=0D diff --git a/OvmfPkg/Bhyve/Library/BhyveFwCtlLib/BhyveFwCtlLib.c b/OvmfPkg/= Bhyve/Library/BhyveFwCtlLib/BhyveFwCtlLib.c new file mode 100644 index 0000000000..2c45ad70ca --- /dev/null +++ b/OvmfPkg/Bhyve/Library/BhyveFwCtlLib/BhyveFwCtlLib.c @@ -0,0 +1,426 @@ +/** @file=0D +=0D + Copyright (c) 2020, Rebecca Cran <rebecca@...>=0D + Copyright (c) 2011 - 2013, Intel Corporation. All rights reserved.<BR>=0D + Copyright (C) 2013, Red Hat, Inc.=0D + Copyright (c) 2015, Nahanni Systems.=0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include "Uefi.h"=0D +#include <Library/BaseLib.h>=0D +#include <Library/BaseMemoryLib.h>=0D +#include <Library/DebugLib.h>=0D +#include <Library/IoLib.h>=0D +#include <Library/BhyveFwCtlLib.h>=0D +#include <Library/MemoryAllocationLib.h>=0D +#include <Library/UefiBootServicesTableLib.h>=0D +=0D +#define FW_PORT 0x510=0D +#define FW_IPORT 0x511=0D +=0D +/* Transport protocol basic operations */=0D +#define OP_NULL 1=0D +#define OP_ECHO 2=0D +#define OP_GET 3=0D +#define OP_GET_LEN 4=0D +#define OP_SET 5=0D +=0D +/* Transport protocol error returns */=0D +#define T_ESUCCESS 0=0D +#define T_ENOENT 2=0D +#define T_E2BIG 7=0D +#define T_EMSGSIZE 40=0D +=0D +#define ROUNDUP(x, y) ((((x)+((y)-1))/(y))*(y))=0D +=0D +STATIC CONST CHAR8 mBhyveSig[4] =3D { 'B', 'H', 'Y', 'V' };=0D +=0D +STATIC BOOLEAN mBhyveFwCtlSupported =3D FALSE;=0D +=0D +STATIC INTN mBhyveFwCtlTxid =3D 0xa5;=0D +=0D +/* XXX Maybe a better inbuilt version of this ? */=0D +struct BIoVec {=0D + VOID *Base;=0D + UINTN Len;=0D +};=0D +=0D +struct MsgRxHdr {=0D + UINT32 Sz;=0D + UINT32 Op;=0D + UINT32 TxId;=0D + UINT32 Err;=0D +};=0D +=0D +STATIC=0D +RETURN_STATUS=0D +EFIAPI=0D +BhyveFwCtl_CvtErr (=0D + IN UINT32 errno=0D + )=0D +{=0D + RETURN_STATUS Status;=0D +=0D + switch (errno) {=0D + case T_ESUCCESS:=0D + Status =3D RETURN_SUCCESS;=0D + break;=0D + case T_ENOENT:=0D + Status =3D RETURN_NOT_FOUND;=0D + break;=0D + case T_E2BIG:=0D + Status =3D RETURN_INVALID_PARAMETER;=0D + break;=0D + case T_EMSGSIZE:=0D + Status =3D RETURN_BUFFER_TOO_SMALL;=0D + break;=0D + default:=0D + Status =3D RETURN_PROTOCOL_ERROR;=0D + break;=0D + }=0D +=0D + return Status;=0D +}=0D +=0D +STATIC=0D +UINTN=0D +EFIAPI=0D +BIov_WLen (=0D + IN struct BIoVec b[]=0D + )=0D +{=0D + UINTN i;=0D + UINTN tLen;=0D +=0D + tLen =3D 0;=0D +=0D + if (b !=3D NULL) {=0D + for (i =3D 0; b[i].Base !=3D NULL; i++)=0D + tLen +=3D ROUNDUP (b[i].Len, sizeof(UINT32));=0D + }=0D +=0D + return tLen;=0D +}=0D +=0D +/**=0D + Utility to send 1-3 bhyes of input as a 4-byte value=0D + with trailing zeroes.=0D + **/=0D +STATIC=0D +UINT32=0D +BIov_Send_Rem (=0D + IN UINT32 *Data,=0D + IN UINTN Len=0D + )=0D +{=0D + union {=0D + UINT8 c[4];=0D + UINT32 w;=0D + } u;=0D + UINT8 *cdata;=0D + UINTN i;=0D +=0D + cdata =3D (UINT8 *)Data;=0D + u.w =3D 0;=0D +=0D + for (i =3D 0; i < Len; i++)=0D + u.c[i] =3D *cdata++;=0D +=0D + return u.w;=0D +}=0D +=0D +/**=0D + Send a block of data out the i/o port as 4-byte quantities,=0D + appending trailing zeroes on the last if required.=0D + **/=0D +STATIC=0D +VOID=0D +BIov_Send (=0D + IN char *Data,=0D + IN UINTN Len=0D + )=0D +{=0D + UINT32 *LData;=0D +=0D + LData =3D (UINT32 *)Data;=0D +=0D + while (Len > sizeof(UINT32)) {=0D + IoWrite32 (FW_PORT, *LData++);=0D + Len -=3D sizeof(UINT32);=0D + }=0D +=0D + if (Len > 0) {=0D + IoWrite32 (FW_PORT, BIov_Send_Rem (LData, Len));=0D + }=0D +}=0D +=0D +/**=0D + Send data described by an array of iovecs out the i/o port.=0D + **/=0D +STATIC=0D +VOID=0D +BIov_SendAll (=0D + IN struct BIoVec b[]=0D + )=0D +{=0D + INTN i;=0D +=0D + if (b !=3D NULL) {=0D + for (i =3D 0; b[i].Base; i++) {=0D + BIov_Send (b[i].Base, b[i].Len);=0D + }=0D + }=0D +}=0D +=0D +/**=0D + Prepend the transport header to a block of data and send.=0D + **/=0D +STATIC=0D +VOID=0D +EFIAPI=0D +BhyveFwCtl_MsgSend(=0D + IN UINTN OpCode,=0D + IN struct BIoVec Data[]=0D + )=0D +{=0D + struct BIoVec hIov[4];=0D + UINT32 Hdr[3];=0D + UINTN i;=0D +=0D + /* Set up header as an iovec */=0D + for (i =3D 0; i < 3; i++) {=0D + hIov[i].Base =3D &Hdr[i];=0D + hIov[i].Len =3D sizeof(Hdr[0]);=0D + }=0D + hIov[i].Base =3D NULL;=0D + hIov[i].Len =3D 0;=0D +=0D + /* Initialize header */=0D + Hdr[0] =3D BIov_WLen (hIov) + BIov_WLen (Data);=0D + Hdr[1] =3D OpCode;=0D + Hdr[2] =3D mBhyveFwCtlTxid;=0D +=0D + /* Send header and data */=0D + BIov_SendAll (hIov);=0D + BIov_SendAll (Data);=0D +}=0D +=0D +/**=0D + Read a transport response and optional data from the i/o port.=0D + **/=0D +STATIC=0D +RETURN_STATUS=0D +EFIAPI=0D +BhyveFwCtl_MsgRecv(=0D + OUT struct MsgRxHdr *Rhdr,=0D + OUT struct BIoVec Data[]=0D + )=0D +{=0D + RETURN_STATUS Status;=0D + UINT32 *Dp;=0D + UINT32 Rd;=0D + UINTN remLen;=0D + INTN oLen, xLen;=0D +=0D + Rd =3D IoRead32 (FW_PORT);=0D + if (Rd < sizeof(struct MsgRxHdr)) {=0D + ;=0D + }=0D +=0D + /* Read in header and setup initial error */=0D + Rhdr->Sz =3D Rd;=0D + Rhdr->Op =3D IoRead32 (FW_PORT);=0D + Rhdr->TxId =3D IoRead32 (FW_PORT);=0D + Rhdr->Err =3D IoRead32 (FW_PORT);=0D +=0D + /* Convert transport errno into UEFI error status */=0D + Status =3D BhyveFwCtl_CvtErr(Rhdr->Err);=0D +=0D + remLen =3D Rd - sizeof(struct MsgRxHdr);=0D + xLen =3D 0;=0D +=0D + /*=0D + * A few cases to handle:=0D + * - the user didn't supply a read buffer=0D + * - the buffer is too small for the response=0D + * - the response is zero-length=0D + */=0D + if (Data !=3D NULL) {=0D + Dp =3D (UINT32 *)Data[0].Base;=0D + oLen =3D remLen;=0D + if (remLen > Data[0].Len) {=0D + Status =3D RETURN_BUFFER_TOO_SMALL;=0D + xLen =3D remLen - Data[0].Len;=0D + oLen =3D remLen =3D Data[0].Len;=0D + }=0D + while (remLen > 0) {=0D + *Dp++ =3D IoRead32 (FW_PORT);=0D + remLen -=3D sizeof(UINT32);=0D + }=0D + Data[0].Len =3D oLen;=0D + } else {=0D + /* No user data, but data returned - drop */=0D + if (remLen > 0) {=0D + Status =3D RETURN_BUFFER_TOO_SMALL;=0D + xLen =3D remLen;=0D + }=0D + }=0D +=0D + /* Drop additional data */=0D + while (xLen > 0) {=0D + (void) IoRead32 (FW_PORT);=0D + xLen -=3D sizeof(UINT32);=0D + }=0D +=0D + return Status;=0D +}=0D +=0D +=0D +STATIC=0D +RETURN_STATUS=0D +EFIAPI=0D +BhyveFwCtl_Msg(=0D + IN UINTN OpCode,=0D + IN struct BIoVec Sdata[],=0D + OUT struct BIoVec Rdata[]=0D + )=0D +{=0D + struct MsgRxHdr Rh;=0D + RETURN_STATUS Status;=0D +=0D + Status =3D RETURN_SUCCESS;=0D +=0D + BhyveFwCtl_MsgSend (OpCode, Sdata);=0D + Status =3D BhyveFwCtl_MsgRecv (&Rh, Rdata);=0D +=0D + mBhyveFwCtlTxid++;=0D +=0D + return Status;=0D +}=0D +=0D +STATIC=0D +RETURN_STATUS=0D +EFIAPI=0D +BhyveFwCtlGetLen (=0D + IN CONST CHAR8 *Name,=0D + IN OUT UINTN *Size=0D + )=0D +{=0D + struct BIoVec Req[2], Resp[2];=0D + RETURN_STATUS Status;=0D +=0D + Req[0].Base =3D (VOID *)Name;=0D + Req[0].Len =3D AsciiStrLen (Name) + 1;=0D + Req[1].Base =3D NULL;=0D +=0D + Resp[0].Base =3D Size;=0D + Resp[0].Len =3D sizeof(UINTN);=0D + Resp[1].Base =3D NULL;=0D +=0D + Status =3D BhyveFwCtl_Msg (OP_GET_LEN, Req, Resp);=0D +=0D + return Status;=0D +}=0D +=0D +#define FMAXSZ 1024=0D +STATIC struct {=0D + UINT64 fSize;=0D + UINT32 fData[FMAXSZ];=0D +} FwGetvalBuf;=0D +=0D +STATIC=0D +RETURN_STATUS=0D +EFIAPI=0D +BhyveFwCtlGetVal (=0D + IN CONST CHAR8 *Name,=0D + OUT VOID *Item,=0D + IN OUT UINTN *Size=0D + )=0D +{=0D + struct BIoVec Req[2], Resp[2];=0D + RETURN_STATUS Status;=0D +=0D + /* Make sure temp buffer is larger than passed-in size */=0D + if (*Size > sizeof(FwGetvalBuf.fData))=0D + return RETURN_INVALID_PARAMETER;=0D +=0D + Req[0].Base =3D (VOID *)Name;=0D + Req[0].Len =3D AsciiStrLen(Name) + 1;=0D + Req[1].Base =3D NULL;=0D +=0D + Resp[0].Base =3D &FwGetvalBuf;=0D + Resp[0].Len =3D sizeof(UINT64) + *Size;=0D + Resp[1].Base =3D NULL;=0D +=0D + Status =3D BhyveFwCtl_Msg (OP_GET, Req, Resp);=0D +=0D + /*=0D + * Copy out data on success (or on a truncated message).=0D + * XXX This step can be eliminted with Msg() supporting=0D + * multiple iovecs.=0D + */=0D + if ((Status =3D=3D RETURN_SUCCESS) || (Status =3D=3D RETURN_BUFFER_TOO_S= MALL)) {=0D + *Size =3D FwGetvalBuf.fSize;=0D + CopyMem (Item, FwGetvalBuf.fData, *Size);=0D + }=0D +=0D + return Status;=0D +}=0D +=0D +/**=0D + Front end to the internal GET_LEN and GET protocols=0D + **/=0D +RETURN_STATUS=0D +EFIAPI=0D +BhyveFwCtlGet (=0D + IN CONST CHAR8 *Name,=0D + OUT VOID *Item,=0D + IN OUT UINTN *Size=0D + )=0D +{=0D + RETURN_STATUS Status;=0D +=0D + if (mBhyveFwCtlSupported =3D=3D FALSE)=0D + return RETURN_UNSUPPORTED;=0D +=0D + if (Item =3D=3D NULL) {=0D + Status =3D BhyveFwCtlGetLen (Name, Size);=0D + } else {=0D + Status =3D BhyveFwCtlGetVal (Name, Item, Size);=0D + }=0D +=0D + return Status;=0D +}=0D +=0D +=0D +/**=0D + Library initialization. Probe the host to see if the f/w ctl=0D + interface is supported.=0D + **/=0D +RETURN_STATUS=0D +EFIAPI=0D +BhyveFwCtlInitialize (=0D + VOID=0D + )=0D +{=0D + UINTN i;=0D + UINT8 ch;=0D +=0D + DEBUG ((DEBUG_INFO, "FwCtlInitialize\n"));=0D +=0D + IoWrite16 (FW_PORT, 0x0000);=0D + for (i =3D 0; i < 4; i++) {=0D + ch =3D IoRead8 (FW_IPORT);=0D + if (ch !=3D mBhyveSig[i]) {=0D + DEBUG ((DEBUG_INFO, "Host f/w sig mismatch %c/%c\n", ch, mBhyveSig[i= ]));=0D + return RETURN_SUCCESS;=0D + }=0D + }=0D +=0D + mBhyveFwCtlSupported =3D TRUE;=0D +=0D + return RETURN_SUCCESS;=0D +}=0D diff --git a/OvmfPkg/Bhyve/Library/BhyveFwCtlLib/BhyveFwCtlLib.inf b/OvmfPk= g/Bhyve/Library/BhyveFwCtlLib/BhyveFwCtlLib.inf new file mode 100644 index 0000000000..e9819f4f96 --- /dev/null +++ b/OvmfPkg/Bhyve/Library/BhyveFwCtlLib/BhyveFwCtlLib.inf @@ -0,0 +1,41 @@ +## @file=0D +#=0D +# Copyright (C) 2020, Rebecca Cran <rebecca@...>=0D +# Copyright (C) 2015 Nahanni Systems=0D +# Copyright (c) 2008 - 2012, Intel Corporation. All rights reserved.<BR>= =0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010005=0D + BASE_NAME =3D BhyveFwCtlLib=0D + FILE_GUID =3D fd982666-67f9-11e5-a42a-0025908602f6= =0D + MODULE_TYPE =3D BASE=0D + VERSION_STRING =3D 1.0=0D + LIBRARY_CLASS =3D BhyveFwCtlLib|PEIM DXE_DRIVER DXE_RUN= TIME_DRIVER=0D +=0D + CONSTRUCTOR =3D BhyveFwCtlInitialize=0D +=0D +#=0D +# The following information is for reference only and not required by the = build tools.=0D +#=0D +# VALID_ARCHITECTURES =3D X64=0D +#=0D +=0D +[Sources]=0D + BhyveFwCtlLib.c=0D +=0D +[Packages]=0D + MdePkg/MdePkg.dec=0D + OvmfPkg/Bhyve/BhyvePkg.dec=0D +=0D +[LibraryClasses]=0D + BaseLib=0D + BaseMemoryLib=0D + DebugLib=0D + IoLib=0D + MemoryAllocationLib=0D + IntrinsicLib=0D +=0D diff --git a/OvmfPkg/Bhyve/Library/PlatformBootManagerLib/BdsPlatform.c b/O= vmfPkg/Bhyve/Library/PlatformBootManagerLib/BdsPlatform.c new file mode 100644 index 0000000000..3b94630ac7 --- /dev/null +++ b/OvmfPkg/Bhyve/Library/PlatformBootManagerLib/BdsPlatform.c @@ -0,0 +1,1660 @@ +/** @file=0D + Platform BDS customizations.=0D +=0D + Copyright (c) 2020, Rebecca Cran <rebecca@...>=0D + Copyright (c) 2004 - 2019, Intel Corporation. All rights reserved.<BR>=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include "BdsPlatform.h"=0D +#include <Guid/RootBridgesConnectedEventGroup.h>=0D +#include <Protocol/FirmwareVolume2.h>=0D +#include <Library/PlatformBmPrintScLib.h>=0D +#include <Library/Tcg2PhysicalPresenceLib.h>=0D +=0D +#include <Protocol/BlockIo.h>=0D +=0D +//=0D +// Global data=0D +//=0D +=0D +VOID *mEfiDevPathNotifyReg;=0D +EFI_EVENT mEfiDevPathEvent;=0D +VOID *mEmuVariableEventReg;=0D +EFI_EVENT mEmuVariableEvent;=0D +UINT16 mHostBridgeDevId;=0D +=0D +//=0D +// Table of host IRQs matching PCI IRQs A-D=0D +// (for configuring PCI Interrupt Line register)=0D +//=0D +CONST UINT8 PciHostIrqs[] =3D {=0D + 0x0a, 0x0a, 0x0b, 0x0b=0D +};=0D +=0D +//=0D +// Type definitions=0D +//=0D +=0D +typedef=0D +EFI_STATUS=0D +(EFIAPI *PROTOCOL_INSTANCE_CALLBACK)(=0D + IN EFI_HANDLE Handle,=0D + IN VOID *Instance,=0D + IN VOID *Context=0D + );=0D +=0D +/**=0D + @param[in] Handle - Handle of PCI device instance=0D + @param[in] PciIo - PCI IO protocol instance=0D + @param[in] Pci - PCI Header register block=0D +**/=0D +typedef=0D +EFI_STATUS=0D +(EFIAPI *VISIT_PCI_INSTANCE_CALLBACK)(=0D + IN EFI_HANDLE Handle,=0D + IN EFI_PCI_IO_PROTOCOL *PciIo,=0D + IN PCI_TYPE00 *Pci=0D + );=0D +=0D +=0D +//=0D +// Function prototypes=0D +//=0D +=0D +EFI_STATUS=0D +VisitAllInstancesOfProtocol (=0D + IN EFI_GUID *Id,=0D + IN PROTOCOL_INSTANCE_CALLBACK CallBackFunction,=0D + IN VOID *Context=0D + );=0D +=0D +EFI_STATUS=0D +VisitAllPciInstancesOfProtocol (=0D + IN VISIT_PCI_INSTANCE_CALLBACK CallBackFunction=0D + );=0D +=0D +VOID=0D +InstallDevicePathCallback (=0D + VOID=0D + );=0D +=0D +VOID=0D +PlatformRegisterFvBootOption (=0D + EFI_GUID *FileGuid,=0D + CHAR16 *Description,=0D + UINT32 Attributes=0D + )=0D +{=0D + EFI_STATUS Status;=0D + INTN OptionIndex;=0D + EFI_BOOT_MANAGER_LOAD_OPTION NewOption;=0D + EFI_BOOT_MANAGER_LOAD_OPTION *BootOptions;=0D + UINTN BootOptionCount;=0D + MEDIA_FW_VOL_FILEPATH_DEVICE_PATH FileNode;=0D + EFI_LOADED_IMAGE_PROTOCOL *LoadedImage;=0D + EFI_DEVICE_PATH_PROTOCOL *DevicePath;=0D +=0D + Status =3D gBS->HandleProtocol (=0D + gImageHandle,=0D + &gEfiLoadedImageProtocolGuid,=0D + (VOID **) &LoadedImage=0D + );=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + EfiInitializeFwVolDevicepathNode (&FileNode, FileGuid);=0D + DevicePath =3D DevicePathFromHandle (LoadedImage->DeviceHandle);=0D + ASSERT (DevicePath !=3D NULL);=0D + DevicePath =3D AppendDevicePathNode (=0D + DevicePath,=0D + (EFI_DEVICE_PATH_PROTOCOL *) &FileNode=0D + );=0D + ASSERT (DevicePath !=3D NULL);=0D +=0D + Status =3D EfiBootManagerInitializeLoadOption (=0D + &NewOption,=0D + LoadOptionNumberUnassigned,=0D + LoadOptionTypeBoot,=0D + Attributes,=0D + Description,=0D + DevicePath,=0D + NULL,=0D + 0=0D + );=0D + ASSERT_EFI_ERROR (Status);=0D + FreePool (DevicePath);=0D +=0D + BootOptions =3D EfiBootManagerGetLoadOptions (=0D + &BootOptionCount, LoadOptionTypeBoot=0D + );=0D +=0D + OptionIndex =3D EfiBootManagerFindLoadOption (=0D + &NewOption, BootOptions, BootOptionCount=0D + );=0D +=0D + if (OptionIndex =3D=3D -1) {=0D + Status =3D EfiBootManagerAddLoadOptionVariable (&NewOption, MAX_UINTN)= ;=0D + ASSERT_EFI_ERROR (Status);=0D + }=0D + EfiBootManagerFreeLoadOption (&NewOption);=0D + EfiBootManagerFreeLoadOptions (BootOptions, BootOptionCount);=0D +}=0D +=0D +/**=0D + Remove all MemoryMapped(...)/FvFile(...) and Fv(...)/FvFile(...) boot op= tions=0D + whose device paths do not resolve exactly to an FvFile in the system.=0D +=0D + This removes any boot options that point to binaries built into the firm= ware=0D + and have become stale due to any of the following:=0D + - DXEFV's base address or size changed (historical),=0D + - DXEFV's FvNameGuid changed,=0D + - the FILE_GUID of the pointed-to binary changed,=0D + - the referenced binary is no longer built into the firmware.=0D +=0D + EfiBootManagerFindLoadOption() used in PlatformRegisterFvBootOption() on= ly=0D + avoids exact duplicates.=0D +**/=0D +VOID=0D +RemoveStaleFvFileOptions (=0D + VOID=0D + )=0D +{=0D + EFI_BOOT_MANAGER_LOAD_OPTION *BootOptions;=0D + UINTN BootOptionCount;=0D + UINTN Index;=0D +=0D + BootOptions =3D EfiBootManagerGetLoadOptions (&BootOptionCount,=0D + LoadOptionTypeBoot);=0D +=0D + for (Index =3D 0; Index < BootOptionCount; ++Index) {=0D + EFI_DEVICE_PATH_PROTOCOL *Node1, *Node2, *SearchNode;=0D + EFI_STATUS Status;=0D + EFI_HANDLE FvHandle;=0D +=0D + //=0D + // If the device path starts with neither MemoryMapped(...) nor Fv(...= ),=0D + // then keep the boot option.=0D + //=0D + Node1 =3D BootOptions[Index].FilePath;=0D + if (!(DevicePathType (Node1) =3D=3D HARDWARE_DEVICE_PATH &&=0D + DevicePathSubType (Node1) =3D=3D HW_MEMMAP_DP) &&=0D + !(DevicePathType (Node1) =3D=3D MEDIA_DEVICE_PATH &&=0D + DevicePathSubType (Node1) =3D=3D MEDIA_PIWG_FW_VOL_DP)) {=0D + continue;=0D + }=0D +=0D + //=0D + // If the second device path node is not FvFile(...), then keep the bo= ot=0D + // option.=0D + //=0D + Node2 =3D NextDevicePathNode (Node1);=0D + if (DevicePathType (Node2) !=3D MEDIA_DEVICE_PATH ||=0D + DevicePathSubType (Node2) !=3D MEDIA_PIWG_FW_FILE_DP) {=0D + continue;=0D + }=0D +=0D + //=0D + // Locate the Firmware Volume2 protocol instance that is denoted by th= e=0D + // boot option. If this lookup fails (i.e., the boot option references= a=0D + // firmware volume that doesn't exist), then we'll proceed to delete t= he=0D + // boot option.=0D + //=0D + SearchNode =3D Node1;=0D + Status =3D gBS->LocateDevicePath (&gEfiFirmwareVolume2ProtocolGuid,=0D + &SearchNode, &FvHandle);=0D +=0D + if (!EFI_ERROR (Status)) {=0D + //=0D + // The firmware volume was found; now let's see if it contains the F= vFile=0D + // identified by GUID.=0D + //=0D + EFI_FIRMWARE_VOLUME2_PROTOCOL *FvProtocol;=0D + MEDIA_FW_VOL_FILEPATH_DEVICE_PATH *FvFileNode;=0D + UINTN BufferSize;=0D + EFI_FV_FILETYPE FoundType;=0D + EFI_FV_FILE_ATTRIBUTES FileAttributes;=0D + UINT32 AuthenticationStatus;=0D +=0D + Status =3D gBS->HandleProtocol (FvHandle, &gEfiFirmwareVolume2Protoc= olGuid,=0D + (VOID **)&FvProtocol);=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + FvFileNode =3D (MEDIA_FW_VOL_FILEPATH_DEVICE_PATH *)Node2;=0D + //=0D + // Buffer=3D=3DNULL means we request metadata only: BufferSize, Foun= dType,=0D + // FileAttributes.=0D + //=0D + Status =3D FvProtocol->ReadFile (=0D + FvProtocol,=0D + &FvFileNode->FvFileName, // NameGuid=0D + NULL, // Buffer=0D + &BufferSize,=0D + &FoundType,=0D + &FileAttributes,=0D + &AuthenticationStatus=0D + );=0D + if (!EFI_ERROR (Status)) {=0D + //=0D + // The FvFile was found. Keep the boot option.=0D + //=0D + continue;=0D + }=0D + }=0D +=0D + //=0D + // Delete the boot option.=0D + //=0D + Status =3D EfiBootManagerDeleteLoadOptionVariable (=0D + BootOptions[Index].OptionNumber, LoadOptionTypeBoot);=0D + DEBUG_CODE (=0D + CHAR16 *DevicePathString;=0D +=0D + DevicePathString =3D ConvertDevicePathToText(BootOptions[Index].File= Path,=0D + FALSE, FALSE);=0D + DEBUG ((=0D + EFI_ERROR (Status) ? EFI_D_WARN : DEBUG_VERBOSE,=0D + "%a: removing stale Boot#%04x %s: %r\n",=0D + __FUNCTION__,=0D + (UINT32)BootOptions[Index].OptionNumber,=0D + DevicePathString =3D=3D NULL ? L"<unavailable>" : DevicePathString= ,=0D + Status=0D + ));=0D + if (DevicePathString !=3D NULL) {=0D + FreePool (DevicePathString);=0D + }=0D + );=0D + }=0D +=0D + EfiBootManagerFreeLoadOptions (BootOptions, BootOptionCount);=0D +}=0D +=0D +VOID=0D +PlatformRegisterOptionsAndKeys (=0D + VOID=0D + )=0D +{=0D + EFI_STATUS Status;=0D + EFI_INPUT_KEY Enter;=0D + EFI_INPUT_KEY F2;=0D + EFI_INPUT_KEY Esc;=0D + EFI_BOOT_MANAGER_LOAD_OPTION BootOption;=0D +=0D + //=0D + // Register ENTER as CONTINUE key=0D + //=0D + Enter.ScanCode =3D SCAN_NULL;=0D + Enter.UnicodeChar =3D CHAR_CARRIAGE_RETURN;=0D + Status =3D EfiBootManagerRegisterContinueKeyOption (0, &Enter, NULL);=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + //=0D + // Map F2 to Boot Manager Menu=0D + //=0D + F2.ScanCode =3D SCAN_F2;=0D + F2.UnicodeChar =3D CHAR_NULL;=0D + Esc.ScanCode =3D SCAN_ESC;=0D + Esc.UnicodeChar =3D CHAR_NULL;=0D + Status =3D EfiBootManagerGetBootManagerMenu (&BootOption);=0D + ASSERT_EFI_ERROR (Status);=0D + Status =3D EfiBootManagerAddKeyOptionVariable (=0D + NULL, (UINT16) BootOption.OptionNumber, 0, &F2, NULL=0D + );=0D + ASSERT (Status =3D=3D EFI_SUCCESS || Status =3D=3D EFI_ALREADY_STARTED);= =0D + Status =3D EfiBootManagerAddKeyOptionVariable (=0D + NULL, (UINT16) BootOption.OptionNumber, 0, &Esc, NULL=0D + );=0D + ASSERT (Status =3D=3D EFI_SUCCESS || Status =3D=3D EFI_ALREADY_STARTED);= =0D +}=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +ConnectRootBridge (=0D + IN EFI_HANDLE RootBridgeHandle,=0D + IN VOID *Instance,=0D + IN VOID *Context=0D + );=0D +=0D +STATIC=0D +EFI_STATUS=0D +EFIAPI=0D +ConnectVirtioPciRng (=0D + IN EFI_HANDLE Handle,=0D + IN VOID *Instance,=0D + IN VOID *Context=0D + );=0D +=0D +STATIC=0D +VOID=0D +SaveS3BootScript (=0D + VOID=0D + );=0D +=0D +//=0D +// BDS Platform Functions=0D +//=0D +/**=0D + Do the platform init, can be customized by OEM/IBV=0D +=0D + Possible things that can be done in PlatformBootManagerBeforeConsole:=0D +=0D + > Update console variable: 1. include hot-plug devices;=0D + > 2. Clear ConIn and add SOL for AMT=0D + > Register new Driver#### or Boot####=0D + > Register new Key####: e.g.: F12=0D + > Signal ReadyToLock event=0D + > Authentication action: 1. connect Auth devices;=0D + > 2. Identify auto logon user.=0D +**/=0D +VOID=0D +EFIAPI=0D +PlatformBootManagerBeforeConsole (=0D + VOID=0D + )=0D +{=0D + EFI_HANDLE Handle;=0D + EFI_STATUS Status;=0D +=0D + DEBUG ((DEBUG_INFO, "PlatformBootManagerBeforeConsole\n"));=0D + InstallDevicePathCallback ();=0D +=0D + VisitAllInstancesOfProtocol (&gEfiPciRootBridgeIoProtocolGuid,=0D + ConnectRootBridge, NULL);=0D +=0D + //=0D + // Signal the ACPI platform driver that it can download QEMU ACPI tables= .=0D + //=0D + EfiEventGroupSignal (&gRootBridgesConnectedEventGroupGuid);=0D +=0D + //=0D + // We can't signal End-of-Dxe earlier than this. Namely, End-of-Dxe trig= gers=0D + // the preparation of S3 system information. That logic has a hard depen= dency=0D + // on the presence of the FACS ACPI table. Since our ACPI tables are onl= y=0D + // installed after PCI enumeration completes, we must not trigger the S3= save=0D + // earlier, hence we can't signal End-of-Dxe earlier.=0D + //=0D + EfiEventGroupSignal (&gEfiEndOfDxeEventGroupGuid);=0D +=0D + //=0D + // Prevent further changes to LockBoxes or SMRAM.=0D + //=0D + Handle =3D NULL;=0D + Status =3D gBS->InstallProtocolInterface (&Handle,=0D + &gEfiDxeSmmReadyToLockProtocolGuid, EFI_NATIVE_INTERFACE= ,=0D + NULL);=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + //=0D + // Dispatch deferred images after EndOfDxe event and ReadyToLock=0D + // installation.=0D + //=0D + EfiBootManagerDispatchDeferredImages ();=0D +=0D + PlatformInitializeConsole (gPlatformConsole);=0D +=0D + PlatformRegisterOptionsAndKeys ();=0D +=0D + //=0D + // Install both VIRTIO_DEVICE_PROTOCOL and (dependent) EFI_RNG_PROTOCOL= =0D + // instances on Virtio PCI RNG devices.=0D + //=0D + VisitAllInstancesOfProtocol (&gEfiPciIoProtocolGuid, ConnectVirtioPciRng= ,=0D + NULL);=0D +}=0D +=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +ConnectRootBridge (=0D + IN EFI_HANDLE RootBridgeHandle,=0D + IN VOID *Instance,=0D + IN VOID *Context=0D + )=0D +{=0D + EFI_STATUS Status;=0D +=0D + //=0D + // Make the PCI bus driver connect the root bridge, non-recursively. Thi= s=0D + // will produce a number of child handles with PciIo on them.=0D + //=0D + Status =3D gBS->ConnectController (=0D + RootBridgeHandle, // ControllerHandle=0D + NULL, // DriverImageHandle=0D + NULL, // RemainingDevicePath -- produce all= =0D + // children=0D + FALSE // Recursive=0D + );=0D + return Status;=0D +}=0D +=0D +=0D +STATIC=0D +EFI_STATUS=0D +EFIAPI=0D +ConnectVirtioPciRng (=0D + IN EFI_HANDLE Handle,=0D + IN VOID *Instance,=0D + IN VOID *Context=0D + )=0D +{=0D + EFI_PCI_IO_PROTOCOL *PciIo;=0D + EFI_STATUS Status;=0D + UINT16 VendorId;=0D + UINT16 DeviceId;=0D + UINT8 RevisionId;=0D + BOOLEAN Virtio10;=0D + UINT16 SubsystemId;=0D +=0D + PciIo =3D Instance;=0D +=0D + //=0D + // Read and check VendorId.=0D + //=0D + Status =3D PciIo->Pci.Read (PciIo, EfiPciIoWidthUint16, PCI_VENDOR_ID_OF= FSET,=0D + 1, &VendorId);=0D + if (EFI_ERROR (Status)) {=0D + goto Error;=0D + }=0D + if (VendorId !=3D VIRTIO_VENDOR_ID) {=0D + return EFI_SUCCESS;=0D + }=0D +=0D + //=0D + // Read DeviceId and RevisionId.=0D + //=0D + Status =3D PciIo->Pci.Read (PciIo, EfiPciIoWidthUint16, PCI_DEVICE_ID_OF= FSET,=0D + 1, &DeviceId);=0D + if (EFI_ERROR (Status)) {=0D + goto Error;=0D + }=0D + Status =3D PciIo->Pci.Read (PciIo, EfiPciIoWidthUint8, PCI_REVISION_ID_O= FFSET,=0D + 1, &RevisionId);=0D + if (EFI_ERROR (Status)) {=0D + goto Error;=0D + }=0D +=0D + //=0D + // From DeviceId and RevisionId, determine whether the device is a=0D + // modern-only Virtio 1.0 device. In case of Virtio 1.0, DeviceId can=0D + // immediately be restricted to VIRTIO_SUBSYSTEM_ENTROPY_SOURCE, and=0D + // SubsystemId will only play a sanity-check role. Otherwise, DeviceId c= an=0D + // only be sanity-checked, and SubsystemId will decide.=0D + //=0D + if (DeviceId =3D=3D 0x1040 + VIRTIO_SUBSYSTEM_ENTROPY_SOURCE &&=0D + RevisionId >=3D 0x01) {=0D + Virtio10 =3D TRUE;=0D + } else if (DeviceId >=3D 0x1000 && DeviceId <=3D 0x103F && RevisionId = =3D=3D 0x00) {=0D + Virtio10 =3D FALSE;=0D + } else {=0D + return EFI_SUCCESS;=0D + }=0D +=0D + //=0D + // Read and check SubsystemId as dictated by Virtio10.=0D + //=0D + Status =3D PciIo->Pci.Read (PciIo, EfiPciIoWidthUint16,=0D + PCI_SUBSYSTEM_ID_OFFSET, 1, &SubsystemId);=0D + if (EFI_ERROR (Status)) {=0D + goto Error;=0D + }=0D + if ((Virtio10 && SubsystemId >=3D 0x40) ||=0D + (!Virtio10 && SubsystemId =3D=3D VIRTIO_SUBSYSTEM_ENTROPY_SOURCE)) {= =0D + Status =3D gBS->ConnectController (=0D + Handle, // ControllerHandle=0D + NULL, // DriverImageHandle -- connect all drivers=0D + NULL, // RemainingDevicePath -- produce all child ha= ndles=0D + FALSE // Recursive -- don't follow child handles=0D + );=0D + if (EFI_ERROR (Status)) {=0D + goto Error;=0D + }=0D + }=0D + return EFI_SUCCESS;=0D +=0D +Error:=0D + DEBUG ((DEBUG_ERROR, "%a: %r\n", __FUNCTION__, Status));=0D + return Status;=0D +}=0D +=0D +=0D +/**=0D + Add IsaKeyboard to ConIn; add IsaSerial to ConOut, ConIn, ErrOut.=0D +=0D + @param[in] DeviceHandle Handle of the LPC Bridge device.=0D +=0D + @retval EFI_SUCCESS Console devices on the LPC bridge have been added t= o=0D + ConOut, ConIn, and ErrOut.=0D +=0D + @return Error codes, due to EFI_DEVICE_PATH_PROTOCOL missin= g=0D + from DeviceHandle.=0D +**/=0D +EFI_STATUS=0D +PrepareLpcBridgeDevicePath (=0D + IN EFI_HANDLE DeviceHandle=0D + )=0D +{=0D + EFI_STATUS Status;=0D + EFI_DEVICE_PATH_PROTOCOL *DevicePath;=0D + EFI_DEVICE_PATH_PROTOCOL *TempDevicePath;=0D + CHAR16 *DevPathStr;=0D +=0D + DevicePath =3D NULL;=0D + Status =3D gBS->HandleProtocol (=0D + DeviceHandle,=0D + &gEfiDevicePathProtocolGuid,=0D + (VOID*)&DevicePath=0D + );=0D + if (EFI_ERROR (Status)) {=0D + return Status;=0D + }=0D + TempDevicePath =3D DevicePath;=0D +=0D + //=0D + // Register Keyboard=0D + //=0D + DevicePath =3D AppendDevicePathNode (DevicePath,=0D + (EFI_DEVICE_PATH_PROTOCOL *)&gPnpPs2KeyboardDeviceNode);= =0D +=0D + EfiBootManagerUpdateConsoleVariable (ConIn, DevicePath, NULL);=0D +=0D + //=0D + // Register COM1=0D + //=0D + DevicePath =3D TempDevicePath;=0D + gPnp16550ComPortDeviceNode.UID =3D 0;=0D +=0D + DevicePath =3D AppendDevicePathNode (DevicePath,=0D + (EFI_DEVICE_PATH_PROTOCOL *)&gPnp16550ComPortDeviceNode);= =0D + DevicePath =3D AppendDevicePathNode (DevicePath,=0D + (EFI_DEVICE_PATH_PROTOCOL *)&gUartDeviceNode);=0D + DevicePath =3D AppendDevicePathNode (DevicePath,=0D + (EFI_DEVICE_PATH_PROTOCOL *)&gTerminalTypeDeviceNode);=0D +=0D + //=0D + // Print Device Path=0D + //=0D + DevPathStr =3D ConvertDevicePathToText (DevicePath, FALSE, FALSE);=0D + if (DevPathStr !=3D NULL) {=0D + DEBUG((=0D + DEBUG_INFO,=0D + "BdsPlatform.c+%d: COM%d DevPath: %s\n",=0D + __LINE__,=0D + gPnp16550ComPortDeviceNode.UID + 1,=0D + DevPathStr=0D + ));=0D + FreePool(DevPathStr);=0D + }=0D +=0D + EfiBootManagerUpdateConsoleVariable (ConOut, DevicePath, NULL);=0D + EfiBootManagerUpdateConsoleVariable (ConIn, DevicePath, NULL);=0D + EfiBootManagerUpdateConsoleVariable (ErrOut, DevicePath, NULL);=0D +=0D + // Don't register COM2 which can be used for DBG instead so keep it clea= n=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D +EFI_STATUS=0D +GetGopDevicePath (=0D + IN EFI_DEVICE_PATH_PROTOCOL *PciDevicePath,=0D + OUT EFI_DEVICE_PATH_PROTOCOL **GopDevicePath=0D + )=0D +{=0D + UINTN Index;=0D + EFI_STATUS Status;=0D + EFI_HANDLE PciDeviceHandle;=0D + EFI_DEVICE_PATH_PROTOCOL *TempDevicePath;=0D + EFI_DEVICE_PATH_PROTOCOL *TempPciDevicePath;=0D + UINTN GopHandleCount;=0D + EFI_HANDLE *GopHandleBuffer;=0D +=0D + if (PciDevicePath =3D=3D NULL || GopDevicePath =3D=3D NULL) {=0D + return EFI_INVALID_PARAMETER;=0D + }=0D +=0D + //=0D + // Initialize the GopDevicePath to be PciDevicePath=0D + //=0D + *GopDevicePath =3D PciDevicePath;=0D + TempPciDevicePath =3D PciDevicePath;=0D +=0D + Status =3D gBS->LocateDevicePath (=0D + &gEfiDevicePathProtocolGuid,=0D + &TempPciDevicePath,=0D + &PciDeviceHandle=0D + );=0D + if (EFI_ERROR (Status)) {=0D + return Status;=0D + }=0D +=0D + //=0D + // Try to connect this handle, so that GOP driver could start on this=0D + // device and create child handles with GraphicsOutput Protocol installe= d=0D + // on them, then we get device paths of these child handles and select=0D + // them as possible console device.=0D + //=0D + gBS->ConnectController (PciDeviceHandle, NULL, NULL, FALSE);=0D +=0D + Status =3D gBS->LocateHandleBuffer (=0D + ByProtocol,=0D + &gEfiGraphicsOutputProtocolGuid,=0D + NULL,=0D + &GopHandleCount,=0D + &GopHandleBuffer=0D + );=0D + if (!EFI_ERROR (Status)) {=0D + //=0D + // Add all the child handles as possible Console Device=0D + //=0D + for (Index =3D 0; Index < GopHandleCount; Index++) {=0D + Status =3D gBS->HandleProtocol (GopHandleBuffer[Index],=0D + &gEfiDevicePathProtocolGuid, (VOID*)&TempDevicePath)= ;=0D + if (EFI_ERROR (Status)) {=0D + continue;=0D + }=0D + if (CompareMem (=0D + PciDevicePath,=0D + TempDevicePath,=0D + GetDevicePathSize (PciDevicePath) - END_DEVICE_PATH_LENGTH=0D + ) =3D=3D 0) {=0D + //=0D + // In current implementation, we only enable one of the child hand= les=0D + // as console device, i.e. sotre one of the child handle's device= =0D + // path to variable "ConOut"=0D + // In future, we could select all child handles to be console devi= ce=0D + //=0D +=0D + *GopDevicePath =3D TempDevicePath;=0D +=0D + //=0D + // Delete the PCI device's path that added by=0D + // GetPlugInPciVgaDevicePath(). Add the integrity GOP device path.= =0D + //=0D + EfiBootManagerUpdateConsoleVariable (ConOutDev, NULL, PciDevicePat= h);=0D + EfiBootManagerUpdateConsoleVariable (ConOutDev, TempDevicePath, NU= LL);=0D + }=0D + }=0D + gBS->FreePool (GopHandleBuffer);=0D + }=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D +/**=0D + Add PCI display to ConOut.=0D +=0D + @param[in] DeviceHandle Handle of the PCI display device.=0D +=0D + @retval EFI_SUCCESS The PCI display device has been added to ConOut.=0D +=0D + @return Error codes, due to EFI_DEVICE_PATH_PROTOCOL missin= g=0D + from DeviceHandle.=0D +**/=0D +EFI_STATUS=0D +PreparePciDisplayDevicePath (=0D + IN EFI_HANDLE DeviceHandle=0D + )=0D +{=0D + EFI_STATUS Status;=0D + EFI_DEVICE_PATH_PROTOCOL *DevicePath;=0D + EFI_DEVICE_PATH_PROTOCOL *GopDevicePath;=0D +=0D + DevicePath =3D NULL;=0D + GopDevicePath =3D NULL;=0D + Status =3D gBS->HandleProtocol (=0D + DeviceHandle,=0D + &gEfiDevicePathProtocolGuid,=0D + (VOID*)&DevicePath=0D + );=0D + if (EFI_ERROR (Status)) {=0D + return Status;=0D + }=0D +=0D + GetGopDevicePath (DevicePath, &GopDevicePath);=0D + DevicePath =3D GopDevicePath;=0D +=0D + EfiBootManagerUpdateConsoleVariable (ConOut, DevicePath, NULL);=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D +/**=0D + Add PCI Serial to ConOut, ConIn, ErrOut.=0D +=0D + @param[in] DeviceHandle Handle of the PCI serial device.=0D +=0D + @retval EFI_SUCCESS The PCI serial device has been added to ConOut, Con= In,=0D + ErrOut.=0D +=0D + @return Error codes, due to EFI_DEVICE_PATH_PROTOCOL missin= g=0D + from DeviceHandle.=0D +**/=0D +EFI_STATUS=0D +PreparePciSerialDevicePath (=0D + IN EFI_HANDLE DeviceHandle=0D + )=0D +{=0D + EFI_STATUS Status;=0D + EFI_DEVICE_PATH_PROTOCOL *DevicePath;=0D +=0D + DevicePath =3D NULL;=0D + Status =3D gBS->HandleProtocol (=0D + DeviceHandle,=0D + &gEfiDevicePathProtocolGuid,=0D + (VOID*)&DevicePath=0D + );=0D + if (EFI_ERROR (Status)) {=0D + return Status;=0D + }=0D +=0D + DevicePath =3D AppendDevicePathNode (DevicePath,=0D + (EFI_DEVICE_PATH_PROTOCOL *)&gUartDeviceNode);=0D + DevicePath =3D AppendDevicePathNode (DevicePath,=0D + (EFI_DEVICE_PATH_PROTOCOL *)&gTerminalTypeDeviceNode);=0D +=0D + EfiBootManagerUpdateConsoleVariable (ConOut, DevicePath, NULL);=0D + EfiBootManagerUpdateConsoleVariable (ConIn, DevicePath, NULL);=0D + EfiBootManagerUpdateConsoleVariable (ErrOut, DevicePath, NULL);=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D +EFI_STATUS=0D +VisitAllInstancesOfProtocol (=0D + IN EFI_GUID *Id,=0D + IN PROTOCOL_INSTANCE_CALLBACK CallBackFunction,=0D + IN VOID *Context=0D + )=0D +{=0D + EFI_STATUS Status;=0D + UINTN HandleCount;=0D + EFI_HANDLE *HandleBuffer;=0D + UINTN Index;=0D + VOID *Instance;=0D +=0D + //=0D + // Start to check all the PciIo to find all possible device=0D + //=0D + HandleCount =3D 0;=0D + HandleBuffer =3D NULL;=0D + Status =3D gBS->LocateHandleBuffer (=0D + ByProtocol,=0D + Id,=0D + NULL,=0D + &HandleCount,=0D + &HandleBuffer=0D + );=0D + if (EFI_ERROR (Status)) {=0D + return Status;=0D + }=0D +=0D + for (Index =3D 0; Index < HandleCount; Index++) {=0D + Status =3D gBS->HandleProtocol (HandleBuffer[Index], Id, &Instance);=0D + if (EFI_ERROR (Status)) {=0D + continue;=0D + }=0D +=0D + Status =3D (*CallBackFunction) (=0D + HandleBuffer[Index],=0D + Instance,=0D + Context=0D + );=0D + }=0D +=0D + gBS->FreePool (HandleBuffer);=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +VisitingAPciInstance (=0D + IN EFI_HANDLE Handle,=0D + IN VOID *Instance,=0D + IN VOID *Context=0D + )=0D +{=0D + EFI_STATUS Status;=0D + EFI_PCI_IO_PROTOCOL *PciIo;=0D + PCI_TYPE00 Pci;=0D +=0D + PciIo =3D (EFI_PCI_IO_PROTOCOL*) Instance;=0D +=0D + //=0D + // Check for all PCI device=0D + //=0D + Status =3D PciIo->Pci.Read (=0D + PciIo,=0D + EfiPciIoWidthUint32,=0D + 0,=0D + sizeof (Pci) / sizeof (UINT32),=0D + &Pci=0D + );=0D + if (EFI_ERROR (Status)) {=0D + return Status;=0D + }=0D +=0D + return (*(VISIT_PCI_INSTANCE_CALLBACK)(UINTN) Context) (=0D + Handle,=0D + PciIo,=0D + &Pci=0D + );=0D +=0D +}=0D +=0D +=0D +=0D +EFI_STATUS=0D +VisitAllPciInstances (=0D + IN VISIT_PCI_INSTANCE_CALLBACK CallBackFunction=0D + )=0D +{=0D + return VisitAllInstancesOfProtocol (=0D + &gEfiPciIoProtocolGuid,=0D + VisitingAPciInstance,=0D + (VOID*)(UINTN) CallBackFunction=0D + );=0D +}=0D +=0D +=0D +/**=0D + Do platform specific PCI Device check and add them to=0D + ConOut, ConIn, ErrOut.=0D +=0D + @param[in] Handle - Handle of PCI device instance=0D + @param[in] PciIo - PCI IO protocol instance=0D + @param[in] Pci - PCI Header register block=0D +=0D + @retval EFI_SUCCESS - PCI Device check and Console variable update=0D + successfully.=0D + @retval EFI_STATUS - PCI Device check or Console variable update fail.=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +DetectAndPreparePlatformPciDevicePath (=0D + IN EFI_HANDLE Handle,=0D + IN EFI_PCI_IO_PROTOCOL *PciIo,=0D + IN PCI_TYPE00 *Pci=0D + )=0D +{=0D + EFI_STATUS Status;=0D +=0D + Status =3D PciIo->Attributes (=0D + PciIo,=0D + EfiPciIoAttributeOperationEnable,=0D + EFI_PCI_DEVICE_ENABLE,=0D + NULL=0D + );=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + //=0D + // Here we decide whether it is LPC Bridge=0D + //=0D + if ((IS_PCI_LPC (Pci)) ||=0D + ((IS_PCI_ISA_PDECODE (Pci)) &&=0D + (Pci->Hdr.VendorId =3D=3D 0x8086) &&=0D + (Pci->Hdr.DeviceId =3D=3D 0x7000)=0D + )=0D + ) {=0D + //=0D + // Add IsaKeyboard to ConIn,=0D + // add IsaSerial to ConOut, ConIn, ErrOut=0D + //=0D + DEBUG ((DEBUG_INFO, "Found LPC Bridge device\n"));=0D + PrepareLpcBridgeDevicePath (Handle);=0D + return EFI_SUCCESS;=0D + }=0D + //=0D + // Here we decide which Serial device to enable in PCI bus=0D + //=0D + if (IS_PCI_16550SERIAL (Pci)) {=0D + //=0D + // Add them to ConOut, ConIn, ErrOut.=0D + //=0D + DEBUG ((DEBUG_INFO, "Found PCI 16550 SERIAL device\n"));=0D + PreparePciSerialDevicePath (Handle);=0D + return EFI_SUCCESS;=0D + }=0D +=0D + //=0D + // Here we decide which display device to enable in PCI bus=0D + //=0D + if (IS_PCI_DISPLAY (Pci)) {=0D + //=0D + // Add them to ConOut.=0D + //=0D + DEBUG ((DEBUG_INFO, "Found PCI display device\n"));=0D + PreparePciDisplayDevicePath (Handle);=0D + return EFI_SUCCESS;=0D + }=0D +=0D + return Status;=0D +}=0D +=0D +=0D +/**=0D + Connect the predefined platform default console device.=0D +=0D + Always try to find and enable PCI display devices.=0D +=0D + @param[in] PlatformConsole Predefined platform default console device a= rray.=0D +**/=0D +VOID=0D +PlatformInitializeConsole (=0D + IN PLATFORM_CONSOLE_CONNECT_ENTRY *PlatformConsole=0D + )=0D +{=0D + UINTN Index;=0D +=0D + //=0D + // Do platform specific PCI Device check and add them to ConOut, ConIn,= =0D + // ErrOut=0D + //=0D + VisitAllPciInstances (DetectAndPreparePlatformPciDevicePath);=0D +=0D + //=0D + // Have chance to connect the platform default console,=0D + // the platform default console is the minimum device group=0D + // the platform should support=0D + //=0D + for (Index =3D 0; PlatformConsole[Index].DevicePath !=3D NULL; ++Index) = {=0D + //=0D + // Update the console variable with the connect type=0D + //=0D + if ((PlatformConsole[Index].ConnectType & CONSOLE_IN) =3D=3D CONSOLE_I= N) {=0D + EfiBootManagerUpdateConsoleVariable (ConIn,=0D + PlatformConsole[Index].DevicePath, NULL);=0D + }=0D + if ((PlatformConsole[Index].ConnectType & CONSOLE_OUT) =3D=3D CONSOLE_= OUT) {=0D + EfiBootManagerUpdateConsoleVariable (ConOut,=0D + PlatformConsole[Index].DevicePath, NULL);=0D + }=0D + if ((PlatformConsole[Index].ConnectType & STD_ERROR) =3D=3D STD_ERROR)= {=0D + EfiBootManagerUpdateConsoleVariable (ErrOut,=0D + PlatformConsole[Index].DevicePath, NULL);=0D + }=0D + }=0D +}=0D +=0D +=0D +/**=0D + Configure PCI Interrupt Line register for applicable devices=0D + Ported from SeaBIOS, src/fw/pciinit.c, *_pci_slot_get_irq()=0D +=0D + @param[in] Handle - Handle of PCI device instance=0D + @param[in] PciIo - PCI IO protocol instance=0D + @param[in] PciHdr - PCI Header register block=0D +=0D + @retval EFI_SUCCESS - PCI Interrupt Line register configured successfull= y.=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +SetPciIntLine (=0D + IN EFI_HANDLE Handle,=0D + IN EFI_PCI_IO_PROTOCOL *PciIo,=0D + IN PCI_TYPE00 *PciHdr=0D + )=0D +{=0D + EFI_DEVICE_PATH_PROTOCOL *DevPathNode;=0D + EFI_DEVICE_PATH_PROTOCOL *DevPath;=0D + UINTN RootSlot;=0D + UINTN Idx;=0D + UINT8 IrqLine;=0D + EFI_STATUS Status;=0D + UINT32 RootBusNumber;=0D +=0D + Status =3D EFI_SUCCESS;=0D +=0D + if (PciHdr->Device.InterruptPin !=3D 0) {=0D +=0D + DevPathNode =3D DevicePathFromHandle (Handle);=0D + ASSERT (DevPathNode !=3D NULL);=0D + DevPath =3D DevPathNode;=0D +=0D + RootBusNumber =3D 0;=0D + if (DevicePathType (DevPathNode) =3D=3D ACPI_DEVICE_PATH &&=0D + DevicePathSubType (DevPathNode) =3D=3D ACPI_DP &&=0D + ((ACPI_HID_DEVICE_PATH *)DevPathNode)->HID =3D=3D EISA_PNP_ID(0x0A= 03)) {=0D + RootBusNumber =3D ((ACPI_HID_DEVICE_PATH *)DevPathNode)->UID;=0D + }=0D +=0D + //=0D + // Compute index into PciHostIrqs[] table by walking=0D + // the device path and adding up all device numbers=0D + //=0D + Status =3D EFI_NOT_FOUND;=0D + RootSlot =3D 0;=0D + Idx =3D PciHdr->Device.InterruptPin - 1;=0D + while (!IsDevicePathEnd (DevPathNode)) {=0D + if (DevicePathType (DevPathNode) =3D=3D HARDWARE_DEVICE_PATH &&=0D + DevicePathSubType (DevPathNode) =3D=3D HW_PCI_DP) {=0D +=0D + Idx +=3D ((PCI_DEVICE_PATH *)DevPathNode)->Device;=0D +=0D + //=0D + // Unlike SeaBIOS, which starts climbing from the leaf device=0D + // up toward the root, we traverse the device path starting at=0D + // the root moving toward the leaf node.=0D + // The slot number of the top-level parent bridge is needed for=0D + // Q35 cases with more than 24 slots on the root bus.=0D + //=0D + if (Status !=3D EFI_SUCCESS) {=0D + Status =3D EFI_SUCCESS;=0D + RootSlot =3D ((PCI_DEVICE_PATH *)DevPathNode)->Device;=0D + }=0D + }=0D +=0D + DevPathNode =3D NextDevicePathNode (DevPathNode);=0D + }=0D + if (EFI_ERROR (Status)) {=0D + return Status;=0D + }=0D + if (RootBusNumber =3D=3D 0 && RootSlot =3D=3D 0) {=0D + DEBUG((=0D + DEBUG_ERROR,=0D + "%a: PCI host bridge (00:00.0) should have no interrupts!\n",=0D + __FUNCTION__=0D + ));=0D + ASSERT (FALSE);=0D + }=0D +=0D + //=0D + // Final PciHostIrqs[] index calculation depends on the platform=0D + // and should match SeaBIOS src/fw/pciinit.c *_pci_slot_get_irq()=0D + //=0D + switch (mHostBridgeDevId) {=0D + case 0x1275: // BHYVE=0D + case INTEL_82441_DEVICE_ID:=0D + Idx -=3D 1;=0D + break;=0D + case INTEL_Q35_MCH_DEVICE_ID:=0D + //=0D + // SeaBIOS contains the following comment:=0D + // "Slots 0-24 rotate slot:pin mapping similar to piix above, but= =0D + // with a different starting index - see q35-acpi-dsdt.dsl.=0D + //=0D + // Slots 25-31 all use LNKA mapping (or LNKE, but A:D =3D E:H)"=0D + //=0D + if (RootSlot > 24) {=0D + //=0D + // in this case, subtract back out RootSlot from Idx=0D + // (SeaBIOS never adds it to begin with, but that would make our= =0D + // device path traversal loop above too awkward)=0D + //=0D + Idx -=3D RootSlot;=0D + }=0D + break;=0D + default:=0D + ASSERT (FALSE); // should never get here=0D + }=0D + Idx %=3D ARRAY_SIZE (PciHostIrqs);=0D + IrqLine =3D PciHostIrqs[Idx];=0D +=0D + DEBUG_CODE_BEGIN ();=0D + {=0D + CHAR16 *DevPathString;=0D + STATIC CHAR16 Fallback[] =3D L"<failed to convert>";=0D + UINTN Segment, Bus, Device, Function;=0D +=0D + DevPathString =3D ConvertDevicePathToText (DevPath, FALSE, FALSE);=0D + if (DevPathString =3D=3D NULL) {=0D + DevPathString =3D Fallback;=0D + }=0D + Status =3D PciIo->GetLocation (PciIo, &Segment, &Bus, &Device, &Func= tion);=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + DEBUG ((DEBUG_VERBOSE, "%a: [%02x:%02x.%x] %s -> 0x%02x\n", __FUNCTI= ON__,=0D + (UINT32)Bus, (UINT32)Device, (UINT32)Function, DevPathString,=0D + IrqLine));=0D +=0D + if (DevPathString !=3D Fallback) {=0D + FreePool (DevPathString);=0D + }=0D + }=0D + DEBUG_CODE_END ();=0D +=0D + //=0D + // Set PCI Interrupt Line register for this device to PciHostIrqs[Idx]= =0D + //=0D + Status =3D PciIo->Pci.Write (=0D + PciIo,=0D + EfiPciIoWidthUint8,=0D + PCI_INT_LINE_OFFSET,=0D + 1,=0D + &IrqLine=0D + );=0D + }=0D +=0D + return Status;=0D +}=0D +=0D +=0D +VOID=0D +PciAcpiInitialization (=0D + )=0D +{=0D + UINTN Pmba;=0D +=0D + //=0D + // Query Host Bridge DID to determine platform type=0D + //=0D + mHostBridgeDevId =3D PcdGet16 (PcdOvmfHostBridgePciDevId);=0D + switch (mHostBridgeDevId) {=0D + case 0x1275: // BHYVE=0D + case INTEL_82441_DEVICE_ID:=0D + Pmba =3D POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);=0D + //=0D + // 00:01.0 ISA Bridge (PIIX4) LNK routing targets=0D + //=0D + PciWrite8 (PCI_LIB_ADDRESS (0, 1, 0, 0x60), 0x0b); // A=0D + PciWrite8 (PCI_LIB_ADDRESS (0, 1, 0, 0x61), 0x0b); // B=0D + PciWrite8 (PCI_LIB_ADDRESS (0, 1, 0, 0x62), 0x0a); // C=0D + PciWrite8 (PCI_LIB_ADDRESS (0, 1, 0, 0x63), 0x0a); // D=0D + break;=0D + case INTEL_Q35_MCH_DEVICE_ID:=0D + Pmba =3D POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);=0D + //=0D + // 00:1f.0 LPC Bridge (Q35) LNK routing targets=0D + //=0D + PciWrite8 (PCI_LIB_ADDRESS (0, 0x1f, 0, 0x60), 0x0a); // A=0D + PciWrite8 (PCI_LIB_ADDRESS (0, 0x1f, 0, 0x61), 0x0a); // B=0D + PciWrite8 (PCI_LIB_ADDRESS (0, 0x1f, 0, 0x62), 0x0b); // C=0D + PciWrite8 (PCI_LIB_ADDRESS (0, 0x1f, 0, 0x63), 0x0b); // D=0D + PciWrite8 (PCI_LIB_ADDRESS (0, 0x1f, 0, 0x68), 0x0a); // E=0D + PciWrite8 (PCI_LIB_ADDRESS (0, 0x1f, 0, 0x69), 0x0a); // F=0D + PciWrite8 (PCI_LIB_ADDRESS (0, 0x1f, 0, 0x6a), 0x0b); // G=0D + PciWrite8 (PCI_LIB_ADDRESS (0, 0x1f, 0, 0x6b), 0x0b); // H=0D + break;=0D + default:=0D + DEBUG ((DEBUG_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",= =0D + __FUNCTION__, mHostBridgeDevId));=0D + ASSERT (FALSE);=0D + return;=0D + }=0D +=0D + //=0D + // Initialize PCI_INTERRUPT_LINE for applicable present PCI devices=0D + //=0D + VisitAllPciInstances (SetPciIntLine);=0D +=0D + //=0D + // Set ACPI SCI_EN bit in PMCNTRL=0D + //=0D + IoOr16 ((PciRead32 (Pmba) & ~BIT0) + 4, BIT0);=0D +}=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +ConnectRecursivelyIfPciMassStorage (=0D + IN EFI_HANDLE Handle,=0D + IN EFI_PCI_IO_PROTOCOL *Instance,=0D + IN PCI_TYPE00 *PciHeader=0D + )=0D +{=0D + EFI_STATUS Status;=0D + EFI_DEVICE_PATH_PROTOCOL *DevicePath;=0D + CHAR16 *DevPathStr;=0D +=0D + //=0D + // Recognize PCI Mass Storage, and Xen PCI devices=0D + //=0D + if (IS_CLASS1 (PciHeader, PCI_CLASS_MASS_STORAGE)) {=0D + DevicePath =3D NULL;=0D + Status =3D gBS->HandleProtocol (=0D + Handle,=0D + &gEfiDevicePathProtocolGuid,=0D + (VOID*)&DevicePath=0D + );=0D + if (EFI_ERROR (Status)) {=0D + return Status;=0D + }=0D +=0D + //=0D + // Print Device Path=0D + //=0D + DevPathStr =3D ConvertDevicePathToText (DevicePath, FALSE, FALSE);=0D + if (DevPathStr !=3D NULL) {=0D + DEBUG((=0D + DEBUG_INFO,=0D + "Found %s device: %s\n",=0D + (IS_CLASS1 (PciHeader, PCI_CLASS_MASS_STORAGE) ?=0D + L"Mass Storage" :=0D + L"Xen"=0D + ),=0D + DevPathStr=0D + ));=0D + FreePool(DevPathStr);=0D + }=0D +=0D + Status =3D gBS->ConnectController (Handle, NULL, NULL, TRUE);=0D + if (EFI_ERROR (Status)) {=0D + return Status;=0D + }=0D +=0D + }=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D +=0D +/**=0D + This notification function is invoked when the=0D + EMU Variable FVB has been changed.=0D +=0D + @param Event The event that occurred=0D + @param Context For EFI compatibility. Not used.=0D +=0D +**/=0D +VOID=0D +EFIAPI=0D +EmuVariablesUpdatedCallback (=0D + IN EFI_EVENT Event,=0D + IN VOID *Context=0D + )=0D +{=0D + DEBUG ((DEBUG_INFO, "EmuVariablesUpdatedCallback\n"));=0D + UpdateNvVarsOnFileSystem ();=0D +}=0D +=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +VisitingFileSystemInstance (=0D + IN EFI_HANDLE Handle,=0D + IN VOID *Instance,=0D + IN VOID *Context=0D + )=0D +{=0D + EFI_STATUS Status;=0D + STATIC BOOLEAN ConnectedToFileSystem =3D FALSE;=0D + RETURN_STATUS PcdStatus;=0D +=0D + if (ConnectedToFileSystem) {=0D + return EFI_ALREADY_STARTED;=0D + }=0D +=0D + Status =3D ConnectNvVarsToFileSystem (Handle);=0D + if (EFI_ERROR (Status)) {=0D + return Status;=0D + }=0D +=0D + ConnectedToFileSystem =3D TRUE;=0D + mEmuVariableEvent =3D=0D + EfiCreateProtocolNotifyEvent (=0D + &gEfiDevicePathProtocolGuid,=0D + TPL_CALLBACK,=0D + EmuVariablesUpdatedCallback,=0D + NULL,=0D + &mEmuVariableEventReg=0D + );=0D + PcdStatus =3D PcdSet64S (PcdEmuVariableEvent,=0D + (UINT64)(UINTN) mEmuVariableEvent);=0D + ASSERT_RETURN_ERROR (PcdStatus);=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D +=0D +VOID=0D +PlatformBdsRestoreNvVarsFromHardDisk (=0D + )=0D +{=0D + VisitAllPciInstances (ConnectRecursivelyIfPciMassStorage);=0D + VisitAllInstancesOfProtocol (=0D + &gEfiSimpleFileSystemProtocolGuid,=0D + VisitingFileSystemInstance,=0D + NULL=0D + );=0D +=0D +}=0D +=0D +/**=0D + Connect with predefined platform connect sequence.=0D +=0D + The OEM/IBV can customize with their own connect sequence.=0D +**/=0D +VOID=0D +PlatformBdsConnectSequence (=0D + VOID=0D + )=0D +{=0D + UINTN Index;=0D +=0D + DEBUG ((DEBUG_INFO, "PlatformBdsConnectSequence\n"));=0D +=0D + Index =3D 0;=0D +=0D + //=0D + // Here we can get the customized platform connect sequence=0D + // Notes: we can connect with new variable which record the=0D + // last time boots connect device path sequence=0D + //=0D + while (gPlatformConnectSequence[Index] !=3D NULL) {=0D + //=0D + // Build the platform boot option=0D + //=0D + EfiBootManagerConnectDevicePath (gPlatformConnectSequence[Index], NULL= );=0D + Index++;=0D + }=0D +=0D + //=0D + // Just use the simple policy to connect all devices=0D + //=0D + DEBUG ((DEBUG_INFO, "EfiBootManagerConnectAll\n"));=0D + EfiBootManagerConnectAll ();=0D +}=0D +=0D +/**=0D + Save the S3 boot script.=0D +=0D + Note that DxeSmmReadyToLock must be signaled after this function returns= ;=0D + otherwise the script wouldn't be saved actually.=0D +**/=0D +#if defined(__GNUC__)=0D +__attribute__((unused))=0D +#endif=0D +STATIC=0D +VOID=0D +SaveS3BootScript (=0D + VOID=0D + )=0D +{=0D + EFI_STATUS Status;=0D + EFI_S3_SAVE_STATE_PROTOCOL *BootScript;=0D + STATIC CONST UINT8 Info[] =3D { 0xDE, 0xAD, 0xBE, 0xEF };=0D +=0D + Status =3D gBS->LocateProtocol (&gEfiS3SaveStateProtocolGuid, NULL,=0D + (VOID **) &BootScript);=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + //=0D + // Despite the opcode documentation in the PI spec, the protocol=0D + // implementation embeds a deep copy of the info in the boot script, rat= her=0D + // than storing just a pointer to runtime or NVS storage.=0D + //=0D + Status =3D BootScript->Write(BootScript, EFI_BOOT_SCRIPT_INFORMATION_OPC= ODE,=0D + (UINT32) sizeof Info,=0D + (EFI_PHYSICAL_ADDRESS)(UINTN) &Info);=0D + ASSERT_EFI_ERROR (Status);=0D +}=0D +=0D +=0D +/**=0D + Do the platform specific action after the console is ready=0D +=0D + Possible things that can be done in PlatformBootManagerAfterConsole:=0D +=0D + > Console post action:=0D + > Dynamically switch output mode from 100x31 to 80x25 for certain sena= rino=0D + > Signal console ready platform customized event=0D + > Run diagnostics like memory testing=0D + > Connect certain devices=0D + > Dispatch aditional option roms=0D + > Special boot: e.g.: USB boot, enter UI=0D +**/=0D +VOID=0D +EFIAPI=0D +PlatformBootManagerAfterConsole (=0D + VOID=0D + )=0D +{=0D + EFI_BOOT_MODE BootMode;=0D +=0D + DEBUG ((DEBUG_INFO, "PlatformBootManagerAfterConsole\n"));=0D +=0D + if (PcdGetBool (PcdOvmfFlashVariablesEnable)) {=0D + DEBUG ((DEBUG_INFO, "PlatformBdsPolicyBehavior: not restoring NvVars "= =0D + "from disk since flash variables appear to be supported.\n"));=0D + } else {=0D + //=0D + // Try to restore variables from the hard disk early so=0D + // they can be used for the other BDS connect operations.=0D + //=0D + /* XXX Calling this causes Keyboard to be removed from ConIn which=0D + results in unresponsive guest boot loaders in the GUI. Restore it=0D + when we figure out what is needed to get NvVars storage done=0D + properly.=0D + */=0D + /*PlatformBdsRestoreNvVarsFromHardDisk ();*/=0D + }=0D +=0D + //=0D + // Get current Boot Mode=0D + //=0D + BootMode =3D GetBootModeHob ();=0D + DEBUG ((DEBUG_INFO, "Boot Mode:%x\n", BootMode));=0D +=0D + //=0D + // Go the different platform policy with different boot mode=0D + // Notes: this part code can be change with the table policy=0D + //=0D + ASSERT (BootMode =3D=3D BOOT_WITH_FULL_CONFIGURATION);=0D +=0D + //=0D + // Logo show=0D + //=0D + BootLogoEnableLogo ();=0D +=0D + //=0D + // Set PCI Interrupt Line registers and ACPI SCI_EN=0D + //=0D + PciAcpiInitialization ();=0D +=0D + //=0D + // Process TPM PPI request=0D + //=0D + Tcg2PhysicalPresenceLibProcessRequest (NULL);=0D +=0D + //=0D + // Perform some platform specific connect sequence=0D + //=0D + PlatformBdsConnectSequence ();=0D +=0D + EfiBootManagerRefreshAllBootOption ();=0D +=0D + //=0D + // Register UEFI Shell=0D + //=0D + PlatformRegisterFvBootOption (=0D + &gUefiShellFileGuid, L"EFI Internal Shell", LOAD_OPTION_ACTIVE=0D + );=0D +=0D + RemoveStaleFvFileOptions ();=0D +=0D + PlatformBmPrintScRegisterHandler ();=0D +}=0D +=0D +/**=0D + This notification function is invoked when an instance of the=0D + EFI_DEVICE_PATH_PROTOCOL is produced.=0D +=0D + @param Event The event that occurred=0D + @param Context For EFI compatibility. Not used.=0D +=0D +**/=0D +VOID=0D +EFIAPI=0D +NotifyDevPath (=0D + IN EFI_EVENT Event,=0D + IN VOID *Context=0D + )=0D +{=0D + EFI_HANDLE Handle;=0D + EFI_STATUS Status;=0D + UINTN BufferSize;=0D + EFI_DEVICE_PATH_PROTOCOL *DevPathNode;=0D + ATAPI_DEVICE_PATH *Atapi;=0D +=0D + //=0D + // Examine all new handles=0D + //=0D + for (;;) {=0D + //=0D + // Get the next handle=0D + //=0D + BufferSize =3D sizeof (Handle);=0D + Status =3D gBS->LocateHandle (=0D + ByRegisterNotify,=0D + NULL,=0D + mEfiDevPathNotifyReg,=0D + &BufferSize,=0D + &Handle=0D + );=0D +=0D + //=0D + // If not found, we're done=0D + //=0D + if (EFI_NOT_FOUND =3D=3D Status) {=0D + break;=0D + }=0D +=0D + if (EFI_ERROR (Status)) {=0D + continue;=0D + }=0D +=0D + //=0D + // Get the DevicePath protocol on that handle=0D + //=0D + Status =3D gBS->HandleProtocol (Handle, &gEfiDevicePathProtocolGuid,=0D + (VOID **)&DevPathNode);=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + while (!IsDevicePathEnd (DevPathNode)) {=0D + //=0D + // Find the handler to dump this device path node=0D + //=0D + if (=0D + (DevicePathType(DevPathNode) =3D=3D MESSAGING_DEVICE_PATH) &&=0D + (DevicePathSubType(DevPathNode) =3D=3D MSG_ATAPI_DP)=0D + ) {=0D + Atapi =3D (ATAPI_DEVICE_PATH*) DevPathNode;=0D + PciOr16 (=0D + PCI_LIB_ADDRESS (=0D + 0,=0D + 1,=0D + 1,=0D + (Atapi->PrimarySecondary =3D=3D 1) ? 0x42: 0x40=0D + ),=0D + BIT15=0D + );=0D + }=0D +=0D + //=0D + // Next device path node=0D + //=0D + DevPathNode =3D NextDevicePathNode (DevPathNode);=0D + }=0D + }=0D +=0D + return;=0D +}=0D +=0D +=0D +VOID=0D +InstallDevicePathCallback (=0D + VOID=0D + )=0D +{=0D + DEBUG ((DEBUG_INFO, "Registered NotifyDevPath Event\n"));=0D + mEfiDevPathEvent =3D EfiCreateProtocolNotifyEvent (=0D + &gEfiDevicePathProtocolGuid,=0D + TPL_CALLBACK,=0D + NotifyDevPath,=0D + NULL,=0D + &mEfiDevPathNotifyReg=0D + );=0D +}=0D +=0D +/**=0D + This function is called each second during the boot manager waits the=0D + timeout.=0D +=0D + @param TimeoutRemain The remaining timeout.=0D +**/=0D +VOID=0D +EFIAPI=0D +PlatformBootManagerWaitCallback (=0D + UINT16 TimeoutRemain=0D + )=0D +{=0D + EFI_GRAPHICS_OUTPUT_BLT_PIXEL_UNION Black;=0D + EFI_GRAPHICS_OUTPUT_BLT_PIXEL_UNION White;=0D + UINT16 Timeout;=0D +=0D + Timeout =3D PcdGet16 (PcdPlatformBootTimeOut);=0D +=0D + Black.Raw =3D 0x00000000;=0D + White.Raw =3D 0x00FFFFFF;=0D +=0D + BootLogoUpdateProgress (=0D + White.Pixel,=0D + Black.Pixel,=0D + L"Start boot option",=0D + White.Pixel,=0D + (Timeout - TimeoutRemain) * 100 / Timeout,=0D + 0=0D + );=0D +}=0D +=0D +/**=0D + The function is called when no boot option could be launched,=0D + including platform recovery options and options pointing to applications= =0D + built into firmware volumes.=0D +=0D + If this function returns, BDS attempts to enter an infinite loop.=0D +**/=0D +VOID=0D +EFIAPI=0D +PlatformBootManagerUnableToBoot (=0D + VOID=0D + )=0D +{=0D + EFI_STATUS Status;=0D + EFI_INPUT_KEY Key;=0D + EFI_BOOT_MANAGER_LOAD_OPTION BootManagerMenu;=0D + UINTN Index;=0D +=0D + //=0D + // BootManagerMenu doesn't contain the correct information when return s= tatus=0D + // is EFI_NOT_FOUND.=0D + //=0D + Status =3D EfiBootManagerGetBootManagerMenu (&BootManagerMenu);=0D + if (EFI_ERROR (Status)) {=0D + return;=0D + }=0D + //=0D + // Normally BdsDxe does not print anything to the system console, but th= is is=0D + // a last resort -- the end-user will likely not see any DEBUG messages= =0D + // logged in this situation.=0D + //=0D + // AsciiPrint() will NULL-check gST->ConOut internally. We check gST->Co= nIn=0D + // here to see if it makes sense to request and wait for a keypress.=0D + //=0D + if (gST->ConIn !=3D NULL) {=0D + AsciiPrint (=0D + "%a: No bootable option or device was found.\n"=0D + "%a: Press any key to enter the Boot Manager Menu.\n",=0D + gEfiCallerBaseName,=0D + gEfiCallerBaseName=0D + );=0D + Status =3D gBS->WaitForEvent (1, &gST->ConIn->WaitForKey, &Index);=0D + ASSERT_EFI_ERROR (Status);=0D + ASSERT (Index =3D=3D 0);=0D +=0D + //=0D + // Drain any queued keys.=0D + //=0D + while (!EFI_ERROR (gST->ConIn->ReadKeyStroke (gST->ConIn, &Key))) {=0D + //=0D + // just throw away Key=0D + //=0D + }=0D + }=0D +=0D + for (;;) {=0D + EfiBootManagerBoot (&BootManagerMenu);=0D + }=0D +}=0D diff --git a/OvmfPkg/Bhyve/Library/PlatformBootManagerLib/BdsPlatform.h b/O= vmfPkg/Bhyve/Library/PlatformBootManagerLib/BdsPlatform.h new file mode 100644 index 0000000000..382fe191a9 --- /dev/null +++ b/OvmfPkg/Bhyve/Library/PlatformBootManagerLib/BdsPlatform.h @@ -0,0 +1,190 @@ +/** @file=0D + Platform BDS customizations include file.=0D +=0D + Copyright (c) 2020, Rebecca Cran <rebecca@...>=0D + Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +Module Name:=0D +=0D + BdsPlatform.h=0D +=0D +Abstract:=0D +=0D + Head file for BDS Platform specific code=0D +=0D +**/=0D +=0D +#ifndef _PLATFORM_SPECIFIC_BDS_PLATFORM_H_=0D +#define _PLATFORM_SPECIFIC_BDS_PLATFORM_H_=0D +=0D +=0D +#include <PiDxe.h>=0D +=0D +#include <IndustryStandard/Pci.h>=0D +#include <IndustryStandard/Acpi.h>=0D +#include <IndustryStandard/SmBios.h>=0D +#include <IndustryStandard/PeImage.h>=0D +#include <IndustryStandard/Virtio095.h>=0D +=0D +#include <Library/DebugLib.h>=0D +#include <Library/BaseMemoryLib.h>=0D +#include <Library/UefiBootServicesTableLib.h>=0D +#include <Library/UefiRuntimeServicesTableLib.h>=0D +#include <Library/MemoryAllocationLib.h>=0D +#include <Library/BaseLib.h>=0D +#include <Library/PcdLib.h>=0D +#include <Library/PciLib.h>=0D +#include <Library/UefiBootManagerLib.h>=0D +#include <Library/BootLogoLib.h>=0D +#include <Library/HobLib.h>=0D +#include <Library/UefiLib.h>=0D +#include <Library/DxeServicesTableLib.h>=0D +#include <Library/DevicePathLib.h>=0D +#include <Library/IoLib.h>=0D +#include <Library/NvVarsFileLib.h>=0D +#include <Library/QemuFwCfgLib.h>=0D +#include <Library/QemuFwCfgS3Lib.h>=0D +#include <Library/QemuBootOrderLib.h>=0D +=0D +#include <Protocol/Decompress.h>=0D +#include <Protocol/PciIo.h>=0D +#include <Protocol/FirmwareVolume2.h>=0D +#include <Protocol/SimpleFileSystem.h>=0D +#include <Protocol/PciRootBridgeIo.h>=0D +#include <Protocol/S3SaveState.h>=0D +#include <Protocol/DxeSmmReadyToLock.h>=0D +#include <Protocol/LoadedImage.h>=0D +=0D +#include <Guid/Acpi.h>=0D +#include <Guid/SmBios.h>=0D +#include <Guid/HobList.h>=0D +#include <Guid/GlobalVariable.h>=0D +#include <Guid/EventGroup.h>=0D +#include <Guid/DebugAgentGuid.h>=0D +=0D +#include <OvmfPlatforms.h>=0D +=0D +extern EFI_DEVICE_PATH_PROTOCOL *gPlatformConnectSequence[];=0D +extern ACPI_HID_DEVICE_PATH gPnpPs2KeyboardDeviceNode;=0D +extern ACPI_HID_DEVICE_PATH gPnp16550ComPortDeviceNode;=0D +extern UART_DEVICE_PATH gUartDeviceNode;=0D +extern VENDOR_DEVICE_PATH gTerminalTypeDeviceNode;=0D +=0D +#define PCI_DEVICE_PATH_NODE(Func, Dev) \=0D + { \=0D + { \=0D + HARDWARE_DEVICE_PATH, \=0D + HW_PCI_DP, \=0D + { \=0D + (UINT8) (sizeof (PCI_DEVICE_PATH)), \=0D + (UINT8) ((sizeof (PCI_DEVICE_PATH)) >> 8) \=0D + } \=0D + }, \=0D + (Func), \=0D + (Dev) \=0D + }=0D +=0D +#define PNPID_DEVICE_PATH_NODE(PnpId) \=0D + { \=0D + { \=0D + ACPI_DEVICE_PATH, \=0D + ACPI_DP, \=0D + { \=0D + (UINT8) (sizeof (ACPI_HID_DEVICE_PATH)), \=0D + (UINT8) ((sizeof (ACPI_HID_DEVICE_PATH)) >> 8) \=0D + }, \=0D + }, \=0D + EISA_PNP_ID((PnpId)), \=0D + 0 \=0D + }=0D +=0D +#define gPciIsaBridge \=0D + PCI_DEVICE_PATH_NODE(0, 0x1f)=0D +=0D +#define gP2PBridge \=0D + PCI_DEVICE_PATH_NODE(0, 0x1e)=0D +=0D +#define gPnpPs2Keyboard \=0D + PNPID_DEVICE_PATH_NODE(0x0303)=0D +=0D +#define gPnp16550ComPort \=0D + PNPID_DEVICE_PATH_NODE(0x0501)=0D +=0D +#define gUart \=0D + { \=0D + { \=0D + MESSAGING_DEVICE_PATH, \=0D + MSG_UART_DP, \=0D + { \=0D + (UINT8) (sizeof (UART_DEVICE_PATH)), \=0D + (UINT8) ((sizeof (UART_DEVICE_PATH)) >> 8) \=0D + } \=0D + }, \=0D + 0, \=0D + 115200, \=0D + 8, \=0D + 1, \=0D + 1 \=0D + }=0D +=0D +#define gPcAnsiTerminal \=0D + { \=0D + { \=0D + MESSAGING_DEVICE_PATH, \=0D + MSG_VENDOR_DP, \=0D + { \=0D + (UINT8) (sizeof (VENDOR_DEVICE_PATH)), \=0D + (UINT8) ((sizeof (VENDOR_DEVICE_PATH)) >> 8) \=0D + } \=0D + }, \=0D + DEVICE_PATH_MESSAGING_PC_ANSI \=0D + }=0D +=0D +#define gEndEntire \=0D + { \=0D + END_DEVICE_PATH_TYPE, \=0D + END_ENTIRE_DEVICE_PATH_SUBTYPE, \=0D + { \=0D + END_DEVICE_PATH_LENGTH, \=0D + 0 \=0D + } \=0D + }=0D +=0D +#define PCI_CLASS_SCC 0x07=0D +#define PCI_SUBCLASS_SERIAL 0x00=0D +#define PCI_IF_16550 0x02=0D +#define IS_PCI_16550SERIAL(_p) IS_CLASS3 (_p, PCI_CLASS_SCC, PCI= _SUBCLASS_SERIAL, PCI_IF_16550)=0D +#define IS_PCI_ISA_PDECODE(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI= _CLASS_BRIDGE_ISA_PDECODE, 0)=0D +=0D +typedef struct {=0D + EFI_DEVICE_PATH_PROTOCOL *DevicePath;=0D + UINTN ConnectType;=0D +} PLATFORM_CONSOLE_CONNECT_ENTRY;=0D +=0D +#define CONSOLE_OUT BIT0=0D +#define CONSOLE_IN BIT1=0D +#define STD_ERROR BIT2=0D +extern PLATFORM_CONSOLE_CONNECT_ENTRY gPlatformConsole[];=0D +=0D +//=0D +// Platform BDS Functions=0D +//=0D +=0D +VOID=0D +PlatformInitializeConsole (=0D + IN PLATFORM_CONSOLE_CONNECT_ENTRY *PlatformConsole=0D + );=0D +=0D +/**=0D + Loads and boots UEFI Linux via the FwCfg interface.=0D +=0D + @retval EFI_NOT_FOUND - The Linux kernel was not found=0D +=0D +**/=0D +EFI_STATUS=0D +TryRunningQemuKernel (=0D + VOID=0D + );=0D +=0D +#endif // _PLATFORM_SPECIFIC_BDS_PLATFORM_H_=0D diff --git a/OvmfPkg/Bhyve/Library/PlatformBootManagerLib/PlatformBootManag= erLib.inf b/OvmfPkg/Bhyve/Library/PlatformBootManagerLib/PlatformBootManage= rLib.inf new file mode 100644 index 0000000000..105123b5e2 --- /dev/null +++ b/OvmfPkg/Bhyve/Library/PlatformBootManagerLib/PlatformBootManagerLib.i= nf @@ -0,0 +1,75 @@ +## @file=0D +# Platform BDS customizations library.=0D +#=0D +# Copyright (c) 2020, Rebecca Cran <rebecca@...>=0D +# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>= =0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010005=0D + BASE_NAME =3D PlatformBootManagerLib=0D + FILE_GUID =3D b0de5f0d-f676-42da-8d00-86997ee0dbb4= =0D + MODULE_TYPE =3D DXE_DRIVER=0D + VERSION_STRING =3D 1.0=0D + LIBRARY_CLASS =3D PlatformBootManagerLib|DXE_DRIVER=0D +=0D +#=0D +# The following information is for reference only and not required by the = build tools.=0D +#=0D +# VALID_ARCHITECTURES =3D IA32 X64 EBC=0D +#=0D +=0D +[Sources]=0D + BdsPlatform.c=0D + PlatformData.c=0D + BdsPlatform.h=0D +=0D +[Packages]=0D + MdePkg/MdePkg.dec=0D + MdeModulePkg/MdeModulePkg.dec=0D + SourceLevelDebugPkg/SourceLevelDebugPkg.dec=0D + OvmfPkg/OvmfPkg.dec=0D + SecurityPkg/SecurityPkg.dec=0D + ShellPkg/ShellPkg.dec=0D +=0D +[LibraryClasses]=0D + BaseLib=0D + MemoryAllocationLib=0D + UefiBootServicesTableLib=0D + BaseMemoryLib=0D + DebugLib=0D + PcdLib=0D + UefiBootManagerLib=0D + BootLogoLib=0D + DevicePathLib=0D + PciLib=0D + NvVarsFileLib=0D + ReportStatusCodeLib=0D + UefiLib=0D + PlatformBmPrintScLib=0D + Tcg2PhysicalPresenceLib=0D +=0D +[Pcd]=0D + gUefiOvmfPkgTokenSpaceGuid.PcdEmuVariableEvent=0D + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashVariablesEnable=0D + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfHostBridgePciDevId=0D + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut=0D +=0D +[Pcd.IA32, Pcd.X64]=0D + gEfiMdePkgTokenSpaceGuid.PcdFSBClock=0D +=0D +[Protocols]=0D + gEfiDecompressProtocolGuid=0D + gEfiPciRootBridgeIoProtocolGuid=0D + gEfiS3SaveStateProtocolGuid # PROTOCOL SOMETIMES_CONSU= MED=0D + gEfiDxeSmmReadyToLockProtocolGuid # PROTOCOL SOMETIMES_PRODU= CED=0D + gEfiLoadedImageProtocolGuid # PROTOCOL SOMETIMES_PRODU= CED=0D + gEfiFirmwareVolume2ProtocolGuid # PROTOCOL SOMETIMES_CONSU= MED=0D +=0D +[Guids]=0D + gEfiEndOfDxeEventGroupGuid=0D + gRootBridgesConnectedEventGroupGuid=0D + gUefiShellFileGuid=0D diff --git a/OvmfPkg/Bhyve/Library/PlatformBootManagerLib/PlatformData.c b/= OvmfPkg/Bhyve/Library/PlatformBootManagerLib/PlatformData.c new file mode 100644 index 0000000000..73674d536d --- /dev/null +++ b/OvmfPkg/Bhyve/Library/PlatformBootManagerLib/PlatformData.c @@ -0,0 +1,171 @@ +/** @file=0D + Defined the platform specific device path which will be used by=0D + platform Bbd to perform the platform policy connect.=0D +=0D + Copyright (c) 2020, Rebecca Cran <rebecca@...>=0D + Copyright (c) 2004 - 2017, Intel Corporation. All rights reserved.<BR>=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include "BdsPlatform.h"=0D +#include <Guid/QemuRamfb.h>=0D +=0D +//=0D +// Debug Agent UART Device Path structure=0D +//=0D +#pragma pack(1)=0D +typedef struct {=0D + VENDOR_DEVICE_PATH VendorHardware;=0D + UART_DEVICE_PATH Uart;=0D + VENDOR_DEVICE_PATH TerminalType;=0D + EFI_DEVICE_PATH_PROTOCOL End;=0D +} VENDOR_UART_DEVICE_PATH;=0D +#pragma pack()=0D +=0D +//=0D +// USB Keyboard Device Path structure=0D +//=0D +#pragma pack (1)=0D +typedef struct {=0D + USB_CLASS_DEVICE_PATH Keyboard;=0D + EFI_DEVICE_PATH_PROTOCOL End;=0D +} USB_KEYBOARD_DEVICE_PATH;=0D +#pragma pack ()=0D +=0D +//=0D +// QemuRamfb Device Path structure=0D +//=0D +#pragma pack (1)=0D +typedef struct {=0D + VENDOR_DEVICE_PATH Vendor;=0D + ACPI_ADR_DEVICE_PATH AcpiAdr;=0D + EFI_DEVICE_PATH_PROTOCOL End;=0D +} VENDOR_RAMFB_DEVICE_PATH;=0D +#pragma pack ()=0D +=0D +ACPI_HID_DEVICE_PATH gPnpPs2KeyboardDeviceNode =3D gPnpPs2Keyboard;= =0D +ACPI_HID_DEVICE_PATH gPnp16550ComPortDeviceNode =3D gPnp16550ComPort= ;=0D +UART_DEVICE_PATH gUartDeviceNode =3D gUart;=0D +VENDOR_DEVICE_PATH gTerminalTypeDeviceNode =3D gPcAnsiTerminal;= =0D +=0D +//=0D +// Platform specific keyboard device path=0D +//=0D +=0D +=0D +//=0D +// Debug Agent UART Device Path=0D +//=0D +VENDOR_UART_DEVICE_PATH gDebugAgentUartDevicePath =3D {=0D + {=0D + {=0D + HARDWARE_DEVICE_PATH,=0D + HW_VENDOR_DP,=0D + {=0D + (UINT8) (sizeof (VENDOR_DEVICE_PATH)),=0D + (UINT8) ((sizeof (VENDOR_DEVICE_PATH)) >> 8)=0D + }=0D + },=0D + EFI_DEBUG_AGENT_GUID,=0D + },=0D + {=0D + {=0D + MESSAGING_DEVICE_PATH,=0D + MSG_UART_DP,=0D + {=0D + (UINT8) (sizeof (UART_DEVICE_PATH)),=0D + (UINT8) ((sizeof (UART_DEVICE_PATH)) >> 8)=0D + }=0D + },=0D + 0, // Reserved=0D + 0, // BaudRate - Default=0D + 0, // DataBits - Default=0D + 0, // Parity - Default=0D + 0, // StopBits - Default=0D + },=0D + gPcAnsiTerminal,=0D + gEndEntire=0D +};=0D +=0D +STATIC USB_KEYBOARD_DEVICE_PATH gUsbKeyboardDevicePath =3D {=0D + {=0D + {=0D + MESSAGING_DEVICE_PATH,=0D + MSG_USB_CLASS_DP,=0D + {=0D + (UINT8)sizeof (USB_CLASS_DEVICE_PATH),=0D + (UINT8)(sizeof (USB_CLASS_DEVICE_PATH) >> 8)=0D + }=0D + },=0D + 0xFFFF, // VendorId: any=0D + 0xFFFF, // ProductId: any=0D + 3, // DeviceClass: HID=0D + 1, // DeviceSubClass: boot=0D + 1 // DeviceProtocol: keyboard=0D + },=0D + gEndEntire=0D +};=0D +=0D +STATIC VENDOR_RAMFB_DEVICE_PATH gQemuRamfbDevicePath =3D {=0D + {=0D + {=0D + HARDWARE_DEVICE_PATH,=0D + HW_VENDOR_DP,=0D + {=0D + (UINT8) (sizeof (VENDOR_DEVICE_PATH)),=0D + (UINT8) ((sizeof (VENDOR_DEVICE_PATH)) >> 8)=0D + }=0D + },=0D + QEMU_RAMFB_GUID,=0D + },=0D + {=0D + {=0D + ACPI_DEVICE_PATH,=0D + ACPI_ADR_DP,=0D + {=0D + (UINT8) (sizeof (ACPI_ADR_DEVICE_PATH)),=0D + (UINT8) ((sizeof (ACPI_ADR_DEVICE_PATH)) >> 8)=0D + }=0D + },=0D + ACPI_DISPLAY_ADR (=0D + 1, // DeviceIdScheme=0D + 0, // HeadId=0D + 0, // NonVgaOutput=0D + 1, // BiosCanDetect=0D + 0, // VendorInfo=0D + ACPI_ADR_DISPLAY_TYPE_EXTERNAL_DIGITAL, // Type=0D + 0, // Port=0D + 0 // Index=0D + ),=0D + },=0D + gEndEntire=0D +};=0D +=0D +//=0D +// Predefined platform default console device path=0D +//=0D +PLATFORM_CONSOLE_CONNECT_ENTRY gPlatformConsole[] =3D {=0D + {=0D + (EFI_DEVICE_PATH_PROTOCOL *) &gDebugAgentUartDevicePath,=0D + (CONSOLE_OUT | CONSOLE_IN | STD_ERROR)=0D + },=0D + {=0D + (EFI_DEVICE_PATH_PROTOCOL *)&gUsbKeyboardDevicePath,=0D + CONSOLE_IN=0D + },=0D + {=0D + (EFI_DEVICE_PATH_PROTOCOL *)&gQemuRamfbDevicePath,=0D + CONSOLE_OUT=0D + },=0D + {=0D + NULL,=0D + 0=0D + }=0D +};=0D +=0D +//=0D +// Predefined platform connect sequence=0D +//=0D +EFI_DEVICE_PATH_PROTOCOL *gPlatformConnectSequence[] =3D { NULL };=0D +=0D diff --git a/OvmfPkg/Bhyve/License.txt b/OvmfPkg/Bhyve/License.txt new file mode 100644 index 0000000000..2930e5372a --- /dev/null +++ b/OvmfPkg/Bhyve/License.txt @@ -0,0 +1,68 @@ +Copyright (c) 2020, Rebecca Cran <rebecca@...>=0D +Copyright (c) 2004 - 2019, Intel Corporation. All rights reserved.<BR>=0D +Copyright (C) 2018, Red Hat, Inc.=0D +Copyright (c) 2017, Advanced Micro Devices. All rights reserved.<BR>=0D +Copyright (C) 2016, Red Hat, Inc.=0D +(C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>=0D +Copyright (c) 2015 Nahanni Systems=0D +Copyright (C) 2015, Red Hat, Inc.=0D +Copyright (C) 2014, Red Hat, Inc.=0D +Copyright (c) 2014, Pluribus Networks, Inc.=0D +Copyright (C) 2013, Red Hat, Inc.=0D +Copyright (c) 2012, 2013, Red Hat, Inc.=0D +Copyright (c) 2011, Bei Guan <gbtju85@...>=0D +Copyright (c) 2011, Andrei Warkentin <andreiw@...>=0D +Portions copyright (c) 2011, Apple Inc. All rights reserved.=0D +Portions copyright (c) 2010,Apple Inc. All rights reserved.<BR>=0D +=0D +=0D +SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +Redistribution and use in source and binary forms, with or without=0D +modification, are permitted provided that the following conditions are met= :=0D +=0D +1. Redistributions of source code must retain the above copyright notice,= =0D + this list of conditions and the following disclaimer.=0D +=0D +2. Redistributions in binary form must reproduce the above copyright notic= e,=0D + this list of conditions and the following disclaimer in the documentati= on=0D + and/or other materials provided with the distribution.=0D +=0D +Subject to the terms and conditions of this license, each copyright holder= =0D +and contributor hereby grants to those receiving rights under this license= =0D +a perpetual, worldwide, non-exclusive, no-charge, royalty-free, irrevocabl= e=0D +(except for failure to satisfy the conditions of this license) patent=0D +license to make, have made, use, offer to sell, sell, import, and otherwis= e=0D +transfer this software, where such license applies only to those patent=0D +claims, already acquired or hereafter acquired, licensable by such copyrig= ht=0D +holder or contributor that are necessarily infringed by:=0D +=0D +(a) their Contribution(s) (the licensed copyrights of copyright holders an= d=0D + non-copyrightable additions of contributors, in source or binary form)= =0D + alone; or=0D +=0D +(b) combination of their Contribution(s) with the work of authorship to=0D + which such Contribution(s) was added by such copyright holder or=0D + contributor, if, at the time the Contribution is added, such addition= =0D + causes such combination to be necessarily infringed. The patent licens= e=0D + shall not apply to any other combinations which include the=0D + Contribution.=0D +=0D +Except as expressly stated above, no rights or licenses from any copyright= =0D +holder or contributor is granted under this license, whether expressly, by= =0D +implication, estoppel or otherwise.=0D +=0D +DISCLAIMER=0D +=0D +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS= "=0D +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE= =0D +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE= =0D +ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE= =0D +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR=0D +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF=0D +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS=0D +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN=0D +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)=0D +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE= =0D +POSSIBILITY OF SUCH DAMAGE.=0D +=0D diff --git a/OvmfPkg/Bhyve/PlatformPei/AmdSev.c b/OvmfPkg/Bhyve/PlatformPei= /AmdSev.c new file mode 100644 index 0000000000..e484f4b311 --- /dev/null +++ b/OvmfPkg/Bhyve/PlatformPei/AmdSev.c @@ -0,0 +1,106 @@ +/**@file=0D + Initialize Secure Encrypted Virtualization (SEV) support=0D +=0D + Copyright (c) 2017, Advanced Micro Devices. All rights reserved.<BR>=0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +//=0D +// The package level header files this module uses=0D +//=0D +#include <IndustryStandard/Q35MchIch9.h>=0D +#include <Library/DebugLib.h>=0D +#include <Library/HobLib.h>=0D +#include <Library/MemEncryptSevLib.h>=0D +#include <Library/PcdLib.h>=0D +#include <PiPei.h>=0D +#include <Register/Amd/Cpuid.h>=0D +#include <Register/Cpuid.h>=0D +#include <Register/Intel/SmramSaveStateMap.h>=0D +=0D +#include "Platform.h"=0D +=0D +/**=0D +=0D + Function checks if SEV support is available, if present then it sets=0D + the dynamic PcdPteMemoryEncryptionAddressOrMask with memory encryption m= ask.=0D +=0D + **/=0D +VOID=0D +AmdSevInitialize (=0D + VOID=0D + )=0D +{=0D + CPUID_MEMORY_ENCRYPTION_INFO_EBX Ebx;=0D + UINT64 EncryptionMask;=0D + RETURN_STATUS PcdStatus;=0D +=0D + //=0D + // Check if SEV is enabled=0D + //=0D + if (!MemEncryptSevIsEnabled ()) {=0D + return;=0D + }=0D +=0D + //=0D + // CPUID Fn8000_001F[EBX] Bit 0:5 (memory encryption bit position)=0D + //=0D + AsmCpuid (CPUID_MEMORY_ENCRYPTION_INFO, NULL, &Ebx.Uint32, NULL, NULL);= =0D + EncryptionMask =3D LShiftU64 (1, Ebx.Bits.PtePosBits);=0D +=0D + //=0D + // Set Memory Encryption Mask PCD=0D + //=0D + PcdStatus =3D PcdSet64S (PcdPteMemoryEncryptionAddressOrMask, Encryption= Mask);=0D + ASSERT_RETURN_ERROR (PcdStatus);=0D +=0D + DEBUG ((DEBUG_INFO, "SEV is enabled (mask 0x%lx)\n", EncryptionMask));=0D +=0D + //=0D + // Set Pcd to Deny the execution of option ROM when security=0D + // violation.=0D + //=0D + PcdStatus =3D PcdSet32S (PcdOptionRomImageVerificationPolicy, 0x4);=0D + ASSERT_RETURN_ERROR (PcdStatus);=0D +=0D + //=0D + // When SMM is required, cover the pages containing the initial SMRAM Sa= ve=0D + // State Map with a memory allocation HOB:=0D + //=0D + // There's going to be a time interval between our decrypting those page= s for=0D + // SMBASE relocation and re-encrypting the same pages after SMBASE=0D + // relocation. We shall ensure that the DXE phase stay away from those p= ages=0D + // until after re-encryption, in order to prevent an information leak to= the=0D + // hypervisor.=0D + //=0D + if (FeaturePcdGet (PcdSmmSmramRequire) && (mBootMode !=3D BOOT_ON_S3_RES= UME)) {=0D + RETURN_STATUS LocateMapStatus;=0D + UINTN MapPagesBase;=0D + UINTN MapPagesCount;=0D +=0D + LocateMapStatus =3D MemEncryptSevLocateInitialSmramSaveStateMapPages (= =0D + &MapPagesBase,=0D + &MapPagesCount=0D + );=0D + ASSERT_RETURN_ERROR (LocateMapStatus);=0D +=0D + if (mQ35SmramAtDefaultSmbase) {=0D + //=0D + // The initial SMRAM Save State Map has been covered as part of a la= rger=0D + // reserved memory allocation in InitializeRamRegions().=0D + //=0D + ASSERT (SMM_DEFAULT_SMBASE <=3D MapPagesBase);=0D + ASSERT (=0D + (MapPagesBase + EFI_PAGES_TO_SIZE (MapPagesCount) <=3D=0D + SMM_DEFAULT_SMBASE + MCH_DEFAULT_SMBASE_SIZE)=0D + );=0D + } else {=0D + BuildMemoryAllocationHob (=0D + MapPagesBase, // BaseAddress=0D + EFI_PAGES_TO_SIZE (MapPagesCount), // Length=0D + EfiBootServicesData // MemoryType=0D + );=0D + }=0D + }=0D +}=0D diff --git a/OvmfPkg/Bhyve/PlatformPei/ClearCache.c b/OvmfPkg/Bhyve/Platfor= mPei/ClearCache.c new file mode 100644 index 0000000000..5c538c59e0 --- /dev/null +++ b/OvmfPkg/Bhyve/PlatformPei/ClearCache.c @@ -0,0 +1,111 @@ +/**@file=0D + Install a callback to clear cache on all processors.=0D + This is for conformance with the TCG "Platform Reset Attack Mitigation=0D + Specification". Because clearing the CPU caches at boot doesn't impact=0D + performance significantly, do it unconditionally, for simplicity's=0D + sake.=0D +=0D + Copyright (C) 2018, Red Hat, Inc.=0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include <Library/CacheMaintenanceLib.h>=0D +#include <Library/DebugLib.h>=0D +#include <Library/PeiServicesLib.h>=0D +#include <Ppi/MpServices.h>=0D +=0D +#include "Platform.h"=0D +=0D +/**=0D + Invalidate data & instruction caches.=0D + All APs execute this function in parallel. The BSP executes the function= =0D + separately.=0D +=0D + @param[in,out] WorkSpace Pointer to the input/output argument workspace= =0D + shared by all processors.=0D +**/=0D +STATIC=0D +VOID=0D +EFIAPI=0D +ClearCache (=0D + IN OUT VOID *WorkSpace=0D + )=0D +{=0D + WriteBackInvalidateDataCache ();=0D + InvalidateInstructionCache ();=0D +}=0D +=0D +/**=0D + Notification function called when EFI_PEI_MP_SERVICES_PPI becomes availa= ble.=0D +=0D + @param[in] PeiServices Indirect reference to the PEI Services Table= .=0D + @param[in] NotifyDescriptor Address of the notification descriptor data= =0D + structure.=0D + @param[in] Ppi Address of the PPI that was installed.=0D +=0D + @return Status of the notification. The status code returned from this= =0D + function is ignored.=0D +**/=0D +STATIC=0D +EFI_STATUS=0D +EFIAPI=0D +ClearCacheOnMpServicesAvailable (=0D + IN EFI_PEI_SERVICES **PeiServices,=0D + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,=0D + IN VOID *Ppi=0D + )=0D +{=0D + EFI_PEI_MP_SERVICES_PPI *MpServices;=0D + EFI_STATUS Status;=0D +=0D + DEBUG ((DEBUG_INFO, "%a: %a\n", gEfiCallerBaseName, __FUNCTION__));=0D +=0D + //=0D + // Clear cache on all the APs in parallel.=0D + //=0D + MpServices =3D Ppi;=0D + Status =3D MpServices->StartupAllAPs (=0D + (CONST EFI_PEI_SERVICES **)PeiServices,=0D + MpServices,=0D + ClearCache, // Procedure=0D + FALSE, // SingleThread=0D + 0, // TimeoutInMicroSeconds: in= f.=0D + NULL // ProcedureArgument=0D + );=0D + if (EFI_ERROR (Status) && Status !=3D EFI_NOT_STARTED) {=0D + DEBUG ((DEBUG_ERROR, "%a: StartupAllAps(): %r\n", __FUNCTION__, Status= ));=0D + return Status;=0D + }=0D +=0D + //=0D + // Now clear cache on the BSP too.=0D + //=0D + ClearCache (NULL);=0D + return EFI_SUCCESS;=0D +}=0D +=0D +//=0D +// Notification object for registering the callback, for when=0D +// EFI_PEI_MP_SERVICES_PPI becomes available.=0D +//=0D +STATIC CONST EFI_PEI_NOTIFY_DESCRIPTOR mMpServicesNotify =3D {=0D + EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | // Flags=0D + EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,=0D + &gEfiPeiMpServicesPpiGuid, // Guid=0D + ClearCacheOnMpServicesAvailable // Notify=0D +};=0D +=0D +VOID=0D +InstallClearCacheCallback (=0D + VOID=0D + )=0D +{=0D + EFI_STATUS Status;=0D +=0D + Status =3D PeiServicesNotifyPpi (&mMpServicesNotify);=0D + if (EFI_ERROR (Status)) {=0D + DEBUG ((DEBUG_ERROR, "%a: failed to set up MP Services callback: %r\n"= ,=0D + __FUNCTION__, Status));=0D + }=0D +}=0D diff --git a/OvmfPkg/Bhyve/PlatformPei/Cmos.c b/OvmfPkg/Bhyve/PlatformPei/C= mos.c new file mode 100644 index 0000000000..9b34e10b17 --- /dev/null +++ b/OvmfPkg/Bhyve/PlatformPei/Cmos.c @@ -0,0 +1,58 @@ +/** @file=0D + PC/AT CMOS access routines=0D +=0D + Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +=0D +#include "Cmos.h"=0D +#include "Library/IoLib.h"=0D +=0D +/**=0D + Reads 8-bits of CMOS data.=0D +=0D + Reads the 8-bits of CMOS data at the location specified by Index.=0D + The 8-bit read value is returned.=0D +=0D + @param Index The CMOS location to read.=0D +=0D + @return The value read.=0D +=0D +**/=0D +UINT8=0D +EFIAPI=0D +CmosRead8 (=0D + IN UINTN Index=0D + )=0D +{=0D + IoWrite8 (0x70, (UINT8) Index);=0D + return IoRead8 (0x71);=0D +}=0D +=0D +=0D +/**=0D + Writes 8-bits of CMOS data.=0D +=0D + Writes 8-bits of CMOS data to the location specified by Index=0D + with the value specified by Value and returns Value.=0D +=0D + @param Index The CMOS location to write.=0D + @param Value The value to write to CMOS.=0D +=0D + @return The value written to CMOS.=0D +=0D +**/=0D +UINT8=0D +EFIAPI=0D +CmosWrite8 (=0D + IN UINTN Index,=0D + IN UINT8 Value=0D + )=0D +{=0D + IoWrite8 (0x70, (UINT8) Index);=0D + IoWrite8 (0x71, Value);=0D + return Value;=0D +}=0D +=0D diff --git a/OvmfPkg/Bhyve/PlatformPei/Cmos.h b/OvmfPkg/Bhyve/PlatformPei/C= mos.h new file mode 100644 index 0000000000..3cd98799a3 --- /dev/null +++ b/OvmfPkg/Bhyve/PlatformPei/Cmos.h @@ -0,0 +1,50 @@ +/** @file=0D + PC/AT CMOS access routines=0D +=0D + Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#ifndef __CMOS_H__=0D +#define __CMOS_H__=0D +=0D +/**=0D + Reads 8-bits of CMOS data.=0D +=0D + Reads the 8-bits of CMOS data at the location specified by Index.=0D + The 8-bit read value is returned.=0D +=0D + @param Index The CMOS location to read.=0D +=0D + @return The value read.=0D +=0D +**/=0D +UINT8=0D +EFIAPI=0D +CmosRead8 (=0D + IN UINTN Index=0D + );=0D +=0D +/**=0D + Writes 8-bits of CMOS data.=0D +=0D + Writes 8-bits of CMOS data to the location specified by Index=0D + with the value specified by Value and returns Value.=0D +=0D + @param Index The CMOS location to write.=0D + @param Value The value to write to CMOS.=0D +=0D + @return The value written to CMOS.=0D +=0D +**/=0D +UINT8=0D +EFIAPI=0D +CmosWrite8 (=0D + IN UINTN Index,=0D + IN UINT8 Value=0D + );=0D +=0D +=0D +#endif=0D +=0D diff --git a/OvmfPkg/Bhyve/PlatformPei/FeatureControl.c b/OvmfPkg/Bhyve/Pla= tformPei/FeatureControl.c new file mode 100644 index 0000000000..40d9ebdbe6 --- /dev/null +++ b/OvmfPkg/Bhyve/PlatformPei/FeatureControl.c @@ -0,0 +1,21 @@ +/**@file=0D + Install a callback when necessary for setting the Feature Control MSR on= all=0D + processors.=0D +=0D + Copyright (C) 2020, Rebecca Cran <rebecca@...>=0D + Copyright (C) 2016, Red Hat, Inc.=0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include "Platform.h"=0D +=0D +VOID=0D +InstallFeatureControlCallback (=0D + VOID=0D + )=0D +{=0D + //=0D + // Nothing to do.=0D + //=0D +}=0D diff --git a/OvmfPkg/Bhyve/PlatformPei/Fv.c b/OvmfPkg/Bhyve/PlatformPei/Fv.c new file mode 100644 index 0000000000..ee4ecab615 --- /dev/null +++ b/OvmfPkg/Bhyve/PlatformPei/Fv.c @@ -0,0 +1,94 @@ +/** @file=0D + Build FV related hobs for platform.=0D +=0D + Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include "PiPei.h"=0D +#include "Platform.h"=0D +#include <Library/DebugLib.h>=0D +#include <Library/HobLib.h>=0D +#include <Library/PeiServicesLib.h>=0D +#include <Library/PcdLib.h>=0D +=0D +=0D +/**=0D + Publish PEI & DXE (Decompressed) Memory based FVs to let PEI=0D + and DXE know about them.=0D +=0D + @retval EFI_SUCCESS Platform PEI FVs were initialized successfully.=0D +=0D +**/=0D +EFI_STATUS=0D +PeiFvInitialization (=0D + VOID=0D + )=0D +{=0D + BOOLEAN SecureS3Needed;=0D +=0D + DEBUG ((DEBUG_INFO, "Platform PEI Firmware Volume Initialization\n"));=0D +=0D + //=0D + // Create a memory allocation HOB for the PEI FV.=0D + //=0D + // Allocate as ACPI NVS is S3 is supported=0D + //=0D + BuildMemoryAllocationHob (=0D + PcdGet32 (PcdOvmfPeiMemFvBase),=0D + PcdGet32 (PcdOvmfPeiMemFvSize),=0D + mS3Supported ? EfiACPIMemoryNVS : EfiBootServicesData=0D + );=0D +=0D + //=0D + // Let DXE know about the DXE FV=0D + //=0D + BuildFvHob (PcdGet32 (PcdOvmfDxeMemFvBase), PcdGet32 (PcdOvmfDxeMemFvSiz= e));=0D +=0D + SecureS3Needed =3D mS3Supported && FeaturePcdGet (PcdSmmSmramRequire);=0D +=0D + //=0D + // Create a memory allocation HOB for the DXE FV.=0D + //=0D + // If "secure" S3 is needed, then SEC will decompress both PEI and DXE=0D + // firmware volumes at S3 resume too, hence we need to keep away the OS = from=0D + // DXEFV as well. Otherwise we only need to keep away DXE itself from th= e=0D + // DXEFV area.=0D + //=0D + BuildMemoryAllocationHob (=0D + PcdGet32 (PcdOvmfDxeMemFvBase),=0D + PcdGet32 (PcdOvmfDxeMemFvSize),=0D + SecureS3Needed ? EfiACPIMemoryNVS : EfiBootServicesData=0D + );=0D +=0D + //=0D + // Additionally, said decompression will use temporary memory above the = end=0D + // of DXEFV, so let's keep away the OS from there too.=0D + //=0D + if (SecureS3Needed) {=0D + UINT32 DxeMemFvEnd;=0D +=0D + DxeMemFvEnd =3D PcdGet32 (PcdOvmfDxeMemFvBase) +=0D + PcdGet32 (PcdOvmfDxeMemFvSize);=0D + BuildMemoryAllocationHob (=0D + DxeMemFvEnd,=0D + PcdGet32 (PcdOvmfDecompressionScratchEnd) - DxeMemFvEnd,=0D + EfiACPIMemoryNVS=0D + );=0D + }=0D +=0D + //=0D + // Let PEI know about the DXE FV so it can find the DXE Core=0D + //=0D + PeiServicesInstallFvInfoPpi (=0D + NULL,=0D + (VOID *)(UINTN) PcdGet32 (PcdOvmfDxeMemFvBase),=0D + PcdGet32 (PcdOvmfDxeMemFvSize),=0D + NULL,=0D + NULL=0D + );=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D diff --git a/OvmfPkg/Bhyve/PlatformPei/MemDetect.c b/OvmfPkg/Bhyve/Platform= Pei/MemDetect.c new file mode 100644 index 0000000000..1b556be69c --- /dev/null +++ b/OvmfPkg/Bhyve/PlatformPei/MemDetect.c @@ -0,0 +1,627 @@ +/**@file=0D + Memory Detection for Virtual Machines.=0D +=0D + Copyright (c) 2020, Rebecca Cran <rebecca@...>=0D + Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>=0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +Module Name:=0D +=0D + MemDetect.c=0D +=0D +**/=0D +=0D +//=0D +// The package level header files this module uses=0D +//=0D +#include <IndustryStandard/E820.h>=0D +#include <IndustryStandard/Q35MchIch9.h>=0D +#include <PiPei.h>=0D +=0D +//=0D +// The Library classes this module consumes=0D +//=0D +#include <Library/BaseLib.h>=0D +#include <Library/BaseMemoryLib.h>=0D +#include <Library/DebugLib.h>=0D +#include <Library/HobLib.h>=0D +#include <Library/IoLib.h>=0D +#include <Library/PcdLib.h>=0D +#include <Library/PciLib.h>=0D +#include <Library/PeimEntryPoint.h>=0D +#include <Library/ResourcePublicationLib.h>=0D +#include <Library/MtrrLib.h>=0D +=0D +#include "Platform.h"=0D +#include "Cmos.h"=0D +=0D +UINT8 mPhysMemAddressWidth;=0D +=0D +STATIC UINT32 mS3AcpiReservedMemoryBase;=0D +STATIC UINT32 mS3AcpiReservedMemorySize;=0D +=0D +STATIC UINT16 mQ35TsegMbytes;=0D +=0D +BOOLEAN mQ35SmramAtDefaultSmbase =3D FALSE;=0D +=0D +VOID=0D +Q35TsegMbytesInitialization (=0D + VOID=0D + )=0D +{=0D + UINT16 ExtendedTsegMbytes;=0D + RETURN_STATUS PcdStatus;=0D +=0D + if (mHostBridgeDevId !=3D INTEL_Q35_MCH_DEVICE_ID) {=0D + DEBUG ((=0D + DEBUG_ERROR,=0D + "%a: no TSEG (SMRAM) on host bridge DID=3D0x%04x; "=0D + "only DID=3D0x%04x (Q35) is supported\n",=0D + __FUNCTION__,=0D + mHostBridgeDevId,=0D + INTEL_Q35_MCH_DEVICE_ID=0D + ));=0D + ASSERT (FALSE);=0D + CpuDeadLoop ();=0D + }=0D +=0D + //=0D + // Check if QEMU offers an extended TSEG.=0D + //=0D + // This can be seen from writing MCH_EXT_TSEG_MB_QUERY to the MCH_EXT_TS= EG_MB=0D + // register, and reading back the register.=0D + //=0D + // On a QEMU machine type that does not offer an extended TSEG, the init= ial=0D + // write overwrites whatever value a malicious guest OS may have placed = in=0D + // the (unimplemented) register, before entering S3 or rebooting.=0D + // Subsequently, the read returns MCH_EXT_TSEG_MB_QUERY unchanged.=0D + //=0D + // On a QEMU machine type that offers an extended TSEG, the initial writ= e=0D + // triggers an update to the register. Subsequently, the value read back= =0D + // (which is guaranteed to differ from MCH_EXT_TSEG_MB_QUERY) tells us t= he=0D + // number of megabytes.=0D + //=0D + PciWrite16 (DRAMC_REGISTER_Q35 (MCH_EXT_TSEG_MB), MCH_EXT_TSEG_MB_QUERY)= ;=0D + ExtendedTsegMbytes =3D PciRead16 (DRAMC_REGISTER_Q35 (MCH_EXT_TSEG_MB));= =0D + if (ExtendedTsegMbytes =3D=3D MCH_EXT_TSEG_MB_QUERY) {=0D + mQ35TsegMbytes =3D PcdGet16 (PcdQ35TsegMbytes);=0D + return;=0D + }=0D +=0D + DEBUG ((=0D + DEBUG_INFO,=0D + "%a: QEMU offers an extended TSEG (%d MB)\n",=0D + __FUNCTION__,=0D + ExtendedTsegMbytes=0D + ));=0D + PcdStatus =3D PcdSet16S (PcdQ35TsegMbytes, ExtendedTsegMbytes);=0D + ASSERT_RETURN_ERROR (PcdStatus);=0D + mQ35TsegMbytes =3D ExtendedTsegMbytes;=0D +}=0D +=0D +=0D +UINT32=0D +GetSystemMemorySizeBelow4gb (=0D + VOID=0D + )=0D +{=0D + UINT8 Cmos0x34;=0D + UINT8 Cmos0x35;=0D +=0D + //=0D + // CMOS 0x34/0x35 specifies the system memory above 16 MB.=0D + // * CMOS(0x35) is the high byte=0D + // * CMOS(0x34) is the low byte=0D + // * The size is specified in 64kb chunks=0D + // * Since this is memory above 16MB, the 16MB must be added=0D + // into the calculation to get the total memory size.=0D + //=0D +=0D + Cmos0x34 =3D (UINT8) CmosRead8 (0x34);=0D + Cmos0x35 =3D (UINT8) CmosRead8 (0x35);=0D +=0D + return (UINT32) (((UINTN)((Cmos0x35 << 8) + Cmos0x34) << 16) + SIZE_16MB= );=0D +}=0D +=0D +=0D +STATIC=0D +UINT64=0D +GetSystemMemorySizeAbove4gb (=0D + )=0D +{=0D + UINT32 Size;=0D + UINTN CmosIndex;=0D +=0D + //=0D + // CMOS 0x5b-0x5d specifies the system memory above 4GB MB.=0D + // * CMOS(0x5d) is the most significant size byte=0D + // * CMOS(0x5c) is the middle size byte=0D + // * CMOS(0x5b) is the least significant size byte=0D + // * The size is specified in 64kb chunks=0D + //=0D +=0D + Size =3D 0;=0D + for (CmosIndex =3D 0x5d; CmosIndex >=3D 0x5b; CmosIndex--) {=0D + Size =3D (UINT32) (Size << 8) + (UINT32) CmosRead8 (CmosIndex);=0D + }=0D +=0D + return LShiftU64 (Size, 16);=0D +}=0D +=0D +=0D +/**=0D + Return the highest address that DXE could possibly use, plus one.=0D +**/=0D +STATIC=0D +UINT64=0D +GetFirstNonAddress (=0D + VOID=0D + )=0D +{=0D + UINT64 FirstNonAddress;=0D + UINT64 Pci64Base, Pci64Size;=0D + RETURN_STATUS PcdStatus;=0D +=0D + FirstNonAddress =3D BASE_4GB + GetSystemMemorySizeAbove4gb ();=0D +=0D + //=0D + // If DXE is 32-bit, then we're done; PciBusDxe will degrade 64-bit MMIO= =0D + // resources to 32-bit anyway. See DegradeResource() in=0D + // "PciResourceSupport.c".=0D + //=0D +#ifdef MDE_CPU_IA32=0D + if (!FeaturePcdGet (PcdDxeIplSwitchToLongMode)) {=0D + return FirstNonAddress;=0D + }=0D +#endif=0D +=0D + //=0D + // Otherwise, in order to calculate the highest address plus one, we mus= t=0D + // consider the 64-bit PCI host aperture too. Fetch the default size.=0D + //=0D + Pci64Size =3D PcdGet64 (PcdPciMmio64Size);=0D +=0D + if (Pci64Size =3D=3D 0) {=0D + if (mBootMode !=3D BOOT_ON_S3_RESUME) {=0D + DEBUG ((DEBUG_INFO, "%a: disabling 64-bit PCI host aperture\n",=0D + __FUNCTION__));=0D + PcdStatus =3D PcdSet64S (PcdPciMmio64Size, 0);=0D + ASSERT_RETURN_ERROR (PcdStatus);=0D + }=0D +=0D + //=0D + // There's nothing more to do; the amount of memory above 4GB fully=0D + // determines the highest address plus one. The memory hotplug area (s= ee=0D + // below) plays no role for the firmware in this case.=0D + //=0D + return FirstNonAddress;=0D + }=0D +=0D + //=0D + // SeaBIOS aligns both boundaries of the 64-bit PCI host aperture to 1GB= , so=0D + // that the host can map it with 1GB hugepages. Follow suit.=0D + //=0D + Pci64Base =3D ALIGN_VALUE (FirstNonAddress, (UINT64)SIZE_1GB);=0D + Pci64Size =3D ALIGN_VALUE (Pci64Size, (UINT64)SIZE_1GB);=0D +=0D + //=0D + // The 64-bit PCI host aperture should also be "naturally" aligned. The= =0D + // alignment is determined by rounding the size of the aperture down to = the=0D + // next smaller or equal power of two. That is, align the aperture by th= e=0D + // largest BAR size that can fit into it.=0D + //=0D + Pci64Base =3D ALIGN_VALUE (Pci64Base, GetPowerOfTwo64 (Pci64Size));=0D +=0D + if (mBootMode !=3D BOOT_ON_S3_RESUME) {=0D + //=0D + // The core PciHostBridgeDxe driver will automatically add this range = to=0D + // the GCD memory space map through our PciHostBridgeLib instance; her= e we=0D + // only need to set the PCDs.=0D + //=0D + PcdStatus =3D PcdSet64S (PcdPciMmio64Base, Pci64Base);=0D + ASSERT_RETURN_ERROR (PcdStatus);=0D + PcdStatus =3D PcdSet64S (PcdPciMmio64Size, Pci64Size);=0D + ASSERT_RETURN_ERROR (PcdStatus);=0D +=0D + DEBUG ((DEBUG_INFO, "%a: Pci64Base=3D0x%Lx Pci64Size=3D0x%Lx\n",=0D + __FUNCTION__, Pci64Base, Pci64Size));=0D + }=0D +=0D + //=0D + // The useful address space ends with the 64-bit PCI host aperture.=0D + //=0D + FirstNonAddress =3D Pci64Base + Pci64Size;=0D + return FirstNonAddress;=0D +}=0D +=0D +=0D +/**=0D + Initialize the mPhysMemAddressWidth variable, based on guest RAM size.=0D +**/=0D +VOID=0D +AddressWidthInitialization (=0D + VOID=0D + )=0D +{=0D + UINT64 FirstNonAddress;=0D +=0D + //=0D + // As guest-physical memory size grows, the permanent PEI RAM requiremen= ts=0D + // are dominated by the identity-mapping page tables built by the DXE IP= L.=0D + // The DXL IPL keys off of the physical address bits advertized in the C= PU=0D + // HOB. To conserve memory, we calculate the minimum address width here.= =0D + //=0D + FirstNonAddress =3D GetFirstNonAddress ();=0D + mPhysMemAddressWidth =3D (UINT8)HighBitSet64 (FirstNonAddress);=0D +=0D + //=0D + // If FirstNonAddress is not an integral power of two, then we need an=0D + // additional bit.=0D + //=0D + if ((FirstNonAddress & (FirstNonAddress - 1)) !=3D 0) {=0D + ++mPhysMemAddressWidth;=0D + }=0D +=0D + //=0D + // The minimum address width is 36 (covers up to and excluding 64 GB, wh= ich=0D + // is the maximum for Ia32 + PAE). The theoretical architecture maximum = for=0D + // X64 long mode is 52 bits, but the DXE IPL clamps that down to 48 bits= . We=0D + // can simply assert that here, since 48 bits are good enough for 256 TB= .=0D + //=0D + if (mPhysMemAddressWidth <=3D 36) {=0D + mPhysMemAddressWidth =3D 36;=0D + }=0D + ASSERT (mPhysMemAddressWidth <=3D 48);=0D +}=0D +=0D +=0D +/**=0D + Calculate the cap for the permanent PEI memory.=0D +**/=0D +STATIC=0D +UINT32=0D +GetPeiMemoryCap (=0D + VOID=0D + )=0D +{=0D + BOOLEAN Page1GSupport;=0D + UINT32 RegEax;=0D + UINT32 RegEdx;=0D + UINT32 Pml4Entries;=0D + UINT32 PdpEntries;=0D + UINTN TotalPages;=0D +=0D + //=0D + // If DXE is 32-bit, then just return the traditional 64 MB cap.=0D + //=0D +#ifdef MDE_CPU_IA32=0D + if (!FeaturePcdGet (PcdDxeIplSwitchToLongMode)) {=0D + return SIZE_64MB;=0D + }=0D +#endif=0D +=0D + //=0D + // Dependent on physical address width, PEI memory allocations can be=0D + // dominated by the page tables built for 64-bit DXE. So we key the cap = off=0D + // of those. The code below is based on CreateIdentityMappingPageTables(= ) in=0D + // "MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c".=0D + //=0D + Page1GSupport =3D FALSE;=0D + if (PcdGetBool (PcdUse1GPageTable)) {=0D + AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);=0D + if (RegEax >=3D 0x80000001) {=0D + AsmCpuid (0x80000001, NULL, NULL, NULL, &RegEdx);=0D + if ((RegEdx & BIT26) !=3D 0) {=0D + Page1GSupport =3D TRUE;=0D + }=0D + }=0D + }=0D +=0D + if (mPhysMemAddressWidth <=3D 39) {=0D + Pml4Entries =3D 1;=0D + PdpEntries =3D 1 << (mPhysMemAddressWidth - 30);=0D + ASSERT (PdpEntries <=3D 0x200);=0D + } else {=0D + Pml4Entries =3D 1 << (mPhysMemAddressWidth - 39);=0D + ASSERT (Pml4Entries <=3D 0x200);=0D + PdpEntries =3D 512;=0D + }=0D +=0D + TotalPages =3D Page1GSupport ? Pml4Entries + 1 :=0D + (PdpEntries + 1) * Pml4Entries + 1;=0D + ASSERT (TotalPages <=3D 0x40201);=0D +=0D + //=0D + // Add 64 MB for miscellaneous allocations. Note that for=0D + // mPhysMemAddressWidth values close to 36, the cap will actually be=0D + // dominated by this increment.=0D + //=0D + return (UINT32)(EFI_PAGES_TO_SIZE (TotalPages) + SIZE_64MB);=0D +}=0D +=0D +=0D +/**=0D + Publish PEI core memory=0D +=0D + @return EFI_SUCCESS The PEIM initialized successfully.=0D +=0D +**/=0D +EFI_STATUS=0D +PublishPeiMemory (=0D + VOID=0D + )=0D +{=0D + EFI_STATUS Status;=0D + EFI_PHYSICAL_ADDRESS MemoryBase;=0D + UINT64 MemorySize;=0D + UINT32 LowerMemorySize;=0D + UINT32 PeiMemoryCap;=0D +=0D + LowerMemorySize =3D GetSystemMemorySizeBelow4gb ();=0D + if (FeaturePcdGet (PcdSmmSmramRequire)) {=0D + //=0D + // TSEG is chipped from the end of low RAM=0D + //=0D + LowerMemorySize -=3D mQ35TsegMbytes * SIZE_1MB;=0D + }=0D +=0D + //=0D + // If S3 is supported, then the S3 permanent PEI memory is placed next,= =0D + // downwards. Its size is primarily dictated by CpuMpPei. The formula be= low=0D + // is an approximation.=0D + //=0D + if (mS3Supported) {=0D + mS3AcpiReservedMemorySize =3D SIZE_512KB +=0D + mMaxCpuCount *=0D + PcdGet32 (PcdCpuApStackSize);=0D + mS3AcpiReservedMemoryBase =3D LowerMemorySize - mS3AcpiReservedMemoryS= ize;=0D + LowerMemorySize =3D mS3AcpiReservedMemoryBase;=0D + }=0D +=0D + if (mBootMode =3D=3D BOOT_ON_S3_RESUME) {=0D + MemoryBase =3D mS3AcpiReservedMemoryBase;=0D + MemorySize =3D mS3AcpiReservedMemorySize;=0D + } else {=0D + PeiMemoryCap =3D GetPeiMemoryCap ();=0D + DEBUG ((DEBUG_INFO, "%a: mPhysMemAddressWidth=3D%d PeiMemoryCap=3D%u K= B\n",=0D + __FUNCTION__, mPhysMemAddressWidth, PeiMemoryCap >> 10));=0D +=0D + //=0D + // Determine the range of memory to use during PEI=0D + //=0D + // Technically we could lay the permanent PEI RAM over SEC's temporary= =0D + // decompression and scratch buffer even if "secure S3" is needed, sin= ce=0D + // their lifetimes don't overlap. However, PeiFvInitialization() will = cover=0D + // RAM up to PcdOvmfDecompressionScratchEnd with an EfiACPIMemoryNVS m= emory=0D + // allocation HOB, and other allocations served from the permanent PEI= RAM=0D + // shouldn't overlap with that HOB.=0D + //=0D + MemoryBase =3D mS3Supported && FeaturePcdGet (PcdSmmSmramRequire) ?=0D + PcdGet32 (PcdOvmfDecompressionScratchEnd) :=0D + PcdGet32 (PcdOvmfDxeMemFvBase) + PcdGet32 (PcdOvmfDxeMemFvSize);=0D + MemorySize =3D LowerMemorySize - MemoryBase;=0D + if (MemorySize > PeiMemoryCap) {=0D + MemoryBase =3D LowerMemorySize - PeiMemoryCap;=0D + MemorySize =3D PeiMemoryCap;=0D + }=0D + }=0D +=0D + //=0D + // Publish this memory to the PEI Core=0D + //=0D + Status =3D PublishSystemMemory(MemoryBase, MemorySize);=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + return Status;=0D +}=0D +=0D +=0D +/**=0D + Peform Memory Detection for QEMU / KVM=0D +=0D +**/=0D +STATIC=0D +VOID=0D +QemuInitializeRam (=0D + VOID=0D + )=0D +{=0D + UINT64 LowerMemorySize;=0D + UINT64 UpperMemorySize;=0D + MTRR_SETTINGS MtrrSettings;=0D + EFI_STATUS Status;=0D +=0D + DEBUG ((DEBUG_INFO, "%a called\n", __FUNCTION__));=0D +=0D + //=0D + // Determine total memory size available=0D + //=0D + LowerMemorySize =3D GetSystemMemorySizeBelow4gb ();=0D + UpperMemorySize =3D GetSystemMemorySizeAbove4gb ();=0D +=0D + if (mBootMode =3D=3D BOOT_ON_S3_RESUME) {=0D + //=0D + // Create the following memory HOB as an exception on the S3 boot path= .=0D + //=0D + // Normally we'd create memory HOBs only on the normal boot path. Howe= ver,=0D + // CpuMpPei specifically needs such a low-memory HOB on the S3 path as= =0D + // well, for "borrowing" a subset of it temporarily, for the AP startu= p=0D + // vector.=0D + //=0D + // CpuMpPei saves the original contents of the borrowed area in perman= ent=0D + // PEI RAM, in a backup buffer allocated with the normal PEI services.= =0D + // CpuMpPei restores the original contents ("returns" the borrowed are= a) at=0D + // End-of-PEI. End-of-PEI in turn is emitted by S3Resume2Pei before=0D + // transferring control to the OS's wakeup vector in the FACS.=0D + //=0D + // We expect any other PEIMs that "borrow" memory similarly to CpuMpPe= i to=0D + // restore the original contents. Furthermore, we expect all such PEIM= s=0D + // (CpuMpPei included) to claim the borrowed areas by producing memory= =0D + // allocation HOBs, and to honor preexistent memory allocation HOBs wh= en=0D + // looking for an area to borrow.=0D + //=0D + AddMemoryRangeHob (0, BASE_512KB + BASE_128KB);=0D + } else {=0D + //=0D + // Create memory HOBs=0D + //=0D + AddMemoryRangeHob (0, BASE_512KB + BASE_128KB);=0D +=0D + if (FeaturePcdGet (PcdSmmSmramRequire)) {=0D + UINT32 TsegSize;=0D +=0D + TsegSize =3D mQ35TsegMbytes * SIZE_1MB;=0D + AddMemoryRangeHob (BASE_1MB, LowerMemorySize - TsegSize);=0D + AddReservedMemoryBaseSizeHob (LowerMemorySize - TsegSize, TsegSize,= =0D + TRUE);=0D + } else {=0D + AddMemoryRangeHob (BASE_1MB, LowerMemorySize);=0D + }=0D +=0D + if (UpperMemorySize !=3D 0) {=0D + AddMemoryBaseSizeHob (BASE_4GB, UpperMemorySize);=0D + }=0D + }=0D +=0D + //=0D + // We'd like to keep the following ranges uncached:=0D + // - [640 KB, 1 MB)=0D + // - [LowerMemorySize, 4 GB)=0D + //=0D + // Everything else should be WB. Unfortunately, programming the inverse = (ie.=0D + // keeping the default UC, and configuring the complement set of the abo= ve as=0D + // WB) is not reliable in general, because the end of the upper RAM can = have=0D + // practically any alignment, and we may not have enough variable MTRRs = to=0D + // cover it exactly.=0D + //=0D + if (IsMtrrSupported ()) {=0D + MtrrGetAllMtrrs (&MtrrSettings);=0D +=0D + //=0D + // MTRRs disabled, fixed MTRRs disabled, default type is uncached=0D + //=0D + ASSERT ((MtrrSettings.MtrrDefType & BIT11) =3D=3D 0);=0D + ASSERT ((MtrrSettings.MtrrDefType & BIT10) =3D=3D 0);=0D + ASSERT ((MtrrSettings.MtrrDefType & 0xFF) =3D=3D 0);=0D +=0D + //=0D + // flip default type to writeback=0D + //=0D + SetMem (&MtrrSettings.Fixed, sizeof MtrrSettings.Fixed, 0x06);=0D + ZeroMem (&MtrrSettings.Variables, sizeof MtrrSettings.Variables);=0D + MtrrSettings.MtrrDefType |=3D BIT11 | BIT10 | 6;=0D + MtrrSetAllMtrrs (&MtrrSettings);=0D +=0D + //=0D + // Set memory range from 640KB to 1MB to uncacheable=0D + //=0D + Status =3D MtrrSetMemoryAttribute (BASE_512KB + BASE_128KB,=0D + BASE_1MB - (BASE_512KB + BASE_128KB), CacheUncacheable);=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + //=0D + // Set memory range from the "top of lower RAM" (RAM below 4GB) to 4GB= as=0D + // uncacheable=0D + //=0D + Status =3D MtrrSetMemoryAttribute (LowerMemorySize,=0D + SIZE_4GB - LowerMemorySize, CacheUncacheable);=0D + ASSERT_EFI_ERROR (Status);=0D + }=0D +}=0D +=0D +/**=0D + Publish system RAM and reserve memory regions=0D +=0D +**/=0D +VOID=0D +InitializeRamRegions (=0D + VOID=0D + )=0D +{=0D + QemuInitializeRam ();=0D +=0D + if (mS3Supported && mBootMode !=3D BOOT_ON_S3_RESUME) {=0D + //=0D + // This is the memory range that will be used for PEI on S3 resume=0D + //=0D + BuildMemoryAllocationHob (=0D + mS3AcpiReservedMemoryBase,=0D + mS3AcpiReservedMemorySize,=0D + EfiACPIMemoryNVS=0D + );=0D +=0D + //=0D + // Cover the initial RAM area used as stack and temporary PEI heap.=0D + //=0D + // This is reserved as ACPI NVS so it can be used on S3 resume.=0D + //=0D + BuildMemoryAllocationHob (=0D + PcdGet32 (PcdOvmfSecPeiTempRamBase),=0D + PcdGet32 (PcdOvmfSecPeiTempRamSize),=0D + EfiACPIMemoryNVS=0D + );=0D +=0D + //=0D + // SEC stores its table of GUIDed section handlers here.=0D + //=0D + BuildMemoryAllocationHob (=0D + PcdGet64 (PcdGuidedExtractHandlerTableAddress),=0D + PcdGet32 (PcdGuidedExtractHandlerTableSize),=0D + EfiACPIMemoryNVS=0D + );=0D +=0D +#ifdef MDE_CPU_X64=0D + //=0D + // Reserve the initial page tables built by the reset vector code.=0D + //=0D + // Since this memory range will be used by the Reset Vector on S3=0D + // resume, it must be reserved as ACPI NVS.=0D + //=0D + BuildMemoryAllocationHob (=0D + (EFI_PHYSICAL_ADDRESS)(UINTN) PcdGet32 (PcdOvmfSecPageTablesBase),=0D + (UINT64)(UINTN) PcdGet32 (PcdOvmfSecPageTablesSize),=0D + EfiACPIMemoryNVS=0D + );=0D +#endif=0D + }=0D +=0D + if (mBootMode !=3D BOOT_ON_S3_RESUME) {=0D + if (!FeaturePcdGet (PcdSmmSmramRequire)) {=0D + //=0D + // Reserve the lock box storage area=0D + //=0D + // Since this memory range will be used on S3 resume, it must be=0D + // reserved as ACPI NVS.=0D + //=0D + // If S3 is unsupported, then various drivers might still write to t= he=0D + // LockBox area. We ought to prevent DXE from serving allocation req= uests=0D + // such that they would overlap the LockBox storage.=0D + //=0D + ZeroMem (=0D + (VOID*)(UINTN) PcdGet32 (PcdOvmfLockBoxStorageBase),=0D + (UINTN) PcdGet32 (PcdOvmfLockBoxStorageSize)=0D + );=0D + BuildMemoryAllocationHob (=0D + (EFI_PHYSICAL_ADDRESS)(UINTN) PcdGet32 (PcdOvmfLockBoxStorageBase)= ,=0D + (UINT64)(UINTN) PcdGet32 (PcdOvmfLockBoxStorageSize),=0D + mS3Supported ? EfiACPIMemoryNVS : EfiBootServicesData=0D + );=0D + }=0D +=0D + if (FeaturePcdGet (PcdSmmSmramRequire)) {=0D + UINT32 TsegSize;=0D +=0D + //=0D + // Make sure the TSEG area that we reported as a reserved memory res= ource=0D + // cannot be used for reserved memory allocations.=0D + //=0D + TsegSize =3D mQ35TsegMbytes * SIZE_1MB;=0D + BuildMemoryAllocationHob (=0D + GetSystemMemorySizeBelow4gb() - TsegSize,=0D + TsegSize,=0D + EfiReservedMemoryType=0D + );=0D + }=0D + }=0D +}=0D diff --git a/OvmfPkg/Bhyve/PlatformPei/Platform.c b/OvmfPkg/Bhyve/PlatformP= ei/Platform.c new file mode 100644 index 0000000000..11658d478c --- /dev/null +++ b/OvmfPkg/Bhyve/PlatformPei/Platform.c @@ -0,0 +1,607 @@ +/**@file=0D + Platform PEI driver=0D +=0D + Copyright (c) 2020, Rebecca Cran <rebecca@...>=0D + Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>=0D + Copyright (c) 2011, Andrei Warkentin <andreiw@...>=0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +//=0D +// The package level header files this module uses=0D +//=0D +#include <PiPei.h>=0D +=0D +//=0D +// The Library classes this module consumes=0D +//=0D +#include <Library/BaseLib.h>=0D +#include <Library/DebugLib.h>=0D +#include <Library/HobLib.h>=0D +#include <Library/IoLib.h>=0D +#include <Library/MemoryAllocationLib.h>=0D +#include <Library/PcdLib.h>=0D +#include <Library/PciLib.h>=0D +#include <Library/PeimEntryPoint.h>=0D +#include <Library/PeiServicesLib.h>=0D +#include <Library/ResourcePublicationLib.h>=0D +#include <Library/LocalApicLib.h>=0D +#include <Guid/MemoryTypeInformation.h>=0D +#include <Ppi/MasterBootMode.h>=0D +#include <IndustryStandard/Pci22.h>=0D +#include <OvmfPlatforms.h>=0D +=0D +#include "Platform.h"=0D +#include "Cmos.h"=0D +=0D +EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] =3D {=0D + { EfiACPIMemoryNVS, 0x004 },=0D + { EfiACPIReclaimMemory, 0x008 },=0D + { EfiReservedMemoryType, 0x004 },=0D + { EfiRuntimeServicesData, 0x024 },=0D + { EfiRuntimeServicesCode, 0x030 },=0D + { EfiBootServicesCode, 0x180 },=0D + { EfiBootServicesData, 0xF00 },=0D + { EfiMaxMemoryType, 0x000 }=0D +};=0D +=0D +=0D +EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] =3D {=0D + {=0D + EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,=0D + &gEfiPeiMasterBootModePpiGuid,=0D + NULL=0D + }=0D +};=0D +=0D +=0D +UINT16 mHostBridgeDevId;=0D +=0D +EFI_BOOT_MODE mBootMode =3D BOOT_WITH_FULL_CONFIGURATION;=0D +=0D +BOOLEAN mS3Supported =3D FALSE;=0D +=0D +UINT32 mMaxCpuCount;=0D +=0D +VOID=0D +AddIoMemoryBaseSizeHob (=0D + EFI_PHYSICAL_ADDRESS MemoryBase,=0D + UINT64 MemorySize=0D + )=0D +{=0D + BuildResourceDescriptorHob (=0D + EFI_RESOURCE_MEMORY_MAPPED_IO,=0D + EFI_RESOURCE_ATTRIBUTE_PRESENT |=0D + EFI_RESOURCE_ATTRIBUTE_INITIALIZED |=0D + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |=0D + EFI_RESOURCE_ATTRIBUTE_TESTED,=0D + MemoryBase,=0D + MemorySize=0D + );=0D +}=0D +=0D +VOID=0D +AddReservedMemoryBaseSizeHob (=0D + EFI_PHYSICAL_ADDRESS MemoryBase,=0D + UINT64 MemorySize,=0D + BOOLEAN Cacheable=0D + )=0D +{=0D + BuildResourceDescriptorHob (=0D + EFI_RESOURCE_MEMORY_RESERVED,=0D + EFI_RESOURCE_ATTRIBUTE_PRESENT |=0D + EFI_RESOURCE_ATTRIBUTE_INITIALIZED |=0D + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |=0D + (Cacheable ?=0D + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |=0D + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |=0D + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE :=0D + 0=0D + ) |=0D + EFI_RESOURCE_ATTRIBUTE_TESTED,=0D + MemoryBase,=0D + MemorySize=0D + );=0D +}=0D +=0D +VOID=0D +AddIoMemoryRangeHob (=0D + EFI_PHYSICAL_ADDRESS MemoryBase,=0D + EFI_PHYSICAL_ADDRESS MemoryLimit=0D + )=0D +{=0D + AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));= =0D +}=0D +=0D +=0D +VOID=0D +AddMemoryBaseSizeHob (=0D + EFI_PHYSICAL_ADDRESS MemoryBase,=0D + UINT64 MemorySize=0D + )=0D +{=0D + BuildResourceDescriptorHob (=0D + EFI_RESOURCE_SYSTEM_MEMORY,=0D + EFI_RESOURCE_ATTRIBUTE_PRESENT |=0D + EFI_RESOURCE_ATTRIBUTE_INITIALIZED |=0D + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |=0D + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |=0D + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |=0D + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |=0D + EFI_RESOURCE_ATTRIBUTE_TESTED,=0D + MemoryBase,=0D + MemorySize=0D + );=0D +}=0D +=0D +=0D +VOID=0D +AddMemoryRangeHob (=0D + EFI_PHYSICAL_ADDRESS MemoryBase,=0D + EFI_PHYSICAL_ADDRESS MemoryLimit=0D + )=0D +{=0D + AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));=0D +}=0D +=0D +=0D +VOID=0D +MemMapInitialization (=0D + VOID=0D + )=0D +{=0D + UINT64 PciIoBase;=0D + UINT64 PciIoSize;=0D + RETURN_STATUS PcdStatus;=0D +=0D + PciIoBase =3D 0xC000;=0D + PciIoSize =3D 0x4000;=0D +=0D + //=0D + // Create Memory Type Information HOB=0D + //=0D + BuildGuidDataHob (=0D + &gEfiMemoryTypeInformationGuid,=0D + mDefaultMemoryTypeInformation,=0D + sizeof(mDefaultMemoryTypeInformation)=0D + );=0D +=0D + //=0D + // Video memory + Legacy BIOS region=0D + //=0D + AddIoMemoryRangeHob (0x0A0000, BASE_1MB);=0D +=0D + if (TRUE) {=0D + UINT32 TopOfLowRam;=0D + UINT64 PciExBarBase;=0D + UINT32 PciBase;=0D + UINT32 PciSize;=0D +=0D + TopOfLowRam =3D GetSystemMemorySizeBelow4gb ();=0D + PciExBarBase =3D 0;=0D + if (mHostBridgeDevId =3D=3D INTEL_Q35_MCH_DEVICE_ID) {=0D + //=0D + // The MMCONFIG area is expected to fall between the top of low RAM = and=0D + // the base of the 32-bit PCI host aperture.=0D + //=0D + PciExBarBase =3D FixedPcdGet64 (PcdPciExpressBaseAddress);=0D + ASSERT (TopOfLowRam <=3D PciExBarBase);=0D + ASSERT (PciExBarBase <=3D MAX_UINT32 - SIZE_256MB);=0D + PciBase =3D (UINT32)(PciExBarBase + SIZE_256MB);=0D + } else {=0D + PciBase =3D (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam;=0D + }=0D +=0D + //=0D + // address purpose size=0D + // ------------ -------- -------------------------=0D + // max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g)=0D + // 0xFC000000 gap 44 MB=0D + // 0xFEC00000 IO-APIC 4 KB=0D + // 0xFEC01000 gap 1020 KB=0D + // 0xFED00000 HPET 1 KB=0D + // 0xFED00400 gap 111 KB=0D + // 0xFED1C000 gap (PIIX4) / RCRB (ICH9) 16 KB=0D + // 0xFED20000 gap 896 KB=0D + // 0xFEE00000 LAPIC 1 MB=0D + //=0D + PciSize =3D 0xFC000000 - PciBase;=0D + AddIoMemoryBaseSizeHob (PciBase, PciSize);=0D + PcdStatus =3D PcdSet64S (PcdPciMmio32Base, PciBase);=0D + ASSERT_RETURN_ERROR (PcdStatus);=0D + PcdStatus =3D PcdSet64S (PcdPciMmio32Size, PciSize);=0D + ASSERT_RETURN_ERROR (PcdStatus);=0D +=0D + AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);=0D + AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);=0D + if (mHostBridgeDevId =3D=3D INTEL_Q35_MCH_DEVICE_ID) {=0D + AddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB);=0D + //=0D + // Note: there should be an=0D + //=0D + // AddIoMemoryBaseSizeHob (PciExBarBase, SIZE_256MB);=0D + //=0D + // call below, just like the one above for RCBA. However, Linux insi= sts=0D + // that the MMCONFIG area be marked in the E820 or UEFI memory map a= s=0D + // "reserved memory" -- Linux does not content itself with a simple = gap=0D + // in the memory map wherever the MCFG ACPI table points to.=0D + //=0D + // This appears to be a safety measure. The PCI Firmware Specificati= on=0D + // (rev 3.1) says in 4.1.2. "MCFG Table Description": "The resources= can=0D + // *optionally* be returned in [...] EFIGetMemoryMap as reserved mem= ory=0D + // [...]". (Emphasis added here.)=0D + //=0D + // Normally we add memory resource descriptor HOBs in=0D + // QemuInitializeRam(), and pre-allocate from those with memory=0D + // allocation HOBs in InitializeRamRegions(). However, the MMCONFIG = area=0D + // is most definitely not RAM; so, as an exception, cover it with=0D + // uncacheable reserved memory right here.=0D + //=0D + AddReservedMemoryBaseSizeHob (PciExBarBase, SIZE_256MB, FALSE);=0D + BuildMemoryAllocationHob (PciExBarBase, SIZE_256MB,=0D + EfiReservedMemoryType);=0D + }=0D + AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB= );=0D +=0D + //=0D + // On Q35, the IO Port space is available for PCI resource allocations= from=0D + // 0x6000 up.=0D + //=0D + if (mHostBridgeDevId =3D=3D INTEL_Q35_MCH_DEVICE_ID) {=0D + PciIoBase =3D 0x6000;=0D + PciIoSize =3D 0xA000;=0D + ASSERT ((ICH9_PMBASE_VALUE & 0xF000) < PciIoBase);=0D + }=0D + }=0D +=0D + //=0D + // Add PCI IO Port space available for PCI resource allocations.=0D + //=0D + BuildResourceDescriptorHob (=0D + EFI_RESOURCE_IO,=0D + EFI_RESOURCE_ATTRIBUTE_PRESENT |=0D + EFI_RESOURCE_ATTRIBUTE_INITIALIZED,=0D + PciIoBase,=0D + PciIoSize=0D + );=0D + PcdStatus =3D PcdSet64S (PcdPciIoBase, PciIoBase);=0D + ASSERT_RETURN_ERROR (PcdStatus);=0D + PcdStatus =3D PcdSet64S (PcdPciIoSize, PciIoSize);=0D + ASSERT_RETURN_ERROR (PcdStatus);=0D +}=0D +=0D +VOID=0D +NoexecDxeInitialization (=0D + VOID=0D + )=0D +{=0D +}=0D +=0D +VOID=0D +PciExBarInitialization (=0D + VOID=0D + )=0D +{=0D + union {=0D + UINT64 Uint64;=0D + UINT32 Uint32[2];=0D + } PciExBarBase;=0D +=0D + //=0D + // We only support the 256MB size for the MMCONFIG area:=0D + // 256 buses * 32 devices * 8 functions * 4096 bytes config space.=0D + //=0D + // The masks used below enforce the Q35 requirements that the MMCONFIG a= rea=0D + // be (a) correctly aligned -- here at 256 MB --, (b) located under 64 G= B.=0D + //=0D + // Note that (b) also ensures that the minimum address width we have=0D + // determined in AddressWidthInitialization(), i.e., 36 bits, will suffi= ce=0D + // for DXE's page tables to cover the MMCONFIG area.=0D + //=0D + PciExBarBase.Uint64 =3D FixedPcdGet64 (PcdPciExpressBaseAddress);=0D + ASSERT ((PciExBarBase.Uint32[1] & MCH_PCIEXBAR_HIGHMASK) =3D=3D 0);=0D + ASSERT ((PciExBarBase.Uint32[0] & MCH_PCIEXBAR_LOWMASK) =3D=3D 0);=0D +=0D + //=0D + // Clear the PCIEXBAREN bit first, before programming the high register.= =0D + //=0D + PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW), 0);=0D +=0D + //=0D + // Program the high register. Then program the low register, setting the= =0D + // MMCONFIG area size and enabling decoding at once.=0D + //=0D + PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_HIGH), PciExBarBase.Uint32[= 1]);=0D + PciWrite32 (=0D + DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW),=0D + PciExBarBase.Uint32[0] | MCH_PCIEXBAR_BUS_FF | MCH_PCIEXBAR_EN=0D + );=0D +}=0D +=0D +VOID=0D +MiscInitialization (=0D + VOID=0D + )=0D +{=0D + UINTN PmCmd;=0D + UINTN Pmba;=0D + UINT32 PmbaAndVal;=0D + UINT32 PmbaOrVal;=0D + UINTN AcpiCtlReg;=0D + UINT8 AcpiEnBit;=0D + RETURN_STATUS PcdStatus;=0D +=0D + //=0D + // Disable A20 Mask=0D + //=0D + IoOr8 (0x92, BIT1);=0D +=0D + //=0D + // Build the CPU HOB with guest RAM size dependent address width and 16-= bits=0D + // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed dur= ing=0D + // S3 resume as well, so we build it unconditionally.)=0D + //=0D + BuildCpuHob (mPhysMemAddressWidth, 16);=0D +=0D + //=0D + // Determine platform type and save Host Bridge DID to PCD=0D + //=0D + switch (mHostBridgeDevId) {=0D + case 0x1275: // BHYVE=0D + case INTEL_82441_DEVICE_ID:=0D + PmCmd =3D POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);=0D + Pmba =3D POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);=0D + PmbaAndVal =3D ~(UINT32)PIIX4_PMBA_MASK;=0D + PmbaOrVal =3D PIIX4_PMBA_VALUE;=0D + AcpiCtlReg =3D POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);=0D + AcpiEnBit =3D PIIX4_PMREGMISC_PMIOSE;=0D + break;=0D + case INTEL_Q35_MCH_DEVICE_ID:=0D + PmCmd =3D POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET);=0D + Pmba =3D POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);=0D + PmbaAndVal =3D ~(UINT32)ICH9_PMBASE_MASK;=0D + PmbaOrVal =3D ICH9_PMBASE_VALUE;=0D + AcpiCtlReg =3D POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);=0D + AcpiEnBit =3D ICH9_ACPI_CNTL_ACPI_EN;=0D + break;=0D + default:=0D + DEBUG ((DEBUG_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",= =0D + __FUNCTION__, mHostBridgeDevId));=0D + ASSERT (FALSE);=0D + return;=0D + }=0D + PcdStatus =3D PcdSet16S (PcdOvmfHostBridgePciDevId, mHostBridgeDevId);=0D + ASSERT_RETURN_ERROR (PcdStatus);=0D +=0D + //=0D + // If the appropriate IOspace enable bit is set, assume the ACPI PMBA=0D + // has been configured (e.g., by Xen) and skip the setup here.=0D + // This matches the logic in AcpiTimerLibConstructor ().=0D + //=0D + if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) =3D=3D 0) {=0D + //=0D + // The PEI phase should be exited with fully accessibe ACPI PM IO spac= e:=0D + // 1. set PMBA=0D + //=0D + PciAndThenOr32 (Pmba, PmbaAndVal, PmbaOrVal);=0D +=0D + //=0D + // 2. set PCICMD/IOSE=0D + //=0D + PciOr8 (PmCmd, EFI_PCI_COMMAND_IO_SPACE);=0D +=0D + //=0D + // 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN= )=0D + //=0D + PciOr8 (AcpiCtlReg, AcpiEnBit);=0D + }=0D +=0D + if (mHostBridgeDevId =3D=3D INTEL_Q35_MCH_DEVICE_ID) {=0D + //=0D + // Set Root Complex Register Block BAR=0D + //=0D + PciWrite32 (=0D + POWER_MGMT_REGISTER_Q35 (ICH9_RCBA),=0D + ICH9_ROOT_COMPLEX_BASE | ICH9_RCBA_EN=0D + );=0D +=0D + //=0D + // Set PCI Express Register Range Base Address=0D + //=0D + PciExBarInitialization ();=0D + }=0D +}=0D +=0D +=0D +VOID=0D +BootModeInitialization (=0D + VOID=0D + )=0D +{=0D + EFI_STATUS Status;=0D +=0D + if (CmosRead8 (0xF) =3D=3D 0xFE) {=0D + mBootMode =3D BOOT_ON_S3_RESUME;=0D + }=0D + CmosWrite8 (0xF, 0x00);=0D +=0D + Status =3D PeiServicesSetBootMode (mBootMode);=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + Status =3D PeiServicesInstallPpi (mPpiBootMode);=0D + ASSERT_EFI_ERROR (Status);=0D +}=0D +=0D +=0D +VOID=0D +ReserveEmuVariableNvStore (=0D + )=0D +{=0D + EFI_PHYSICAL_ADDRESS VariableStore;=0D + RETURN_STATUS PcdStatus;=0D +=0D + //=0D + // Allocate storage for NV variables early on so it will be=0D + // at a consistent address. Since VM memory is preserved=0D + // across reboots, this allows the NV variable storage to survive=0D + // a VM reboot.=0D + //=0D + VariableStore =3D=0D + (EFI_PHYSICAL_ADDRESS)(UINTN)=0D + AllocateRuntimePages (=0D + EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize))=0D + );=0D + DEBUG ((DEBUG_INFO,=0D + "Reserved variable store memory: 0x%lX; size: %dkb\n",=0D + VariableStore,=0D + (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / 1024=0D + ));=0D + PcdStatus =3D PcdSet64S (PcdEmuVariableNvStoreReserved, VariableStore);= =0D + ASSERT_RETURN_ERROR (PcdStatus);=0D +}=0D +=0D +=0D +VOID=0D +DebugDumpCmos (=0D + VOID=0D + )=0D +{=0D + UINT32 Loop;=0D +=0D + DEBUG ((DEBUG_INFO, "CMOS:\n"));=0D +=0D + for (Loop =3D 0; Loop < 0x80; Loop++) {=0D + if ((Loop % 0x10) =3D=3D 0) {=0D + DEBUG ((DEBUG_INFO, "%02x:", Loop));=0D + }=0D + DEBUG ((DEBUG_INFO, " %02x", CmosRead8 (Loop)));=0D + if ((Loop % 0x10) =3D=3D 0xf) {=0D + DEBUG ((DEBUG_INFO, "\n"));=0D + }=0D + }=0D +}=0D +=0D +=0D +VOID=0D +S3Verification (=0D + VOID=0D + )=0D +{=0D +#if defined (MDE_CPU_X64)=0D + if (FeaturePcdGet (PcdSmmSmramRequire) && mS3Supported) {=0D + DEBUG ((DEBUG_ERROR,=0D + "%a: S3Resume2Pei doesn't support X64 PEI + SMM yet.\n", __FUNCTION_= _));=0D + DEBUG ((DEBUG_ERROR,=0D + "%a: Please disable S3 on the QEMU command line (see the README),\n"= ,=0D + __FUNCTION__));=0D + DEBUG ((DEBUG_ERROR,=0D + "%a: or build OVMF with \"OvmfPkgIa32X64.dsc\".\n", __FUNCTION__));= =0D + ASSERT (FALSE);=0D + CpuDeadLoop ();=0D + }=0D +#endif=0D +}=0D +=0D +=0D +/**=0D + Fetch the number of boot CPUs from QEMU and expose it to UefiCpuPkg modu= les.=0D + Set the mMaxCpuCount variable.=0D +**/=0D +VOID=0D +MaxCpuCountInitialization (=0D + VOID=0D + )=0D +{=0D + UINT16 ProcessorCount =3D 0;=0D + RETURN_STATUS PcdStatus;=0D +=0D + //=0D + // If the fw_cfg key or fw_cfg entirely is unavailable, load mMaxCpuCoun= t=0D + // from the PCD default. No change to PCDs.=0D + //=0D + if (ProcessorCount =3D=3D 0) {=0D + mMaxCpuCount =3D PcdGet32 (PcdCpuMaxLogicalProcessorNumber);=0D + return;=0D + }=0D + //=0D + // Otherwise, set mMaxCpuCount to the value reported by QEMU.=0D + //=0D + mMaxCpuCount =3D ProcessorCount;=0D + //=0D + // Additionally, tell UefiCpuPkg modules (a) the exact number of VCPUs, = (b)=0D + // to wait, in the initial AP bringup, exactly as long as it takes for a= ll of=0D + // the APs to report in. For this, we set the longest representable time= out=0D + // (approx. 71 minutes).=0D + //=0D + PcdStatus =3D PcdSet32S (PcdCpuMaxLogicalProcessorNumber, ProcessorCount= );=0D + ASSERT_RETURN_ERROR (PcdStatus);=0D + PcdStatus =3D PcdSet32S (PcdCpuApInitTimeOutInMicroSeconds, MAX_UINT32);= =0D + ASSERT_RETURN_ERROR (PcdStatus);=0D + DEBUG ((DEBUG_INFO, "%a: QEMU reports %d processor(s)\n", __FUNCTION__,= =0D + ProcessorCount));=0D +}=0D +=0D +=0D +/**=0D + Perform Platform PEI initialization.=0D +=0D + @param FileHandle Handle of the file being invoked.=0D + @param PeiServices Describes the list of possible PEI Services.=0D +=0D + @return EFI_SUCCESS The PEIM initialized successfully.=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +InitializePlatform (=0D + IN EFI_PEI_FILE_HANDLE FileHandle,=0D + IN CONST EFI_PEI_SERVICES **PeiServices=0D + )=0D +{=0D + DEBUG ((DEBUG_INFO, "Platform PEIM Loaded\n"));=0D +=0D + //=0D + // Initialize Local APIC Timer hardware and disable Local APIC Timer=0D + // interrupts before initializing the Debug Agent and the debug timer is= =0D + // enabled.=0D + //=0D + InitializeApicTimer (0, MAX_UINT32, TRUE, 5);=0D + DisableApicTimerInterrupt ();=0D +=0D + DebugDumpCmos ();=0D +=0D + BootModeInitialization ();=0D + AddressWidthInitialization ();=0D + MaxCpuCountInitialization ();=0D +=0D + //=0D + // Query Host Bridge DID=0D + //=0D + mHostBridgeDevId =3D PciRead16 (OVMF_HOSTBRIDGE_DID);=0D +=0D + if (FeaturePcdGet (PcdSmmSmramRequire)) {=0D + Q35TsegMbytesInitialization ();=0D + }=0D +=0D + PublishPeiMemory ();=0D +=0D + InitializeRamRegions ();=0D +=0D + if (mBootMode !=3D BOOT_ON_S3_RESUME) {=0D + if (!FeaturePcdGet (PcdSmmSmramRequire)) {=0D + ReserveEmuVariableNvStore ();=0D + }=0D + PeiFvInitialization ();=0D + MemMapInitialization ();=0D + NoexecDxeInitialization ();=0D + }=0D +=0D + InstallClearCacheCallback ();=0D + AmdSevInitialize ();=0D + MiscInitialization ();=0D + InstallFeatureControlCallback ();=0D +=0D + return EFI_SUCCESS;=0D +}=0D diff --git a/OvmfPkg/Bhyve/PlatformPei/Platform.h b/OvmfPkg/Bhyve/PlatformP= ei/Platform.h new file mode 100644 index 0000000000..8239ca05ac --- /dev/null +++ b/OvmfPkg/Bhyve/PlatformPei/Platform.h @@ -0,0 +1,137 @@ +/** @file=0D + Platform PEI module include file.=0D +=0D + Copyright (c) 2020, Rebecca Cran <rebecca@...>=0D + Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#ifndef _PLATFORM_PEI_H_INCLUDED_=0D +#define _PLATFORM_PEI_H_INCLUDED_=0D +=0D +#include <IndustryStandard/E820.h>=0D +=0D +VOID=0D +AddIoMemoryBaseSizeHob (=0D + EFI_PHYSICAL_ADDRESS MemoryBase,=0D + UINT64 MemorySize=0D + );=0D +=0D +VOID=0D +AddIoMemoryRangeHob (=0D + EFI_PHYSICAL_ADDRESS MemoryBase,=0D + EFI_PHYSICAL_ADDRESS MemoryLimit=0D + );=0D +=0D +VOID=0D +AddMemoryBaseSizeHob (=0D + EFI_PHYSICAL_ADDRESS MemoryBase,=0D + UINT64 MemorySize=0D + );=0D +=0D +VOID=0D +AddMemoryRangeHob (=0D + EFI_PHYSICAL_ADDRESS MemoryBase,=0D + EFI_PHYSICAL_ADDRESS MemoryLimit=0D + );=0D +=0D +VOID=0D +AddReservedMemoryBaseSizeHob (=0D + EFI_PHYSICAL_ADDRESS MemoryBase,=0D + UINT64 MemorySize,=0D + BOOLEAN Cacheable=0D + );=0D +=0D +VOID=0D +AddressWidthInitialization (=0D + VOID=0D + );=0D +=0D +VOID=0D +Q35TsegMbytesInitialization (=0D + VOID=0D + );=0D +=0D +VOID=0D +Q35SmramAtDefaultSmbaseInitialization (=0D + VOID=0D + );=0D +=0D +EFI_STATUS=0D +PublishPeiMemory (=0D + VOID=0D + );=0D +=0D +UINT32=0D +GetSystemMemorySizeBelow4gb (=0D + VOID=0D + );=0D +=0D +VOID=0D +QemuUc32BaseInitialization (=0D + VOID=0D + );=0D +=0D +VOID=0D +InitializeRamRegions (=0D + VOID=0D + );=0D +=0D +EFI_STATUS=0D +PeiFvInitialization (=0D + VOID=0D + );=0D +=0D +VOID=0D +MemTypeInfoInitialization (=0D + VOID=0D + );=0D +=0D +VOID=0D +InstallFeatureControlCallback (=0D + VOID=0D + );=0D +=0D +VOID=0D +InstallClearCacheCallback (=0D + VOID=0D + );=0D +=0D +EFI_STATUS=0D +InitializeXen (=0D + VOID=0D + );=0D +=0D +BOOLEAN=0D +XenDetect (=0D + VOID=0D + );=0D +=0D +VOID=0D +AmdSevInitialize (=0D + VOID=0D + );=0D +=0D +extern BOOLEAN mXen;=0D +=0D +VOID=0D +XenPublishRamRegions (=0D + VOID=0D + );=0D +=0D +extern EFI_BOOT_MODE mBootMode;=0D +=0D +extern BOOLEAN mS3Supported;=0D +=0D +extern UINT8 mPhysMemAddressWidth;=0D +=0D +extern UINT32 mMaxCpuCount;=0D +=0D +extern UINT16 mHostBridgeDevId;=0D +=0D +extern BOOLEAN mQ35SmramAtDefaultSmbase;=0D +=0D +extern UINT32 mQemuUc32Base;=0D +=0D +#endif // _PLATFORM_PEI_H_INCLUDED_=0D diff --git a/OvmfPkg/Bhyve/PlatformPei/PlatformPei.inf b/OvmfPkg/Bhyve/Plat= formPei/PlatformPei.inf new file mode 100644 index 0000000000..7288cff4c8 --- /dev/null +++ b/OvmfPkg/Bhyve/PlatformPei/PlatformPei.inf @@ -0,0 +1,113 @@ +## @file=0D +# Platform PEI driver=0D +#=0D +# This module provides platform specific function to detect boot mode.=0D +#=0D +# Copyright (c) 2020, Rebecca Cran <rebecca@...>=0D +# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>= =0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010005=0D + BASE_NAME =3D PlatformPei=0D + FILE_GUID =3D aa89d903-345b-4ab2-9abf-030b5efb5d50= =0D + MODULE_TYPE =3D PEIM=0D + VERSION_STRING =3D 1.0=0D + ENTRY_POINT =3D InitializePlatform=0D +=0D +#=0D +# The following information is for reference only and not required by the = build tools.=0D +#=0D +# VALID_ARCHITECTURES =3D IA32 X64 EBC=0D +#=0D +=0D +[Sources]=0D + AmdSev.c=0D + ClearCache.c=0D + Cmos.c=0D + Cmos.h=0D + FeatureControl.c=0D + Fv.c=0D + MemDetect.c=0D + Platform.c=0D + Platform.h=0D +=0D +[Packages]=0D + MdePkg/MdePkg.dec=0D + MdeModulePkg/MdeModulePkg.dec=0D + SecurityPkg/SecurityPkg.dec=0D + UefiCpuPkg/UefiCpuPkg.dec=0D + OvmfPkg/OvmfPkg.dec=0D +=0D +[Guids]=0D + gEfiMemoryTypeInformationGuid=0D +=0D +[LibraryClasses]=0D + BaseLib=0D + CacheMaintenanceLib=0D + DebugLib=0D + HobLib=0D + IoLib=0D + PciLib=0D + ResourcePublicationLib=0D + PeiServicesLib=0D + PeiServicesTablePointerLib=0D + PeimEntryPoint=0D + MtrrLib=0D + MemEncryptSevLib=0D + PcdLib=0D + LocalApicLib=0D +=0D +[Pcd]=0D + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfPeiMemFvBase=0D + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfPeiMemFvSize=0D + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvBase=0D + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvSize=0D + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamBase=0D + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamSize=0D + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPageTablesBase=0D + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPageTablesSize=0D + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfLockBoxStorageBase=0D + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfLockBoxStorageSize=0D + gUefiOvmfPkgTokenSpaceGuid.PcdGuidedExtractHandlerTableSize=0D + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfHostBridgePciDevId=0D + gUefiOvmfPkgTokenSpaceGuid.PcdPciIoBase=0D + gUefiOvmfPkgTokenSpaceGuid.PcdPciIoSize=0D + gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio32Base=0D + gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio32Size=0D + gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio64Base=0D + gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio64Size=0D + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDecompressionScratchEnd=0D + gUefiOvmfPkgTokenSpaceGuid.PcdQ35TsegMbytes=0D + gEfiMdePkgTokenSpaceGuid.PcdGuidedExtractHandlerTableAddress=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvStoreReserved=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdSetNxForStack=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiS3Enable=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask=0D + gEfiSecurityPkgTokenSpaceGuid.PcdOptionRomImageVerificationPolicy=0D + gUefiCpuPkgTokenSpaceGuid.PcdCpuLocalApicBaseAddress=0D + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber=0D + gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds=0D + gUefiCpuPkgTokenSpaceGuid.PcdCpuApStackSize=0D +=0D +[FixedPcd]=0D + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress=0D +=0D +[FeaturePcd]=0D + gUefiOvmfPkgTokenSpaceGuid.PcdSmmSmramRequire=0D +=0D +[Ppis]=0D + gEfiPeiMasterBootModePpiGuid=0D + gEfiPeiMpServicesPpiGuid=0D +=0D +[Depex]=0D + TRUE=0D +=0D diff --git a/OvmfPkg/Bhyve/SmbiosPlatformDxe/Bhyve.c b/OvmfPkg/Bhyve/Smbios= PlatformDxe/Bhyve.c new file mode 100644 index 0000000000..6ca976daa6 --- /dev/null +++ b/OvmfPkg/Bhyve/SmbiosPlatformDxe/Bhyve.c @@ -0,0 +1,43 @@ +/*=0D + * Copyright (c) 2020, Rebecca Cran <rebecca@...>=0D + * Copyright (c) 2014, Pluribus Networks, Inc.=0D + *=0D + * SPDX-License-Identifier: BSD-2-Clause-Patent=0D + */=0D +=0D +#include "SmbiosPlatformDxe.h"=0D +=0D +#define BHYVE_SMBIOS_PHYSICAL_ADDRESS 0x000F0000=0D +#define BHYVE_SMBIOS_PHYSICAL_END 0x000FFFFF=0D +=0D +/**=0D + Locates the bhyve SMBIOS data if it exists=0D +=0D + @return SMBIOS_TABLE_ENTRY_POINT Address of bhyve SMBIOS data=0D +=0D +**/=0D +SMBIOS_TABLE_ENTRY_POINT *=0D +GetBhyveSmbiosTables (=0D + VOID=0D + )=0D +{=0D + UINT8 *BhyveSmbiosPtr;=0D + SMBIOS_TABLE_ENTRY_POINT *BhyveSmbiosEntryPointStructure;=0D +=0D + for (BhyveSmbiosPtr =3D (UINT8*)(UINTN) BHYVE_SMBIOS_PHYSICAL_ADDRESS;=0D + BhyveSmbiosPtr < (UINT8*)(UINTN) BHYVE_SMBIOS_PHYSICAL_END;=0D + BhyveSmbiosPtr +=3D 0x10) {=0D +=0D + BhyveSmbiosEntryPointStructure =3D (SMBIOS_TABLE_ENTRY_POINT *) BhyveS= mbiosPtr;=0D +=0D + if (!AsciiStrnCmp ((CHAR8 *) BhyveSmbiosEntryPointStructure->AnchorStr= ing, "_SM_", 4) &&=0D + !AsciiStrnCmp ((CHAR8 *) BhyveSmbiosEntryPointStructure->Intermedi= ateAnchorString, "_DMI_", 5) &&=0D + IsEntryPointStructureValid (BhyveSmbiosEntryPointStructure)) {=0D +=0D + return BhyveSmbiosEntryPointStructure;=0D +=0D + }=0D + }=0D +=0D + return NULL;=0D +}=0D diff --git a/OvmfPkg/Bhyve/SmbiosPlatformDxe/SmbiosPlatformDxe.c b/OvmfPkg/= Bhyve/SmbiosPlatformDxe/SmbiosPlatformDxe.c new file mode 100644 index 0000000000..59f5d77a3b --- /dev/null +++ b/OvmfPkg/Bhyve/SmbiosPlatformDxe/SmbiosPlatformDxe.c @@ -0,0 +1,245 @@ +/** @file=0D + This driver installs SMBIOS information for OVMF=0D +=0D + Copyright (c) 2020, Rebecca Cran <rebecca@...>=0D + Copyright (c) 2011, Bei Guan <gbtju85@...>=0D + Copyright (c) 2011 - 2015, Intel Corporation. All rights reserved.<BR>=0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include "SmbiosPlatformDxe.h"=0D +=0D +#define TYPE0_STRINGS \=0D + "EFI Development Kit II / OVMF\0" /* Vendor */ \=0D + "0.0.0\0" /* BiosVersion */ \=0D + "02/06/2015\0" /* BiosReleaseDate */=0D +//=0D +// Type definition and contents of the default Type 0 SMBIOS table.=0D +//=0D +#pragma pack(1)=0D +typedef struct {=0D + SMBIOS_TABLE_TYPE0 Base;=0D + UINT8 Strings[sizeof(TYPE0_STRINGS)];=0D +} OVMF_TYPE0;=0D +#pragma pack()=0D +=0D +STATIC CONST OVMF_TYPE0 mOvmfDefaultType0 =3D {=0D + {=0D + // SMBIOS_STRUCTURE Hdr=0D + {=0D + EFI_SMBIOS_TYPE_BIOS_INFORMATION, // UINT8 Type=0D + sizeof (SMBIOS_TABLE_TYPE0), // UINT8 Length=0D + },=0D + 1, // SMBIOS_TABLE_STRING Vendor=0D + 2, // SMBIOS_TABLE_STRING BiosVersion=0D + 0xE800,// UINT16 BiosSegment=0D + 3, // SMBIOS_TABLE_STRING BiosReleaseDate=0D + 0, // UINT8 BiosSize=0D + { // MISC_BIOS_CHARACTERISTICS BiosCharacteristics=0D + 0, // Reserved :2=0D + 0, // Unknown :1=0D + 1, // BiosCharacteristicsNotSupported :1=0D + // Remaining BiosCharacteristics bits left unset :60=0D + },=0D + { // BIOSCharacteristicsExtensionBytes[2]=0D + 0, // BiosReserved=0D + 0x1C // SystemReserved =3D VirtualMachineSupported |=0D + // UefiSpecificationSupported |=0D + // TargetContentDistributionEnabled=0D + },=0D + 0, // UINT8 SystemBiosMajorRelease=0D + 0, // UINT8 SystemBiosMinorRelease=0D + 0xFF, // UINT8 EmbeddedControllerFirmwareMajorRel= ease=0D + 0xFF // UINT8 EmbeddedControllerFirmwareMinorRel= ease=0D + },=0D + // Text strings (unformatted area)=0D + TYPE0_STRINGS=0D +};=0D +=0D +=0D +/**=0D + Validates the SMBIOS entry point structure=0D +=0D + @param EntryPointStructure SMBIOS entry point structure=0D +=0D + @retval TRUE The entry point structure is valid=0D + @retval FALSE The entry point structure is not valid=0D +=0D +**/=0D +BOOLEAN=0D +IsEntryPointStructureValid (=0D + IN SMBIOS_TABLE_ENTRY_POINT *EntryPointStructure=0D + )=0D +{=0D + UINTN Index;=0D + UINT8 Length;=0D + UINT8 Checksum;=0D + UINT8 *BytePtr;=0D +=0D + BytePtr =3D (UINT8*) EntryPointStructure;=0D + Length =3D EntryPointStructure->EntryPointLength;=0D + Checksum =3D 0;=0D +=0D + for (Index =3D 0; Index < Length; Index++) {=0D + Checksum =3D Checksum + (UINT8) BytePtr[Index];=0D + }=0D +=0D + if (Checksum !=3D 0) {=0D + return FALSE;=0D + } else {=0D + return TRUE;=0D + }=0D +}=0D +=0D +=0D +/**=0D + Get SMBIOS record length.=0D +=0D + @param SmbiosTable SMBIOS pointer.=0D +=0D +**/=0D +UINTN=0D +SmbiosTableLength (=0D + IN SMBIOS_STRUCTURE_POINTER SmbiosTable=0D + )=0D +{=0D + CHAR8 *AChar;=0D + UINTN Length;=0D +=0D + AChar =3D (CHAR8 *)(SmbiosTable.Raw + SmbiosTable.Hdr->Length);=0D +=0D + //=0D + // Each structure shall be terminated by a double-null (SMBIOS spec.7.1)= =0D + //=0D + while ((*AChar !=3D 0) || (*(AChar + 1) !=3D 0)) {=0D + AChar ++;=0D + }=0D + Length =3D ((UINTN)AChar - (UINTN)SmbiosTable.Raw + 2);=0D +=0D + return Length;=0D +}=0D +=0D +=0D +/**=0D + Install all structures from the given SMBIOS structures block=0D +=0D + @param Smbios SMBIOS protocol=0D + @param TableAddress SMBIOS tables starting address=0D +=0D +**/=0D +EFI_STATUS=0D +InstallAllStructures (=0D + IN EFI_SMBIOS_PROTOCOL *Smbios,=0D + IN UINT8 *TableAddress=0D + )=0D +{=0D + EFI_STATUS Status;=0D + SMBIOS_STRUCTURE_POINTER SmbiosTable;=0D + EFI_SMBIOS_HANDLE SmbiosHandle;=0D + BOOLEAN NeedSmbiosType0;=0D +=0D + SmbiosTable.Raw =3D TableAddress;=0D + if (SmbiosTable.Raw =3D=3D NULL) {=0D + return EFI_INVALID_PARAMETER;=0D + }=0D +=0D + NeedSmbiosType0 =3D TRUE;=0D +=0D + while (SmbiosTable.Hdr->Type !=3D 127) {=0D + //=0D + // Log the SMBIOS data for this structure=0D + //=0D + SmbiosHandle =3D SmbiosTable.Hdr->Handle;=0D + Status =3D Smbios->Add (=0D + Smbios,=0D + NULL,=0D + &SmbiosHandle,=0D + (EFI_SMBIOS_TABLE_HEADER*) SmbiosTable.Raw=0D + );=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + if (SmbiosTable.Hdr->Type =3D=3D 0) {=0D + NeedSmbiosType0 =3D FALSE;=0D + }=0D +=0D + //=0D + // Get the next structure address=0D + //=0D + SmbiosTable.Raw =3D (UINT8 *)(SmbiosTable.Raw + SmbiosTableLength (Smb= iosTable));=0D + }=0D +=0D + if (NeedSmbiosType0) {=0D + //=0D + // Add OVMF default Type 0 (BIOS Information) table=0D + //=0D + SmbiosHandle =3D SMBIOS_HANDLE_PI_RESERVED;=0D + Status =3D Smbios->Add (=0D + Smbios,=0D + NULL,=0D + &SmbiosHandle,=0D + (EFI_SMBIOS_TABLE_HEADER*) &mOvmfDefaultType0=0D + );=0D + ASSERT_EFI_ERROR (Status);=0D + }=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D +=0D +/**=0D + Installs SMBIOS information for OVMF=0D +=0D + @param ImageHandle Module's image handle=0D + @param SystemTable Pointer of EFI_SYSTEM_TABLE=0D +=0D + @retval EFI_SUCCESS Smbios data successfully installed=0D + @retval Other Smbios data was not installed=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +SmbiosTablePublishEntry (=0D + IN EFI_HANDLE ImageHandle,=0D + IN EFI_SYSTEM_TABLE *SystemTable=0D + )=0D +{=0D + EFI_STATUS Status;=0D + EFI_SMBIOS_PROTOCOL *Smbios;=0D + SMBIOS_TABLE_ENTRY_POINT *EntryPointStructure;=0D + UINT8 *SmbiosTables =3D NULL;=0D +=0D + //=0D + // Find the SMBIOS protocol=0D + //=0D + Status =3D gBS->LocateProtocol (=0D + &gEfiSmbiosProtocolGuid,=0D + NULL,=0D + (VOID**)&Smbios=0D + );=0D + if (EFI_ERROR (Status)) {=0D + return Status;=0D + }=0D +=0D + //=0D + // Add bhyve SMBIOS data=0D + //=0D + EntryPointStructure =3D GetBhyveSmbiosTables ();=0D + if (EntryPointStructure !=3D NULL) {=0D + SmbiosTables =3D (UINT8*)(UINTN)EntryPointStructure->TableAddress;=0D + }=0D +=0D + if (SmbiosTables !=3D NULL) {=0D + Status =3D InstallAllStructures (Smbios, SmbiosTables);=0D +=0D + //=0D + // Free SmbiosTables if allocated by Qemu (i.e., NOT by Xen):=0D + //=0D + if (EntryPointStructure =3D=3D NULL) {=0D + FreePool (SmbiosTables);=0D + }=0D + }=0D +=0D + return Status;=0D +}=0D diff --git a/OvmfPkg/Bhyve/SmbiosPlatformDxe/SmbiosPlatformDxe.h b/OvmfPkg/= Bhyve/SmbiosPlatformDxe/SmbiosPlatformDxe.h new file mode 100644 index 0000000000..1971827be4 --- /dev/null +++ b/OvmfPkg/Bhyve/SmbiosPlatformDxe/SmbiosPlatformDxe.h @@ -0,0 +1,52 @@ +/** @file=0D + This driver installs SMBIOS information for OVMF=0D +=0D + Copyright (c) 2020, Rebecca Cran <rebecca@...>=0D + Copyright (c) 2011, Bei Guan <gbtju85@...>=0D + Copyright (c) 2011, Intel Corporation. All rights reserved.<BR>=0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#ifndef _SMBIOS_PLATFORM_DXE_H_=0D +#define _SMBIOS_PLATFORM_DXE_H_=0D +=0D +#include <PiDxe.h>=0D +=0D +#include <Protocol/Smbios.h>=0D +#include <IndustryStandard/SmBios.h>=0D +#include <Library/DebugLib.h>=0D +#include <Library/BaseLib.h>=0D +#include <Library/BaseMemoryLib.h>=0D +#include <Library/UefiBootServicesTableLib.h>=0D +#include <Library/MemoryAllocationLib.h>=0D +=0D +=0D +/**=0D + Locates the bhyve SMBIOS data if it exists=0D +=0D + @return SMBIOS_TABLE_ENTRY_POINT Address of bhyve SMBIOS data=0D +=0D +**/=0D +SMBIOS_TABLE_ENTRY_POINT *=0D +GetBhyveSmbiosTables (=0D + VOID=0D + );=0D +=0D +=0D +/**=0D + Validates the SMBIOS entry point structure=0D +=0D + @param EntryPointStructure SMBIOS entry point structure=0D +=0D + @retval TRUE The entry point structure is valid=0D + @retval FALSE The entry point structure is not valid=0D +=0D +**/=0D +BOOLEAN=0D +IsEntryPointStructureValid (=0D + IN SMBIOS_TABLE_ENTRY_POINT *EntryPointStructure=0D + );=0D +=0D +#endif=0D diff --git a/OvmfPkg/Bhyve/SmbiosPlatformDxe/SmbiosPlatformDxe.inf b/OvmfPk= g/Bhyve/SmbiosPlatformDxe/SmbiosPlatformDxe.inf new file mode 100644 index 0000000000..a4cc6e7a56 --- /dev/null +++ b/OvmfPkg/Bhyve/SmbiosPlatformDxe/SmbiosPlatformDxe.inf @@ -0,0 +1,55 @@ +## @file=0D +# This driver installs SMBIOS information for bhyve=0D +#=0D +# Copyright (c) 2020, Rebecca Cran <rebecca@...>=0D +# Copyright (c) 2011, Bei Guan <gbtju85@...>=0D +# Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR>= =0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010005=0D + BASE_NAME =3D SmbiosPlatformDxe=0D + FILE_GUID =3D e2d8a63c-c239-484f-bb21-2917843cc382= =0D + MODULE_TYPE =3D DXE_DRIVER=0D + VERSION_STRING =3D 1.0=0D +=0D + ENTRY_POINT =3D SmbiosTablePublishEntry=0D +=0D +#=0D +# The following information is for reference only and not required by the = build tools.=0D +#=0D +# VALID_ARCHITECTURES =3D IA32 X64 EBC ARM AARCH64=0D +#=0D +=0D +[Sources]=0D + SmbiosPlatformDxe.h=0D + SmbiosPlatformDxe.c=0D + Bhyve.c=0D +=0D +[Packages]=0D + MdePkg/MdePkg.dec=0D + MdeModulePkg/MdeModulePkg.dec=0D + OvmfPkg/OvmfPkg.dec=0D +=0D +[LibraryClasses]=0D + UefiBootServicesTableLib=0D + BaseMemoryLib=0D + BaseLib=0D + UefiDriverEntryPoint=0D + DebugLib=0D + HobLib=0D + MemoryAllocationLib=0D + PcdLib=0D +=0D +[Pcd]=0D + gUefiOvmfPkgTokenSpaceGuid.PcdQemuSmbiosValidated=0D +=0D +[Protocols]=0D + gEfiSmbiosProtocolGuid # PROTOCOL ALWAYS_CONSUMED=0D +=0D +[Depex]=0D + gEfiSmbiosProtocolGuid=0D +=0D diff --git a/OvmfPkg/Bhyve/VarStore.fdf.inc b/OvmfPkg/Bhyve/VarStore.fdf.inc new file mode 100644 index 0000000000..a1e524e393 --- /dev/null +++ b/OvmfPkg/Bhyve/VarStore.fdf.inc @@ -0,0 +1,115 @@ +## @file=0D +# FDF include file with Layout Regions that define an empty variable stor= e.=0D +#=0D +# Copyright (C) 2014, Red Hat, Inc.=0D +# Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>= =0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +!if ($(FD_SIZE_IN_KB) =3D=3D 1024) || ($(FD_SIZE_IN_KB) =3D=3D 2048)=0D +0x00000000|0x0000e000=0D +!endif=0D +!if $(FD_SIZE_IN_KB) =3D=3D 4096=0D +0x00000000|0x00040000=0D +!endif=0D +#NV_VARIABLE_STORE=0D +DATA =3D {=0D + ## This is the EFI_FIRMWARE_VOLUME_HEADER=0D + # ZeroVector []=0D + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,=0D + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,=0D + # FileSystemGuid: gEfiSystemNvDataFvGuid =3D=0D + # { 0xFFF12B8D, 0x7696, 0x4C8B,=0D + # { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }}=0D + 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,=0D + 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,=0D +!if ($(FD_SIZE_IN_KB) =3D=3D 1024) || ($(FD_SIZE_IN_KB) =3D=3D 2048)=0D + # FvLength: 0x20000=0D + 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00,=0D +!endif=0D +!if $(FD_SIZE_IN_KB) =3D=3D 4096=0D + # FvLength: 0x84000=0D + 0x00, 0x40, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00,=0D +!endif=0D + # Signature "_FVH" # Attributes=0D + 0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00,=0D + # HeaderLength=0D + 0x48, 0x00,=0D +!if ($(FD_SIZE_IN_KB) =3D=3D 1024) || ($(FD_SIZE_IN_KB) =3D=3D 2048)=0D + # CheckSum=0D + 0x19, 0xF9,=0D +!endif=0D +!if $(FD_SIZE_IN_KB) =3D=3D 4096=0D + # CheckSum=0D + 0xAF, 0xB8,=0D +!endif=0D + # ExtHeaderOffset #Reserved #Revision=0D + 0x00, 0x00, 0x00, 0x02,=0D +!if ($(FD_SIZE_IN_KB) =3D=3D 1024) || ($(FD_SIZE_IN_KB) =3D=3D 2048)=0D + # Blockmap[0]: 0x20 Blocks * 0x1000 Bytes / Block=0D + 0x20, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00,=0D +!endif=0D +!if $(FD_SIZE_IN_KB) =3D=3D 4096=0D + # Blockmap[0]: 0x84 Blocks * 0x1000 Bytes / Block=0D + 0x84, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00,=0D +!endif=0D + # Blockmap[1]: End=0D + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,=0D + ## This is the VARIABLE_STORE_HEADER=0D + # It is compatible with SECURE_BOOT_ENABLE =3D=3D FALSE as well.=0D + # Signature: gEfiAuthenticatedVariableGuid =3D=0D + # { 0xaaf32c78, 0x947b, 0x439a,=0D + # { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }}=0D + 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43,=0D + 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92,=0D +!if ($(FD_SIZE_IN_KB) =3D=3D 1024) || ($(FD_SIZE_IN_KB) =3D=3D 2048)=0D + # Size: 0xe000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariable= Size) -=0D + # 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) =3D 0xdfb8=0D + # This can speed up the Variable Dispatch a bit.=0D + 0xB8, 0xDF, 0x00, 0x00,=0D +!endif=0D +!if $(FD_SIZE_IN_KB) =3D=3D 4096=0D + # Size: 0x40000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariabl= eSize) -=0D + # 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) =3D 0x3ffb8=0D + # This can speed up the Variable Dispatch a bit.=0D + 0xB8, 0xFF, 0x03, 0x00,=0D +!endif=0D + # FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32=0D + 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00=0D +}=0D +=0D +!if ($(FD_SIZE_IN_KB) =3D=3D 1024) || ($(FD_SIZE_IN_KB) =3D=3D 2048)=0D +0x0000e000|0x00001000=0D +!endif=0D +!if $(FD_SIZE_IN_KB) =3D=3D 4096=0D +0x00040000|0x00001000=0D +!endif=0D +#NV_EVENT_LOG=0D +=0D +!if ($(FD_SIZE_IN_KB) =3D=3D 1024) || ($(FD_SIZE_IN_KB) =3D=3D 2048)=0D +0x0000f000|0x00001000=0D +!endif=0D +!if $(FD_SIZE_IN_KB) =3D=3D 4096=0D +0x00041000|0x00001000=0D +!endif=0D +#NV_FTW_WORKING=0D +DATA =3D {=0D + # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature =3D gEdkiiWorkingBl= ockSignatureGuid =3D=0D + # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0= x1b, 0x95 }}=0D + 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49,=0D + 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95,=0D + # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Res= erved=0D + 0x2c, 0xaf, 0x2c, 0x64, 0xFE, 0xFF, 0xFF, 0xFF,=0D + # WriteQueueSize: UINT64=0D + 0xE0, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00=0D +}=0D +=0D +!if ($(FD_SIZE_IN_KB) =3D=3D 1024) || ($(FD_SIZE_IN_KB) =3D=3D 2048)=0D +0x00010000|0x00010000=0D +!endif=0D +!if $(FD_SIZE_IN_KB) =3D=3D 4096=0D +0x00042000|0x00042000=0D +!endif=0D +#NV_FTW_SPARE=0D --=20 2.25.1 |
|
|