[PATCH edk2-platforms v3 14/24] Silicon/NXP: Use Clock retrieval PPI in modules


Pankaj Bansal
 

From: Pankaj Bansal <pankaj.bansal@...>

Use NXP_PLATFORM_GET_CLOCK_PPI in various Layerscape IP modules.

Signed-off-by: Pankaj Bansal <pankaj.bansal@...>
---

Notes:
- Added clock retrieval APIs to DUartPortLib

Silicon/NXP/NxpQoriqLs.dec | 5 ----
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 2 --
Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf | 2 +-
Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf | 5 ++--
Silicon/NXP/Library/SocLib/LS1043aSocLib.inf | 1 -
Silicon/NXP/Drivers/I2cDxe/I2cDxe.h | 6 ----
Silicon/NXP/Include/Chassis2/NxpSoc.h | 9 ------
Silicon/NXP/Library/DUartPortLib/DUart.h | 8 +----
Silicon/NXP/Drivers/I2cDxe/I2cDxe.c | 3 +-
Silicon/NXP/Library/DUartPortLib/DUartPortLib.c | 7 ++---
Silicon/NXP/Library/SocLib/Chassis.c | 15 ----------
Silicon/NXP/Library/SocLib/Chassis2/Soc.c | 31 --------------------
12 files changed, 9 insertions(+), 85 deletions(-)

diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
index b478560450b3..2ac047a89274 100644
--- a/Silicon/NXP/NxpQoriqLs.dec
+++ b/Silicon/NXP/NxpQoriqLs.dec
@@ -22,11 +22,6 @@
gNxpNonDiscoverableI2cMasterGuid = { 0x5f2c099c, 0x54a3, 0x4dd4, {0x9e, 0xc5, 0xe9, 0x12, 0x8c, 0x36, 0x81, 0x6a}}

[PcdsFixedAtBuild.common]
- #
- # Platform PCDs
- #
- gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x0|UINT32|0x00000250
-
#
# Pcds to support Big Endian IPs
#
diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
index e5383aaf0cc5..d486c9b36fab 100644
--- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
+++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
@@ -39,8 +39,6 @@
gArmTokenSpaceGuid.PcdSystemMemorySize|0x7BE00000
gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x02000000

- gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x1
-
#
# RTC Pcds
#
diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
index 867376044656..3bf7a8124fc6 100644
--- a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
+++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
@@ -25,13 +25,13 @@

[LibraryClasses]
ArmLib
+ ArmPlatformLib
BaseMemoryLib
DevicePathLib
I2cLib
IoLib
MemoryAllocationLib
PcdLib
- SocLib
TimerLib
UefiBootServicesTableLib
UefiDriverEntryPoint
diff --git a/Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf b/Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
index 7a2fa619b027..b8a77ae05243 100644
--- a/Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
+++ b/Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
@@ -3,7 +3,7 @@
# Component description file for DUartPortLib module
#
# Copyright (c) 2013, Freescale Ltd. All rights reserved.
-# Copyright 2017 NXP
+# Copyright 2017, 2020 NXP
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -20,8 +20,8 @@
DUartPortLib.c

[LibraryClasses]
+ ArmPlatformLib
PcdLib
- SocLib

[Packages]
MdeModulePkg/MdeModulePkg.dec
@@ -31,4 +31,3 @@
[Pcd]
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
- gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv
diff --git a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
index 3d38a7e58b91..bb15e0a3d710 100644
--- a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
+++ b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
@@ -36,4 +36,3 @@
[FixedPcd]
gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian
- gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv
diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h
index 88316f313380..7c4a306c16a0 100644
--- a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h
+++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h
@@ -37,12 +37,6 @@ typedef struct {
NON_DISCOVERABLE_DEVICE *Dev;
} NXP_I2C_MASTER;

-extern
-UINT64
-GetBusFrequency (
- VOID
- );
-
EFI_STATUS
NxpI2cInit (
IN EFI_HANDLE DriverBindingHandle,
diff --git a/Silicon/NXP/Include/Chassis2/NxpSoc.h b/Silicon/NXP/Include/Chassis2/NxpSoc.h
index 6812beafe447..3f00a2614131 100644
--- a/Silicon/NXP/Include/Chassis2/NxpSoc.h
+++ b/Silicon/NXP/Include/Chassis2/NxpSoc.h
@@ -27,10 +27,6 @@
#define SACR_PAGESIZE_MASK 0x00010000
#define IDR1_PAGESIZE_MASK 0x80000000

-typedef struct {
- UINTN FreqSystemBus;
-} SYS_INFO;
-
/* Device Configuration and Pin Control */
typedef struct {
UINT8 Res0[0x100-0x00];
@@ -39,11 +35,6 @@ typedef struct {
#define CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK 0x1f
} CCSR_GUR;

-VOID
-GetSysInfo (
- OUT SYS_INFO *
- );
-
UINT32
EFIAPI
GurRead (
diff --git a/Silicon/NXP/Library/DUartPortLib/DUart.h b/Silicon/NXP/Library/DUartPortLib/DUart.h
index c71e2ce55d1d..aca7cd8d3f01 100644
--- a/Silicon/NXP/Library/DUartPortLib/DUart.h
+++ b/Silicon/NXP/Library/DUartPortLib/DUart.h
@@ -5,7 +5,7 @@
*
* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
-* Copyright 2017 NXP
+* Copyright 2017, 2020 NXP
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
@@ -113,10 +113,4 @@
#define USCR 0x7
#define UDSR 0x10

-extern
-UINT64
-GetBusFrequency (
- VOID
- );
-
#endif /* DUART_H_ */
diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
index a5aba47b3ed4..30804450d2b7 100644
--- a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
+++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
@@ -17,6 +17,7 @@
#include <Library/UefiBootServicesTableLib.h>
#include <Library/UefiLib.h>
#include <Library/UefiRuntimeLib.h>
+#include <Ppi/NxpPlatformGetClock.h>

#include "I2cDxe.h"

@@ -51,7 +52,7 @@ SetBusFrequency (

I2cBase = (UINTN)(I2c->Dev->Resources[0].AddrRangeMin);

- I2cClock = GetBusFrequency ();
+ I2cClock = gPlatformGetClockPpi.PlatformGetClock (NXP_I2C_CLOCK, 0);

I2cInitialize (I2cBase, I2cClock, *BusClockHertz);

diff --git a/Silicon/NXP/Library/DUartPortLib/DUartPortLib.c b/Silicon/NXP/Library/DUartPortLib/DUartPortLib.c
index c3c738d3cca8..f9c2c44a4c3b 100644
--- a/Silicon/NXP/Library/DUartPortLib/DUartPortLib.c
+++ b/Silicon/NXP/Library/DUartPortLib/DUartPortLib.c
@@ -6,7 +6,7 @@
Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
Copyright (c) 2012 - 2013, ARM Ltd. All rights reserved.<BR>
Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
- Copyright 2017 NXP
+ Copyright 2017, 2020 NXP

SPDX-License-Identifier: BSD-2-Clause-Patent

@@ -16,6 +16,7 @@
#include <Library/IoLib.h>
#include <Library/PcdLib.h>
#include <Library/SerialPortLib.h>
+#include <Ppi/NxpPlatformGetClock.h>

#include "DUart.h"

@@ -169,10 +170,8 @@ CalculateBaudDivisor (
)
{
UINTN DUartClk;
- UINTN FreqSystemBus;

- FreqSystemBus = GetBusFrequency ();
- DUartClk = FreqSystemBus/PcdGet32(PcdPlatformFreqDiv);
+ DUartClk = gPlatformGetClockPpi.PlatformGetClock (NXP_UART_CLOCK, 0);

return ((DUartClk)/(BaudRate * 16));
}
diff --git a/Silicon/NXP/Library/SocLib/Chassis.c b/Silicon/NXP/Library/SocLib/Chassis.c
index 1ef99e8de25f..90677f0f36ca 100644
--- a/Silicon/NXP/Library/SocLib/Chassis.c
+++ b/Silicon/NXP/Library/SocLib/Chassis.c
@@ -37,21 +37,6 @@ GurRead (
}
}

-/*
- * Return system bus frequency
- */
-UINT64
-GetBusFrequency (
- VOID
- )
-{
- SYS_INFO SocSysInfo;
-
- GetSysInfo (&SocSysInfo);
-
- return SocSysInfo.FreqSystemBus;
-}
-
/*
* Setup SMMU in bypass mode
* and also set its pagesize
diff --git a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
index 480d8d18fb9f..b14ada7f595d 100644
--- a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
+++ b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
@@ -21,37 +21,6 @@
#include <Library/SocLib.h>
#include <Soc.h>

-/**
- Calculate the frequency of various controllers and
- populate the passed structure with frequuencies.
-
- @param PtrSysInfo Input structure to populate with
- frequencies.
-**/
-VOID
-GetSysInfo (
- OUT SYS_INFO *PtrSysInfo
- )
-{
- CCSR_GUR *GurBase;
- UINTN SysClk;
-
- GurBase = (CCSR_GUR *)CHASSIS2_DCFG_ADDRESS;
- SysClk = CLK_FREQ;
-
- SetMem (PtrSysInfo, sizeof (SYS_INFO), 0);
-
- PtrSysInfo->FreqSystemBus = SysClk;
-
- //
- // selects the platform clock:SYSCLK ratio and calculate
- // system frequency
- //
- PtrSysInfo->FreqSystemBus *= (GurRead ((UINTN)&GurBase->RcwSr[0]) >>
- CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
- CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
-}
-
/**
Return the input clock frequency to an IP Module.
This function reads the RCW bits and calculates the PLL multipler/divider
--
2.17.1

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