[PATCH 05/19] NXP/BaseSerialPortLib16550: remove SerialPortInitalize functionality


Pankaj Bansal
 

SerialPortInitalize is called from DebugLib constructor. so this gets
called for each of the module in system. now, during SerialPortInitalize,
we need the Uart clock to set it's baud rate.

This Uart clock retrieval is implemented in SocLib and it usually involves
reading SysClock information (from FPGA or from clock generator)

so it's an unnecessary overhead, that can be avoided because we have
already initalized SerialPort in SEC phase.

Therefore, return SUCCESS from SerialPortInitalize everytime, without doing
anything.

In SEC phase we use SerialPortSetAttributes with default parameters to
mimic SerialPortInitalize.

Signed-off-by: Pankaj Bansal <pankaj.bansal@...>
---
.../BaseSerialPortLib16550.c | 109 ++++--------------
Silicon/NXP/Library/SocLib/Chassis2/Soc.c | 25 +++-
Silicon/NXP/Library/SocLib/LS1043aSocLib.inf | 6 +-
3 files changed, 51 insertions(+), 89 deletions(-)

diff --git a/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c b/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c
index 2c5c54ac7d..6b2aa46ff6 100644
--- a/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c
+++ b/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c
@@ -176,92 +176,6 @@ SerialPortInitialize (
VOID
)
{
- UINTN SerialRegisterBase;
- UINT32 Divisor;
- UINT32 CurrentDivisor;
- BOOLEAN Initialized;
- UINT64 SerialClock;
-
- //
- // Perform platform specific initialization required to enable use of the 16550 device
- // at the location specified by PcdSerialUseMmio and PcdSerialRegisterBase.
- //
- SerialClock = GetBusFrequency ();
- if (SerialClock == 0) {
- return EFI_DEVICE_ERROR;
- }
-
- //
- // Calculate divisor for baud generator
- // Ref_Clk_Rate / Baud_Rate / 16
- //
- Divisor = SerialClock / (PcdGet32 (PcdSerialBaudRate) * 16);
- if ((SerialClock % (PcdGet32 (PcdSerialBaudRate) * 16)) >= PcdGet32 (PcdSerialBaudRate) * 8) {
- Divisor++;
- }
-
- //
- // Get the base address of the serial port in either I/O or MMIO space
- //
- SerialRegisterBase = GetSerialRegisterBase ();
- if (SerialRegisterBase == 0) {
- return RETURN_DEVICE_ERROR;
- }
-
- //
- // See if the serial port is already initialized
- //
- Initialized = TRUE;
- if ((SerialPortReadRegister (SerialRegisterBase, R_UART_LCR) & 0x3F) != (PcdGet8 (PcdSerialLineControl) & 0x3F)) {
- Initialized = FALSE;
- }
- SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR, (UINT8)(SerialPortReadRegister (SerialRegisterBase, R_UART_LCR) | B_UART_LCR_DLAB));
- CurrentDivisor = SerialPortReadRegister (SerialRegisterBase, R_UART_BAUD_HIGH) << 8;
- CurrentDivisor |= (UINT32) SerialPortReadRegister (SerialRegisterBase, R_UART_BAUD_LOW);
- SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR, (UINT8)(SerialPortReadRegister (SerialRegisterBase, R_UART_LCR) & ~B_UART_LCR_DLAB));
- if (CurrentDivisor != Divisor) {
- Initialized = FALSE;
- }
- if (Initialized) {
- return RETURN_SUCCESS;
- }
-
- //
- // Wait for the serial port to be ready.
- // Verify that both the transmit FIFO and the shift register are empty.
- //
- while ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) & (B_UART_LSR_TEMT | B_UART_LSR_TXRDY)) != (B_UART_LSR_TEMT | B_UART_LSR_TXRDY));
-
- //
- // Configure baud rate
- //
- SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR, B_UART_LCR_DLAB);
- SerialPortWriteRegister (SerialRegisterBase, R_UART_BAUD_HIGH, (UINT8) (Divisor >> 8));
- SerialPortWriteRegister (SerialRegisterBase, R_UART_BAUD_LOW, (UINT8) (Divisor & 0xff));
-
- //
- // Clear DLAB and configure Data Bits, Parity, and Stop Bits.
- // Strip reserved bits from PcdSerialLineControl
- //
- SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR, (UINT8)(PcdGet8 (PcdSerialLineControl) & 0x3F));
-
- //
- // Enable and reset FIFOs
- // Strip reserved bits from PcdSerialFifoControl
- //
- SerialPortWriteRegister (SerialRegisterBase, R_UART_FCR, 0x00);
- SerialPortWriteRegister (SerialRegisterBase, R_UART_FCR, (UINT8)(PcdGet8 (PcdSerialFifoControl) & (B_UART_FCR_FIFOE | B_UART_FCR_FIFO64)));
-
- //
- // Set FIFO Polled Mode by clearing IER after setting FCR
- //
- SerialPortWriteRegister (SerialRegisterBase, R_UART_IER, 0x00);
-
- //
- // Put Modem Control Register(MCR) into its reset state of 0x00.
- //
- SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, 0x00);
-
return RETURN_SUCCESS;
}

@@ -785,6 +699,12 @@ SerialPortSetAttributes (
Divisor++;
}

+ //
+ // Wait for the serial port to be ready.
+ // Verify that both the transmit FIFO and the shift register are empty.
+ //
+ while ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) & (B_UART_LSR_TEMT | B_UART_LSR_TXRDY)) != (B_UART_LSR_TEMT | B_UART_LSR_TXRDY));
+
//
// Configure baud rate
//
@@ -799,6 +719,23 @@ SerialPortSetAttributes (
Lcr = (UINT8) ((LcrParity << 3) | (LcrStop << 2) | LcrData);
SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR, (UINT8) (Lcr & 0x3F));

+ //
+ // Enable and reset FIFOs
+ // Strip reserved bits from PcdSerialFifoControl
+ //
+ SerialPortWriteRegister (SerialRegisterBase, R_UART_FCR, 0x00);
+ SerialPortWriteRegister (SerialRegisterBase, R_UART_FCR, (UINT8)(PcdGet8 (PcdSerialFifoControl) & (B_UART_FCR_FIFOE | B_UART_FCR_FIFO64)));
+
+ //
+ // Set FIFO Polled Mode by clearing IER after setting FCR
+ //
+ SerialPortWriteRegister (SerialRegisterBase, R_UART_IER, 0x00);
+
+ //
+ // Put Modem Control Register(MCR) into its reset state of 0x00.
+ //
+ SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, 0x00);
+
return RETURN_SUCCESS;
}

diff --git a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
index bfb8b8cb33..5a1a7376cd 100644
--- a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
+++ b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
@@ -1,7 +1,7 @@
/** @Soc.c
SoC specific Library containg functions to initialize various SoC components

- Copyright 2017-2019 NXP
+ Copyright 2017-2020 NXP

SPDX-License-Identifier: BSD-2-Clause-Patent

@@ -141,12 +141,33 @@ SocInit (
VOID
)
{
+ UINT64 BaudRate;
+ UINT32 ReceiveFifoDepth;
+ EFI_PARITY_TYPE Parity;
+ UINT8 DataBits;
+ EFI_STOP_BITS_TYPE StopBits;
+ UINT32 Timeout;
+
+ BaudRate = FixedPcdGet64 (PcdUartDefaultBaudRate);
+ ReceiveFifoDepth = 0; // Use default FIFO depth
+ Timeout = 0;
+ Parity = (EFI_PARITY_TYPE)FixedPcdGet8 (PcdUartDefaultParity);
+ DataBits = FixedPcdGet8 (PcdUartDefaultDataBits);
+ StopBits = (EFI_STOP_BITS_TYPE) FixedPcdGet8 (PcdUartDefaultStopBits);
+
SmmuInit ();

//
// Early init serial Port to get board information.
//
- SerialPortInitialize ();
+ SerialPortSetAttributes (
+ &BaudRate,
+ &ReceiveFifoDepth,
+ &Timeout,
+ &Parity,
+ &DataBits,
+ &StopBits
+ );
DEBUG ((DEBUG_INIT, "\nUEFI firmware (version %s built at %a on %a)\n",
(CHAR16*)PcdGetPtr (PcdFirmwareVersionString), __TIME__, __DATE__));

diff --git a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
index cb670a1279..3334d4d4f1 100644
--- a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
+++ b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
@@ -1,6 +1,6 @@
# @file
#
-# Copyright 2017-2019 NXP
+# Copyright 2017-2020 NXP
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -36,6 +36,10 @@
GCC:*_*_*_CC_FLAGS = -DCHASSIS2

[FixedPcd]
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits
gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr
gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian
--
2.17.1

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