[PATCH 2/3] ARM/Assembler: Correct syntax from RVCT for MSFT


Baptiste Gerondeau
 

From: Baptiste GERONDEAU <bgerondeau@gmail.com>

RVCT and MSFT's ARM assembler share the same file syntax, but some
instructions use pre-UAL syntax that is not picked up
by MSFT's ARM assembler, this commit translates those instructions
into MSFT-buildable ones (subset of UAL/THUMB).

Signed-off-by: Baptiste Gerondeau <baptiste.gerondeau@linaro.org>
---
ArmPkg/Library/ArmExceptionLib/Arm/ExceptionSupport.asm | 30 +++++++++++++=
++++-------------
ArmPkg/Library/ArmLib/Arm/ArmV7Support.asm | 6 ++++--
MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.asm | 18 +++++++++----=
-----
3 files changed, 30 insertions(+), 24 deletions(-)

diff --git a/ArmPkg/Library/ArmExceptionLib/Arm/ExceptionSupport.asm b/ArmP=
kg/Library/ArmExceptionLib/Arm/ExceptionSupport.asm
index aa0229d2e85f..880246bd6206 100644
--- a/ArmPkg/Library/ArmExceptionLib/Arm/ExceptionSupport.asm
+++ b/ArmPkg/Library/ArmExceptionLib/Arm/ExceptionSupport.asm
@@ -90,7 +90,7 @@ Fiq
ResetEntry=0D
srsfd #0x13! ; Store return state on SVC stack=0D
; We are already in SVC mode=0D
- stmfd SP!,{LR} ; Store the link register for the cu=
rrent mode=0D
+ push {LR} ; Store the link register for the cu=
rrent mode=0D
sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - =
CPSR=0D
stmfd SP!,{R0-R12} ; Store the register state=0D
=0D
@@ -102,7 +102,7 @@ UndefinedInstructionEntry
sub LR, LR, #4 ; Only -2 for Thumb, adjust in Commo=
nExceptionEntry=0D
srsfd #0x13! ; Store return state on SVC stack=0D
cps #0x13 ; Switch to SVC for common stack=0D
- stmfd SP!,{LR} ; Store the link register for the cu=
rrent mode=0D
+ push {LR} ; Store the link register for the cu=
rrent mode=0D
sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - =
CPSR=0D
stmfd SP!,{R0-R12} ; Store the register state=0D
=0D
@@ -113,7 +113,7 @@ UndefinedInstructionEntry
SoftwareInterruptEntry=0D
srsfd #0x13! ; Store return state on SVC stack=0D
; We are already in SVC mode=0D
- stmfd SP!,{LR} ; Store the link register for the cu=
rrent mode=0D
+ push {LR} ; Store the link register for the cu=
rrent mode=0D
sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - =
CPSR=0D
stmfd SP!,{R0-R12} ; Store the register state=0D
=0D
@@ -125,7 +125,7 @@ PrefetchAbortEntry
sub LR,LR,#4=0D
srsfd #0x13! ; Store return state on SVC stack=0D
cps #0x13 ; Switch to SVC for common stack=0D
- stmfd SP!,{LR} ; Store the link register for the cu=
rrent mode=0D
+ push {LR} ; Store the link register for the cu=
rrent mode=0D
sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - =
CPSR=0D
stmfd SP!,{R0-R12} ; Store the register state=0D
=0D
@@ -137,7 +137,7 @@ DataAbortEntry
sub LR,LR,#8=0D
srsfd #0x13! ; Store return state on SVC stack=0D
cps #0x13 ; Switch to SVC for common stack=0D
- stmfd SP!,{LR} ; Store the link register for the cu=
rrent mode=0D
+ push {LR} ; Store the link register for the cu=
rrent mode=0D
sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - =
CPSR=0D
stmfd SP!,{R0-R12} ; Store the register state=0D
=0D
@@ -148,7 +148,7 @@ DataAbortEntry
ReservedExceptionEntry=0D
srsfd #0x13! ; Store return state on SVC stack=0D
cps #0x13 ; Switch to SVC for common stack=0D
- stmfd SP!,{LR} ; Store the link register for the cu=
rrent mode=0D
+ push {LR} ; Store the link register for the cu=
rrent mode=0D
sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - =
CPSR=0D
stmfd SP!,{R0-R12} ; Store the register state=0D
=0D
@@ -160,7 +160,7 @@ IrqEntry
sub LR,LR,#4=0D
srsfd #0x13! ; Store return state on SVC stack=0D
cps #0x13 ; Switch to SVC for common stack=0D
- stmfd SP!,{LR} ; Store the link register for the cu=
rrent mode=0D
+ push {LR} ; Store the link register for the cu=
rrent mode=0D
sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - =
CPSR=0D
stmfd SP!,{R0-R12} ; Store the register state=0D
=0D
@@ -172,7 +172,7 @@ FiqEntry
sub LR,LR,#4=0D
srsfd #0x13! ; Store return state on SVC stack=0D
cps #0x13 ; Switch to SVC for common stack=0D
- stmfd SP!,{LR} ; Store the link register for the cu=
rrent mode=0D
+ push {LR} ; Store the link register for the cu=
rrent mode=0D
sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - =
CPSR=0D
stmfd SP!,{R0-R12} ; Store the register state=0D
; Since we have already switch to SV=
C R8_fiq - R12_fiq=0D
@@ -213,9 +213,11 @@ AsmCommonExceptionEntry
and R3, R1, #0x1f ; Check CPSR to see if User or System =
Mode=0D
cmp R3, #0x1f ; if ((CPSR =3D=3D 0x10) || (CPSR =3D=
=3D 0x1f))=0D
cmpne R3, #0x10 ;=0D
- stmeqed R2, {lr}^ ; save unbanked lr=0D
+ mrseq R8, lr_usr ; save unbanked lr to R8=0D
+ streq R2, [R8] ; make R2 point to R8=0D
; else=0D
- stmneed R2, {lr} ; save SVC lr=0D
+ mrsne R8, lr_svc ; save SVC lr to R8=0D
+ strne R2, [R8] ; make R2 point to R8=0D
=0D
=0D
ldr R5, [SP, #0x58] ; PC is the LR pushed by srsfd=0D
@@ -280,15 +282,17 @@ CommonCExceptionHandler (
and R1, R1, #0x1f ; Check to see if User or System Mode=
=0D
cmp R1, #0x1f ; if ((CPSR =3D=3D 0x10) || (CPSR =3D=
=3D 0x1f))=0D
cmpne R1, #0x10 ;=0D
- ldmeqed R2, {lr}^ ; restore unbanked lr=0D
+ ldreq R8, [R2] ; load sys/usr lr from R2 pointer=0D
+ msreq lr_usr, R8 ; restore unbanked lr=0D
; else=0D
- ldmneed R3, {lr} ; restore SVC lr, via ldmfd SP!, {LR=
}=0D
+ ldrne R8, [R3] ; load SVC lr from R3 pointer=0D
+ msrne lr_svc, R8 ; restore SVC lr, via ldmfd SP!, {LR=
}=0D
=0D
ldmfd SP!,{R0-R12} ; Restore general purpose registers=0D
; Exception handler can not change SP=
=0D
=0D
add SP,SP,#0x20 ; Clear out the remaining stack space=
=0D
- ldmfd SP!,{LR} ; restore the link register for this c=
ontext=0D
+ pop {LR} ; restore the link register for this c=
ontext=0D
rfefd SP! ; return from exception via srsfd stac=
k slot=0D
=0D
END=0D
diff --git a/ArmPkg/Library/ArmLib/Arm/ArmV7Support.asm b/ArmPkg/Library/Ar=
mLib/Arm/ArmV7Support.asm
index 3146c2b52181..724306399e6c 100644
--- a/ArmPkg/Library/ArmLib/Arm/ArmV7Support.asm
+++ b/ArmPkg/Library/ArmLib/Arm/ArmV7Support.asm
@@ -200,8 +200,10 @@ Loop2
mov R9, R4 ; R9 working copy of the max way size (rig=
ht aligned)=0D
=0D
Loop3=0D
- orr R0, R10, R9, LSL R5 ; factor in the way number and cache numbe=
r into R11=0D
- orr R0, R0, R7, LSL R2 ; factor in the index number=0D
+ lsl R8, R9, R5=0D
+ orr R0, R10, R8 ; factor in the way number and cache numbe=
r=0D
+ lsl R8, R7, R2=0D
+ orr R0, R0, R8 ; factor in the index number=0D
=0D
blx R1=0D
=0D
diff --git a/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.asm b/MdePkg=
/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.asm
index 5a423df16bff..a46d70e41433 100644
--- a/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.asm
+++ b/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.asm
@@ -5,16 +5,16 @@
;=0D
=0D
=0D
-AREA IoLibMmio, CODE, READONLY=0D
+ AREA IoLibMmio, CODE, READONLY=0D
=0D
-EXPORT MmioRead8Internal=0D
-EXPORT MmioWrite8Internal=0D
-EXPORT MmioRead16Internal=0D
-EXPORT MmioWrite16Internal=0D
-EXPORT MmioRead32Internal=0D
-EXPORT MmioWrite32Internal=0D
-EXPORT MmioRead64Internal=0D
-EXPORT MmioWrite64Internal=0D
+ EXPORT MmioRead8Internal=0D
+ EXPORT MmioWrite8Internal=0D
+ EXPORT MmioRead16Internal=0D
+ EXPORT MmioWrite16Internal=0D
+ EXPORT MmioRead32Internal=0D
+ EXPORT MmioWrite32Internal=0D
+ EXPORT MmioRead64Internal=0D
+ EXPORT MmioWrite64Internal=0D
=0D
;=0D
; Reads an 8-bit MMIO register.=0D
--=20
2.23.0

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