Re: [edk2-platform patch 6/7] SimicsOpenBoardPkg: Add board module for QSP Build tip


Kubacki, Michael A
 

Feedback I could not find already noted elsewhere:

1. Remove the batch build files:
- GitEdk2X58ICH10.bat
- bld.bat
- prebuild.bat

The changes must be built with the Python scripts.

2. General comment that applies to multiple files:
Files such as "PlatformPkgBuildOption.dsc" should follow the pre-existing open board package
naming convention. For example, "OpenBoardPkgBuildOption.dsc" in KabylakeOpenBoardPkg.
3. The first commit line should be "SimicsOpenBoardPkg/BoardX58Ich10 to indicate the files relative
to their location in that board directory.
4. Some build option macros in here seem unnecessary. For example, "PURLEY_FLAG". Can you please
check and clean this up?
5. PlatformPkgConfig.dsc: The following PCDs should not always be TRUE as they originate in the
AdvancedFeaturePkg and should only be enabled for an advanced feature boot.
- gAdvancedFeaturePkgTokenSpaceGuid.PcdNetworkEnable
- gAdvancedFeaturePkgTokenSpaceGuid.PcdSmbiosEnable

-----Original Message-----
From: Wei, David Y
Sent: Friday, August 9, 2019 3:47 PM
To: devel@edk2.groups.io
Cc: Wu, Hao A <hao.a.wu@...>; Gao, Liming <liming.gao@...>;
Sinha, Ankit <ankit.sinha@...>; Agyeman, Prince
<prince.agyeman@...>; Kubacki, Michael A
<michael.a.kubacki@...>; Desimone, Nathaniel L
<@natedesimone>; Kinney, Michael D
<michael.d.kinney@...>
Subject: [edk2-platform patch 6/7] SimicsOpenBoardPkg: Add board module
for QSP Build tip

Add BoardX58ICH10 module for QSP Build tip

Cc: Hao Wu <hao.a.wu@...>
Cc: Liming Gao <liming.gao@...>
Cc: Ankit Sinha <ankit.sinha@...>
Cc: Agyeman Prince <prince.agyeman@...>
Cc: Kubacki Michael A <michael.a.kubacki@...>
Cc: Nate DeSimone <@natedesimone>
Cc: Michael D Kinney <michael.d.kinney@...>
Contributed-under: TianoCore Contribution Agreement 1.0

Signed-off-by: David Wei <david.y.wei@...>
---
.../Library/BoardInitLib/PeiBoardInitPostMemLib.c | 44 +++
.../Library/BoardInitLib/PeiBoardInitPreMemLib.c | 110 ++++++++
.../Library/BoardInitLib/PeiX58ICH10Detect.c | 26 ++
.../BoardInitLib/PeiX58ICH10InitPostMemLib.c | 34 +++
.../BoardInitLib/PeiX58ICH10InitPreMemLib.c | 111 ++++++++
.../BoardX58ICH10/DecomprScratchEnd.fdf.inc | 66 +++++
.../BoardX58ICH10/GitEdk2X58ICH10.bat | 75 +++++
.../BoardInitLib/PeiBoardInitPostMemLib.inf | 36 +++
.../Library/BoardInitLib/PeiBoardInitPreMemLib.inf | 38 +++
.../Library/BoardInitLib/PeiX58ICH10InitLib.h | 16 ++
.../BoardX58ICH10/PlatformPkgBuildOption.dsc | 89 ++++++
.../BoardX58ICH10/PlatformPkgConfig.dsc | 56 ++++
.../BoardX58ICH10/PlatformPkgPcd.dsc | 283 +++++++++++++++++++
.../BoardX58ICH10/SimicsX58Pkg.fdf.inc | 48 ++++
.../BoardX58ICH10/SimicsX58PkgIa32X64.dsc | 244 +++++++++++++++++
.../BoardX58ICH10/SimicsX58PkgIa32X64.fdf | 303
+++++++++++++++++++++
.../BoardX58ICH10/VarStore.fdf.inc | 53 ++++
.../Intel/SimicsOpenBoardPkg/BoardX58ICH10/bld.bat | 139 ++++++++++
.../BoardX58ICH10/build_config.cfg | 31 +++
.../SimicsOpenBoardPkg/BoardX58ICH10/prebuild.bat | 198
++++++++++++++
20 files changed, 2000 insertions(+)
create mode 100644
Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/Library/BoardInitLib/PeiB
oardInitPostMemLib.c
create mode 100644
Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/Library/BoardInitLib/PeiB
oardInitPreMemLib.c
create mode 100644
Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/Library/BoardInitLib/PeiX
58ICH10Detect.c
create mode 100644
Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/Library/BoardInitLib/PeiX
58ICH10InitPostMemLib.c
create mode 100644
Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/Library/BoardInitLib/PeiX
58ICH10InitPreMemLib.c
create mode 100644
Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/DecomprScratchEnd.fdf.i
nc
create mode 100644
Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/GitEdk2X58ICH10.bat
create mode 100644
Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/Library/BoardInitLib/PeiB
oardInitPostMemLib.inf
create mode 100644
Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/Library/BoardInitLib/PeiB
oardInitPreMemLib.inf
create mode 100644
Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/Library/BoardInitLib/PeiX
58ICH10InitLib.h
create mode 100644
Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/PlatformPkgBuildOption.
dsc
create mode 100644
Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/PlatformPkgConfig.dsc
create mode 100644
Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/PlatformPkgPcd.dsc
create mode 100644
Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/SimicsX58Pkg.fdf.inc
create mode 100644
Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/SimicsX58PkgIa32X64.ds
c
create mode 100644
Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/SimicsX58PkgIa32X64.fdf
create mode 100644
Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/VarStore.fdf.inc
create mode 100644
Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/bld.bat
create mode 100644
Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/build_config.cfg
create mode 100644
Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/prebuild.bat

diff --git
a/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/Library/BoardInitLib/Pe
iBoardInitPostMemLib.c
b/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/Library/BoardInitLib/Pe
iBoardInitPostMemLib.c
new file mode 100644
index 0000000000..29df3d41ee
--- /dev/null
+++
b/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/Library/BoardInitLib/Pe
iBoardInitPostMemLib.c
@@ -0,0 +1,44 @@
+/** @file
+ Copyright (c) 2018 Intel Corporation. All rights reserved. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PiPei.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/BoardInitLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+
+EFI_STATUS
+EFIAPI
+X58ICH10BoardInitBeforeSiliconInit (
+ VOID
+ );
+
+EFI_STATUS
+EFIAPI
+X58ICH10BoardInitAfterSiliconInit (
+ VOID
+ );
+
+EFI_STATUS
+EFIAPI
+BoardInitBeforeSiliconInit (
+ VOID
+ )
+{
+ X58ICH10BoardInitBeforeSiliconInit ();
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+BoardInitAfterSiliconInit (
+ VOID
+ )
+{
+ X58ICH10BoardInitAfterSiliconInit ();
+ return EFI_SUCCESS;
+}
diff --git
a/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/Library/BoardInitLib/Pe
iBoardInitPreMemLib.c
b/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/Library/BoardInitLib/Pe
iBoardInitPreMemLib.c
new file mode 100644
index 0000000000..228fd696df
--- /dev/null
+++
b/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/Library/BoardInitLib/Pe
iBoardInitPreMemLib.c
@@ -0,0 +1,110 @@
+/** @file
+ Copyright (c) 2018 Intel Corporation. All rights reserved. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PiPei.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/BoardInitLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+
+EFI_STATUS
+EFIAPI
+X58ICH10BoardDetect(
+ VOID
+ );
+
+EFI_BOOT_MODE
+EFIAPI
+X58ICH10BoardBootModeDetect (
+ VOID
+ );
+
+EFI_STATUS
+EFIAPI
+X58ICH10BoardDebugInit (
+ VOID
+ );
+
+EFI_STATUS
+EFIAPI
+X58ICH10BoardInitBeforeMemoryInit (
+ VOID
+ );
+
+EFI_STATUS
+EFIAPI
+X58ICH10BoardInitAfterMemoryInit (
+ VOID
+ );
+
+EFI_STATUS
+EFIAPI
+BoardDetect (
+ VOID
+ )
+{
+ X58ICH10BoardDetect ();
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+BoardDebugInit (
+ VOID
+ )
+{
+ X58ICH10BoardDebugInit ();
+ return EFI_SUCCESS;
+}
+
+EFI_BOOT_MODE
+EFIAPI
+BoardBootModeDetect (
+ VOID
+ )
+{
+ return X58ICH10BoardBootModeDetect ();
+}
+
+EFI_STATUS
+EFIAPI
+BoardInitBeforeMemoryInit (
+ VOID
+ )
+{
+ X58ICH10BoardInitBeforeMemoryInit ();
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+BoardInitAfterMemoryInit (
+ VOID
+ )
+{
+ X58ICH10BoardInitAfterMemoryInit ();
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+BoardInitBeforeTempRamExit (
+ VOID
+ )
+{
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+BoardInitAfterTempRamExit (
+ VOID
+ )
+{
+ return EFI_SUCCESS;
+}
+
diff --git
a/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/Library/BoardInitLib/Pe
iX58ICH10Detect.c
b/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/Library/BoardInitLib/Pe
iX58ICH10Detect.c
new file mode 100644
index 0000000000..7305ce3181
--- /dev/null
+++
b/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/Library/BoardInitLib/Pe
iX58ICH10Detect.c
@@ -0,0 +1,26 @@
+/** @file
+ Copyright (c) 2018 Intel Corporation. All rights reserved. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PiPei.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/IoLib.h>
+#include <Library/HobLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PciLib.h>
+#include <Library/PcdLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/BoardInitLib.h>
+
+EFI_STATUS
+EFIAPI
+X58ICH10BoardDetect (
+ VOID
+ )
+{
+ DEBUG ((EFI_D_INFO, "X58ICH10BoardDetect\n"));
+ return EFI_SUCCESS;
+}
diff --git
a/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/Library/BoardInitLib/Pe
iX58ICH10InitPostMemLib.c
b/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/Library/BoardInitLib/Pe
iX58ICH10InitPostMemLib.c
new file mode 100644
index 0000000000..002f63a434
--- /dev/null
+++
b/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/Library/BoardInitLib/Pe
iX58ICH10InitPostMemLib.c
@@ -0,0 +1,34 @@
+/** @file
+ Copyright (c) 2018 Intel Corporation. All rights reserved. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PiPei.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/IoLib.h>
+#include <Library/HobLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PciLib.h>
+
+#include "PeiX58ICH10InitLib.h"
+EFI_STATUS
+EFIAPI
+X58ICH10BoardInitBeforeSiliconInit (
+ VOID
+ )
+{
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+X58ICH10BoardInitAfterSiliconInit (
+ VOID
+ )
+{
+
+ DEBUG((EFI_D_ERROR, "X58ICH10BoardInitAfterSiliconInit\n"));
+ return EFI_SUCCESS;
+}
diff --git
a/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/Library/BoardInitLib/Pe
iX58ICH10InitPreMemLib.c
b/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/Library/BoardInitLib/Pe
iX58ICH10InitPreMemLib.c
new file mode 100644
index 0000000000..9f0dc91c8a
--- /dev/null
+++
b/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/Library/BoardInitLib/Pe
iX58ICH10InitPreMemLib.c
@@ -0,0 +1,111 @@
+/** @file
+ Copyright (c) 2018 Intel Corporation. All rights reserved. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Base.h>
+#include <PiPei.h>
+#include <Uefi.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/IoLib.h>
+#include <Library/HobLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PciLib.h>
+#include <Library/BoardInitLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/PeiServicesTablePointerLib.h>
+
+#include "PeiX58ICH10InitLib.h"
+#include <IndustryStandard/X58Ich10.h>
+/**
+ Reads 8-bits of CMOS data.
+
+ Reads the 8-bits of CMOS data at the location specified by Index.
+ The 8-bit read value is returned.
+
+ @param Index The CMOS location to read.
+
+ @return The value read.
+
+**/
+UINT8
+EFIAPI
+CmosRead8(
+ IN UINTN Index
+ )
+{
+ IoWrite8 (0x70, (UINT8)Index);
+ return IoRead8(0x71);
+}
+
+
+/**
+ Writes 8-bits of CMOS data.
+
+ Writes 8-bits of CMOS data to the location specified by Index
+ with the value specified by Value and returns Value.
+
+ @param Index The CMOS location to write.
+ @param Value The value to write to CMOS.
+
+ @return The value written to CMOS.
+
+**/
+UINT8
+EFIAPI
+CmosWrite8(
+ IN UINTN Index,
+ IN UINT8 Value
+ )
+{
+ IoWrite8 (0x70, (UINT8)Index);
+ IoWrite8 (0x71, Value);
+ return Value;
+}
+
+
+EFI_STATUS
+EFIAPI
+X58ICH10BoardInitBeforeMemoryInit (
+ VOID
+ )
+{
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+X58ICH10BoardInitAfterMemoryInit (
+ VOID
+ )
+{
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+X58ICH10BoardDebugInit (
+ VOID
+ )
+{
+ return EFI_SUCCESS;
+}
+
+EFI_BOOT_MODE
+EFIAPI
+X58ICH10BoardBootModeDetect (
+ VOID
+ )
+{
+ EFI_BOOT_MODE BootMode = BOOT_WITH_FULL_CONFIGURATION;
+
+ DEBUG((EFI_D_INFO, "modeValue = %x\n",
IoBitFieldRead16(ICH10_PMBASE_IO + 4, 10, 12)));
+ if (IoBitFieldRead16(ICH10_PMBASE_IO + 4, 10, 12) == 0x5) {
+ BootMode = BOOT_ON_S3_RESUME;
+ }
+
+ return BootMode;
+}
diff --git
a/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/DecomprScratchEnd.fd
f.inc
b/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/DecomprScratchEnd.fd
f.inc
new file mode 100644
index 0000000000..394875f205
--- /dev/null
+++
b/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/DecomprScratchEnd.fd
f.inc
@@ -0,0 +1,66 @@
+## @file
+# This FDF include file computes the end of the scratch buffer used in
+# DecompressMemFvs() [SimicsX58Pkg/Sec/SecMain.c]. It is based on the
decompressed
+# (ie. original) size of the LZMA-compressed section of the one FFS file in
+# the FVMAIN_COMPACT firmware volume.
+#
+# Copyright (C) 2015, Red Hat, Inc.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+# The GUID EE4E5898-3914-4259-9D6E-DC7BD79403CF means
"LzmaCustomDecompress".
+# The decompressed output will have the following structure (see the file
+# "9E21FD93-9C72-4c15-8C4B-E77F1DB2D792SEC1.guided.dummy" in the
+# Build/SimicsX58*/*/FV/Ffs/9E21FD93-9C72-4c15-8C4B-E77F1DB2D792/
directory):
+#
+# Size Contents
+# ------------------- --------------------------------------------------------
+# 4 EFI_COMMON_SECTION_HEADER, stating size 124 (0x7C) and
+# type 0x19 (EFI_SECTION_RAW). The purpose of this section
+# is to pad the start of PEIFV to 128 bytes.
+# 120 Zero bytes (padding).
+#
+# 4 EFI_COMMON_SECTION_HEADER, stating size
+# (PcdSimicsPeiMemFvSize + 4), and type 0x17
+# (EFI_SECTION_FIRMWARE_VOLUME_IMAGE).
+# PcdSimicsPeiMemFvSize PEIFV. Note that the above sizes pad the offset of
this
+# object to 128 bytes. See also the "guided.dummy.txt"
+# file in the same directory.
+#
+# 4 EFI_COMMON_SECTION_HEADER, stating size 12 (0xC) and
+# type 0x19 (EFI_SECTION_RAW). The purpose of this section
+# is to pad the start of DXEFV to 16 bytes.
+# 8 Zero bytes (padding).
+#
+# 4 EFI_COMMON_SECTION_HEADER, stating size
+# (PcdSimicsDxeMemFvSize + 4), and type 0x17
+# (EFI_SECTION_FIRMWARE_VOLUME_IMAGE).
+# PcdSimicsDxeMemFvSize DXEFV. Note that the above sizes pad the offset of
this
+# object to 16 bytes. See also the "guided.dummy.txt" file
+# in the same directory.
+#
+# The total size after decompression is (128 + PcdSimicsPeiMemFvSize + 16 +
+# PcdSimicsDxeMemFvSize).
+
+DEFINE OUTPUT_SIZE = (128 +
gSimicsX58PkgTokenSpaceGuid.PcdSimicsPeiMemFvSize + 16 +
gSimicsX58PkgTokenSpaceGuid.PcdSimicsDxeMemFvSize)
+
+# LzmaCustomDecompressLib uses a constant scratch buffer size of 64KB; see
+# SCRATCH_BUFFER_REQUEST_SIZE in
+# "MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaDecompress.c".
+
+DEFINE DECOMP_SCRATCH_SIZE = 0x00010000
+
+# Note: when we use PcdSimicsDxeMemFvBase in this context, BaseTools have
not yet
+# offset it with MEMFD's base address. For that reason we have to do it
manually.
+#
+# The calculation below mirrors DecompressMemFvs()
[SimicsX58Pkg/Sec/SecMain.c].
+
+DEFINE OUTPUT_BASE = ($(MEMFD_BASE_ADDRESS) +
gSimicsX58PkgTokenSpaceGuid.PcdSimicsDxeMemFvBase + 0x00100000)
+DEFINE DECOMP_SCRATCH_BASE_UNALIGNED = ($(OUTPUT_BASE) +
$(OUTPUT_SIZE))
+DEFINE DECOMP_SCRATCH_BASE_ALIGNMENT = 0x000FFFFF
+DEFINE DECOMP_SCRATCH_BASE_MASK = 0xFFF00000
+DEFINE DECOMP_SCRATCH_BASE =
(($(DECOMP_SCRATCH_BASE_UNALIGNED) +
$(DECOMP_SCRATCH_BASE_ALIGNMENT)) &
$(DECOMP_SCRATCH_BASE_MASK))
+
+SET gSimicsX58PkgTokenSpaceGuid.PcdSimicsDecompressionScratchEnd =
$(DECOMP_SCRATCH_BASE) + $(DECOMP_SCRATCH_SIZE)
diff --git
a/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/GitEdk2X58ICH10.bat
b/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/GitEdk2X58ICH10.bat
new file mode 100644
index 0000000000..48e9c6b09d
--- /dev/null
+++
b/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/GitEdk2X58ICH10.bat
@@ -0,0 +1,75 @@
+@echo off
+@REM @file
+@REM Copyright (c) 2018 Intel Corporation. All rights reserved. <BR>
+@REM
+@REM SPDX-License-Identifier: BSD-2-Clause-Patent
+@REM
+
+@echo off
+
+pushd ..\..\..\..\..\
+
+@REM Set WORKSPACE environment.
+set WORKSPACE=%cd%
+echo.
+echo Set WORKSPACE as: %WORKSPACE%
+echo.
+
+@REM Check whether Git has been installed and been added to system path.
+git --help >nul 2>nul
+if %ERRORLEVEL% NEQ 0 (
+ echo.
+ echo The 'git' command is not recognized.
+ echo Please make sure that Git is installed and has been added to system path.
+ echo.
+ goto :EOF
+)
+
+@REM Create the Conf directory under WORKSPACE
+if not exist %WORKSPACE%\Conf (
+ mkdir Conf
+)
+
+@REM Set other environments.
+@REM Basic Rule:
+@REM Platform override Silicon override Core
+@REM Source override Binary
+
+set PACKAGES_PATH=%WORKSPACE%\edk2-
platforms\Platform\Intel;%WORKSPACE%\edk2-
platforms\Silicon\Intel;%WORKSPACE%\edk2-
platforms\Drivers;%WORKSPACE%\edk2-non-
osi\Silicon\Intel;%WORKSPACE%\edk2;%WORKSPACE%
+
+set EDK_TOOLS_BIN=%WORKSPACE%\edk2-BaseTools-win32
+
+@if not defined PYTHON_HOME (
+ @if exist C:\Python27 (
+ set PYTHON_HOME=C:\Python27
+ )
+)
+
+set EDK_SETUP_OPTION=
+@rem if python is installed, disable the binary base tools.
+if defined PYTHON_HOME (
+ set EDK_TOOLS_BIN=
+ set EDK_SETUP_OPTION=Rebuild
+)
+pushd %WORKSPACE%\edk2
+call edksetup.bat %EDK_SETUP_OPTION%
+popd
+
+set openssl_path=%WORKSPACE%
+
+popd
+
+goto :EOF
+
+:Help
+echo.
+echo Usage:
+echo GitEdk2.bat [-w Workspace_Directory] (optional) [-b Branch_Name]
(optional)
+echo.
+echo -w A absolute/relative path to be the workspace.
+echo Default value is the current directory.
+echo.
+echo -b The branch name of the repository. Currently, only master, udk2015,
+echo trunk (same as master) and bp13 (same as udk2015) are supported.
+echo Default value is master.
+echo.
diff --git
a/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/Library/BoardInitLib/Pe
iBoardInitPostMemLib.inf
b/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/Library/BoardInitLib/Pe
iBoardInitPostMemLib.inf
new file mode 100644
index 0000000000..542b53547f
--- /dev/null
+++
b/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/Library/BoardInitLib/Pe
iBoardInitPostMemLib.inf
@@ -0,0 +1,36 @@
+## @file
+#
+# Copyright (c) 2018 Intel Corporation. All rights reserved. <BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PeiBoardPostMemInitLib
+ FILE_GUID = 30F407D6-6B92-412A-B2DA-8E73E2B386E6
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = BoardInitLib
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+ BaseMemoryLib
+ MemoryAllocationLib
+ PcdLib
+
+[Packages]
+ MinPlatformPkg/MinPlatformPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+
+[Sources]
+ PeiX58ICH10InitPostMemLib.c
+ PeiBoardInitPostMemLib.c
+
+[FixedPcd]
+
+[Pcd]
+
diff --git
a/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/Library/BoardInitLib/Pe
iBoardInitPreMemLib.inf
b/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/Library/BoardInitLib/Pe
iBoardInitPreMemLib.inf
new file mode 100644
index 0000000000..ab1286602b
--- /dev/null
+++
b/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/Library/BoardInitLib/Pe
iBoardInitPreMemLib.inf
@@ -0,0 +1,38 @@
+## @file
+#
+# Copyright (c) 2018 Intel Corporation. All rights reserved. <BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PeiBoardInitPreMemLib
+ FILE_GUID = 73AA24AE-FB20-43F9-A3BA-448953A03A78
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = BoardInitLib
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+ BaseMemoryLib
+ MemoryAllocationLib
+ PcdLib
+
+[Packages]
+ MinPlatformPkg/MinPlatformPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ SimicsOpenBoardPkg/SimicsOpenBoardPkg.dec
+
+[Sources]
+ PeiX58ICH10Detect.c
+ PeiX58ICH10InitPreMemLib.c
+ PeiBoardInitPreMemLib.c
+
+[Pcd]
+
+[FixedPcd]
+
diff --git
a/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/Library/BoardInitLib/Pe
iX58ICH10InitLib.h
b/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/Library/BoardInitLib/Pe
iX58ICH10InitLib.h
new file mode 100644
index 0000000000..996679e8f5
--- /dev/null
+++
b/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/Library/BoardInitLib/Pe
iX58ICH10InitLib.h
@@ -0,0 +1,16 @@
+/** @file
+ Copyright (c) 2018 Intel Corporation. All rights reserved. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PEI_X58ICH10_BOARD_INIT_LIB_H_
+#define _PEI_X58ICH10_BOARD_INIT_LIB_H_
+
+#include <Uefi.h>
+#include <Library/BaseLib.h>
+#include <Library/PcdLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/DebugLib.h>
+
+#endif
diff --git
a/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/PlatformPkgBuildOptio
n.dsc
b/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/PlatformPkgBuildOptio
n.dsc
new file mode 100644
index 0000000000..8bce3c7a4f
--- /dev/null
+++
b/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/PlatformPkgBuildOptio
n.dsc
@@ -0,0 +1,89 @@
+## @file
+#
+# Copyright (c) 2018 Intel Corporation. All rights reserved. <BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[BuildOptions.Common.EDKII]
+# Append build options for EDK and EDKII drivers (= is Append, == is Replace)
+
+ DEFINE CRB_EDKII_BUILD_OPTIONS = -D CRB_FLAG
+ DEFINE EDKII_CPU_BUILD_OPTIONS = -D PURLEY_FLAG
+ DEFINE TRAD_BUILD_OPTION = -D TRAD_FLAG=1
+ DEFINE SUS_WELL_RESTORE_BUILD_OPTION = -D SUS_WELL_RESTORE=1
+ DEFINE PCH_BUILD_OPTION = -D PCH_SERVER_BIOS_FLAG=1
+ DEFINE SERVER_BUILD_OPTION = -D SERVER_BIOS_FLAG=1
+ DEFINE PCH_PKG_OPTIONS = -D PCH_SPT
+ DEFINE MAX_SOCKET_OPTIONS = -D MAX_SOCKET=2
+
+ DEFINE EDKII_ALL_PPO_OPTIONS = $(EDKII_CPU_BUILD_OPTIONS)
+ DEFINE PCH_BIOS_BUILD_OPTIONS = $(TRAD_BUILD_OPTION)
$(ULT_BUILD_OPTION) $(PCH_BUILD_OPTION)
$(SUS_WELL_RESTORE_BUILD_OPTION) $(SERVER_BUILD_OPTION)
+ DEFINE EDKII_DSC_FEATURE_BUILD_OPTIONS =
$(CRB_EDKII_BUILD_OPTIONS) $(PCH_BIOS_BUILD_OPTIONS)
$(PCH_PKG_OPTIONS) $(EDKII_ALL_PPO_OPTIONS)
$(SPARING_SCRATCHPAD_OPTION) $(TRACE_HUB_DEBUG_BUILD_OPTIONS)
$(TRACE_HUB_INIT_BUILD_OPTIONS) $(MAX_SOCKET_OPTIONS) -D
EFI_PCI_IOV_SUPPORT -D WHEA_SUPPORT -D SKX_HOST -D CLX_HOST
+
+!if $(TARGET) == "DEBUG"
+ DEFINE DEBUG_BUILD_FLAG = -D SERIAL_DBG_MSG=1
+!else
+ DEFINE DEBUG_BUILD_FLAG = -D MDEPKG_NDEBUG -D SILENT_MODE
+!endif
+
+ DEFINE EDKII_DSC_FEATURE_BUILD_OPTIONS =
$(EDKII_DSC_FEATURE_BUILD_OPTIONS) $(DEBUG_BUILD_FLAG)
+#
+# PC_BUILD_END
+#
+
+
+ DEFINE EDKII_DSC_FEATURE_BUILD_OPTIONS =
$(EDKII_DSC_FEATURE_BUILD_OPTIONS)
+
+
+ *_*_IA32_CC_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
+ *_*_IA32_VFRPP_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
+ *_*_IA32_APP_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
+ *_*_IA32_PP_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
+ *_*_IA32_ASLPP_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
+ *_*_IA32_ASLCC_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
+
+ *_*_X64_CC_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
+ *_*_X64_VFRPP_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
+ *_*_X64_APP_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
+ *_*_X64_PP_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
+ *_*_X64_ASLPP_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
+ *_*_X64_ASLCC_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
+
+
+
+#
+# Enable source level debugging for RELEASE build
+#
+!if $(TARGET) == "RELEASE"
+ DEFINE EDKII_RELEASE_SRCDBG_ASM_BUILD_OPTIONS = /Zi
+ DEFINE EDKII_RELEASE_SRCDBG_CC_BUILD_OPTIONS = /Zi /Gm
+ DEFINE EDKII_RELEASE_SRCDBG_DLINK_BUILD_OPTIONS = /DEBUG
+
+ MSFT:*_*_*_ASM_FLAGS =
$(EDKII_RELEASE_SRCDBG_ASM_BUILD_OPTIONS)
+ MSFT:*_*_*_CC_FLAGS =
$(EDKII_RELEASE_SRCDBG_CC_BUILD_OPTIONS)
+ MSFT:*_*_*_DLINK_FLAGS =
$(EDKII_RELEASE_SRCDBG_DLINK_BUILD_OPTIONS)
+!endif
+
+
+#
+# Override the existing iasl path in tools_def.template
+#
+# MSFT:*_*_*_ASL_PATH == c:/Iasl/iasl.exe
+
+#
+# Override the VFR compile flags to speed the build time
+#
+
+*_*_*_VFR_FLAGS == -n
+
+# Force PE/COFF sections to be aligned at 4KB boundaries to support page level
protection
+#[BuildOptions.common.EDKII.DXE_SMM_DRIVER,
BuildOptions.common.EDKII.SMM_CORE]
+# MSFT:*_*_*_DLINK_FLAGS = /ALIGN:4096
+# GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000
+
+# Force PE/COFF sections to be aligned at 4KB boundaries to support
MemoryAttribute table
+#[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]
+# MSFT:*_*_*_DLINK_FLAGS = /ALIGN:4096
+# GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000
diff --git
a/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/PlatformPkgConfig.dsc
b/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/PlatformPkgConfig.dsc
new file mode 100644
index 0000000000..f0ab846290
--- /dev/null
+++
b/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/PlatformPkgConfig.dsc
@@ -0,0 +1,56 @@
+## @file
+#
+# Copyright (c) 2018 Intel Corporation. All rights reserved. <BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+#
+# TRUE is ENABLE. FALSE is DISABLE.
+#
+
+[PcdsFixedAtBuild]
+ gMinPlatformPkgTokenSpaceGuid.PcdBootStage|4
+
+[PcdsFeatureFlag]
+ gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE
+ gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE
+ gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE
+ gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|FALSE
+ gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|FALSE
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 1
+ gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|TRUE
+!endif
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 2
+ gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE
+ gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|TRUE
+!endif
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 3
+ gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE
+ gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|TRUE
+!endif
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 4
+ gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE
+!endif
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 5
+ gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|TRUE
+ gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|TRUE
+!endif
+
+ !if $(TARGET) == DEBUG
+ gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|TRUE
+ !else
+ gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|FALSE
+ !endif
+
+ gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable|FALSE
+
+ gAdvancedFeaturePkgTokenSpaceGuid.PcdNetworkEnable|TRUE
+ gAdvancedFeaturePkgTokenSpaceGuid.PcdSmbiosEnable|TRUE
+
diff --git
a/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/PlatformPkgPcd.dsc
b/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/PlatformPkgPcd.dsc
new file mode 100644
index 0000000000..dc70adee34
--- /dev/null
+++
b/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/PlatformPkgPcd.dsc
@@ -0,0 +1,283 @@
+## @file
+#
+# Copyright (c) 2018 Intel Corporation. All rights reserved. <BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+############################################################
####################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+############################################################
####################
+[PcdsFeatureFlag.common]
+!if $(TARGET) == RELEASE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE
+!else
+ gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE
+!endif
+ # Server doesn't support capsle update on Reset.
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSupportUpdateCapsuleReset|FALSE
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|FALSE
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugSupport|FALSE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdPciBusHotplugDeviceSupport|FALSE
+
+
+#S3 add
+ gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode|TRUE
+#S3 add
+
+ ## This PCD specified whether ACPI SDT protocol is installed.
+ gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE
+
+[PcdsFeatureFlag.X64]
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackGuard|FALSE
+
+[PcdsFeatureFlag]
+
gEfiMdeModulePkgTokenSpaceGuid.PcdBrowerGrayOutReadOnlyMenu|TRUE
+
+[PcdsDynamicExDefault]
+
+[PcdsFixedAtBuild.common]
+
gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChan
ge|TRUE
+!if $(TARGET) == "RELEASE"
+ gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x03
+!else
+ gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
+!endif
+ gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
+ gEfiMdeModulePkgTokenSpaceGuid.PcdLoadModuleAtFixAddressEnable|0
+ gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x0
+#S3 modified
+ gEfiMdeModulePkgTokenSpaceGuid.PcdShadowPeimOnS3Boot|TRUE
+#S3 modified
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x0
+ gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x0
+ gEfiMdePkgTokenSpaceGuid.PcdFSBClock|133333333
+ gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxPeiStackSize|0x100000
+
gEfiMdeModulePkgTokenSpaceGuid.PcdMaxSizeNonPopulateCapsule|0x17000
00
+
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|10000
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|512
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x4000
+
+ ## Specifies delay value in microseconds after sending out an INIT IPI.
+ # @Prompt Configure delay value after send an INIT IPI
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuInitIpiDelayInMicroSeconds|10
+
+ ## Specifies max supported number of Logical Processors.
+ # @Prompt Configure max supported number of Logical Processorss
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|512
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuApStackSize|0x1000
+!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable == TRUE
+ gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1
+!endif
+
+ ## Defines the ACPI register set base address.
+ # The invalid 0xFFFF is as its default value. It must be configured to the real
value.
+ # @Prompt ACPI Timer IO Port Address
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddress | 0x0400
+
+ ## Defines the PCI Bus Number of the PCI device that contains the BAR and
Enable for ACPI hardware registers.
+ # @Prompt ACPI Hardware PCI Bus Number
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBusNumber | 0x00
+
+
gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision|0x00000002
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId|0x4C544E49
+
gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision|0x200910
13
+
+ ## Defines the PCI Device Number of the PCI device that contains the BAR and
Enable for ACPI hardware registers.
+ # The invalid 0xFF is as its default value. It must be configured to the real
value.
+ # @Prompt ACPI Hardware PCI Device Number
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciDeviceNumber | 0x1F
+
+ ## Defines the PCI Function Number of the PCI device that contains the BAR
and Enable for ACPI hardware registers.
+ # The invalid 0xFF is as its default value. It must be configured to the real
value.
+ # @Prompt ACPI Hardware PCI Function Number
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciFunctionNumber | 0x00
+
+ ## Defines the PCI Register Offset of the PCI device that contains the Enable
for ACPI hardware registers.
+ # The invalid 0xFFFF is as its default value. It must be configured to the real
value.
+ # @Prompt ACPI Hardware PCI Register Offset
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciEnableRegisterOffset |0x0044
+
+ ## Defines the bit mask that must be set to enable the APIC hardware register
BAR.
+ # @Prompt ACPI Hardware PCI Bar Enable BitMask
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoBarEnableMask | 0x80
+
+ ## Defines the PCI Register Offset of the PCI device that contains the BAR for
ACPI hardware registers.
+ # The invalid 0xFFFF is as its default value. It must be configured to the real
value.
+ # @Prompt ACPI Hardware PCI Bar Register Offset
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBarRegisterOffset |0x0040
+
+ ## Defines the offset to the 32-bit Timer Value register that resides within the
ACPI BAR.
+ # @Prompt Offset to 32-bit Timer register in ACPI BAR
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiPm1TmrOffset |0x0008
+
+ ## Defines the bit mask to retrieve ACPI IO Port Base Address
+ # @Prompt ACPI IO Port Base Address Mask
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddressMask |0xFFFC
+
+
gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChan
ge|FALSE
+
+ gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|4
+ gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|128
+ gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|4
+ gMinPlatformPkgTokenSpaceGuid.PcdLocalApicAddress|0xFEE00000
+ gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicAddressBase|0xFEC01000
+ gMinPlatformPkgTokenSpaceGuid.PcdFadtPreferredPmProfile|0x0
+ gMinPlatformPkgTokenSpaceGuid.PcdFadtIaPcBootArch|0x0003
+ gMinPlatformPkgTokenSpaceGuid.PcdFadtFlags|0x000004A5
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1AEventBlockAddress|0x400
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1BEventBlockAddress|0
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1AControlBlockAddress|0x404
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1BControlBlockAddress|0
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm2ControlBlockAddress|0x450
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiPmTimerBlockAddress|0x408
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiGpe0BlockAddress|0x420
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiGpe1BlockAddress|0
+
+[PcdsFixedAtBuild.X64]
+ gPcAtChipsetPkgTokenSpaceGuid.Pcd8259LegacyModeMask|0x0eB8
+ gPcAtChipsetPkgTokenSpaceGuid.PcdMinimalValidYear|2015
+ gPcAtChipsetPkgTokenSpaceGuid.PcdMaximalValidYear|2099
+ # Change PcdBootManagerMenuFile to UiApp
+##
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa,
0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23,
0x31 }
+
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmCodeAccessCheckEnable |TRUE
+
+ [PcdsPatchableInModule.common]
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable == TRUE
+
gEfiMdeModulePkgTokenSpaceGuid.PcdSmiHandlerProfilePropertyMask|0x1
+!endif
+
+ gPcAtChipsetPkgTokenSpaceGuid.PcdHpetBaseAddress|0xFED00000
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|1024
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|600
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable|TRUE
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase|0x0
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize|0x0
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress|0xFFE00000
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize|0x00200000
+
+[PcdsDynamicExDefault.common.DEFAULT]
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|30000
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuS3DataAddress|0
+
+[PcdsDynamicExHii.common.DEFAULT]
+
gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobal
VariableGuid|0x0|50 # Variable: L"Timeout"
+
gEfiMdePkgTokenSpaceGuid.PcdHardwareErrorRecordLevel|L"HwErrRecSuppo
rt"|gEfiGlobalVariableGuid|0x0|1 # Variable: L"HwErrRecSupport"
+
+
+[PcdsDynamicExDefault]
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMrIovSupport|FALSE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSystemPageSize|0x1F
+
+
gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L""|VOID*|36
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId|{0x49, 0x4E,
0x54, 0x45, 0x4C, 0x20}
+
gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x204657303
0363253
+
+[PcdsDynamicExDefault.X64]
+
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|8
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|1
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|1
+ gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|0
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|31
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|100
+
+
gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|800
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|600
+
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugDataAddress|0
+
+[PcdsFeatureFlag]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|TRUE
+
gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSupportUefiDecompress|FALSE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode|TRUE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutUgaSupport|FALSE
+ #gOptionRomPkgTokenSpaceGuid.PcdSupportGop|TRUE
+ #gOptionRomPkgTokenSpaceGuid.PcdSupportUga|FALSE
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
+ gSimicsX58PkgTokenSpaceGuid.PcdSmmSmramRequire|TRUE
+!endif
+
+[PcdsFixedAtBuild]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeMemorySize|1
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumGuidedExtractHandler|0x10
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x400
+
gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x800
0
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVariableStoreSize|0xc000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0xc000
+
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0x200
0
+
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x10000
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0
+
+ # DEBUG_INIT 0x00000001 // Initialization
+ # DEBUG_WARN 0x00000002 // Warnings
+ # DEBUG_LOAD 0x00000004 // Load events
+ # DEBUG_FS 0x00000008 // EFI File system
+ # DEBUG_POOL 0x00000010 // Alloc & Free (pool)
+ # DEBUG_PAGE 0x00000020 // Alloc & Free (page)
+ # DEBUG_INFO 0x00000040 // Informational debug messages
+ # DEBUG_DISPATCH 0x00000080 // PEI/DXE/SMM Dispatchers
+ # DEBUG_VARIABLE 0x00000100 // Variable
+ # DEBUG_BM 0x00000400 // Boot Manager
+ # DEBUG_BLKIO 0x00001000 // BlkIo Driver
+ # DEBUG_NET 0x00004000 // SNP Driver
+ # DEBUG_UNDI 0x00010000 // UNDI Driver
+ # DEBUG_LOADFILE 0x00020000 // LoadFile
+ # DEBUG_EVENT 0x00080000 // Event messages
+ # DEBUG_GCD 0x00100000 // Global Coherency Database changes
+ # DEBUG_CACHE 0x00200000 // Memory range cachability changes
+ # DEBUG_VERBOSE 0x00400000 // Detailed debug messages that may
+ # // significantly impact boot performance
+ # DEBUG_ERROR 0x80000000 // Error
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8000004F
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F
+
+ #
+ # PCI feature overrides.
+ #
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|FALSE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE
+
+############################################################
####################
+#
+# Pcd Dynamic Section - list of all EDK II PCD Entries defined by this Platform
+#
+############################################################
####################
+
+[PcdsDynamicDefault]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvStoreReserved|0
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0
+
+ gSimicsX58PkgTokenSpaceGuid.PcdSimicsX58HostBridgePciDevId|0
+ gSimicsX58PkgTokenSpaceGuid.PcdPciIoBase|0x0
+ gSimicsX58PkgTokenSpaceGuid.PcdPciIoSize|0x0
+ gSimicsX58PkgTokenSpaceGuid.PcdPciMmio32Base|0x0
+ gSimicsX58PkgTokenSpaceGuid.PcdPciMmio32Size|0x0
+ gSimicsX58PkgTokenSpaceGuid.PcdPciMmio64Base|0x0
+ gSimicsX58PkgTokenSpaceGuid.PcdPciMmio64Size|0x800000000
+
+
gAdvancedFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringBiosVersion|"Ve
r.1.0.0"
+
gAdvancedFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringProductName|"
QSP UEFI BIOS"
+
gAdvancedFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringProductName|"
QSP UEFI BIOS"
+
gAdvancedFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringBiosReleaseDate
|"2019-08-09"
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiS3Enable|FALSE
diff --git
a/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/SimicsX58Pkg.fdf.inc
b/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/SimicsX58Pkg.fdf.inc
new file mode 100644
index 0000000000..f42e8b0e0e
--- /dev/null
+++
b/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/SimicsX58Pkg.fdf.inc
@@ -0,0 +1,48 @@
+## @file
+# FDF include file that defines the main macros and sets the dependent PCDs.
+#
+# Copyright (C) 2014, Red Hat, Inc.
+# Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+#
+# Default flash size is 2MB.
+#
+# Defining FD_SIZE_2MB on the build command line can override this.
+#
+
+DEFINE BLOCK_SIZE = 0x1000
+DEFINE VARS_SIZE = 0x3e000
+DEFINE VARS_BLOCKS = 0x3e
+
+DEFINE FW_BASE_ADDRESS = 0xFFE00000
+DEFINE FW_SIZE = 0x00200000
+DEFINE FW_BLOCKS = 0x200
+DEFINE CODE_BASE_ADDRESS = 0xFFE80000
+DEFINE CODE_SIZE = 0x00180000
+DEFINE CODE_BLOCKS = 0x180
+DEFINE FVMAIN_SIZE = 0x0016C000
+DEFINE SECFV_OFFSET = 0x001EC000
+DEFINE SECFV_SIZE = 0x14000
+
+
+SET gSimicsX58PkgTokenSpaceGuid.PcdSimicsFdBaseAddress =
$(FW_BASE_ADDRESS)
+SET gSimicsX58PkgTokenSpaceGuid.PcdSimicsFirmwareFdSize = $(FW_SIZE)
+SET gSimicsX58PkgTokenSpaceGuid.PcdSimicsFirmwareBlockSize =
$(BLOCK_SIZE)
+
+SET gSimicsX58PkgTokenSpaceGuid.PcdSimicsFlashNvStorageVariableBase =
$(FW_BASE_ADDRESS)
+SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize =
0xE000
+
+SET gSimicsX58PkgTokenSpaceGuid.PcdSimicsFlashNvStorageEventLogBase =
gSimicsX58PkgTokenSpaceGuid.PcdSimicsFlashNvStorageVariableBase +
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+SET gSimicsX58PkgTokenSpaceGuid.PcdSimicsFlashNvStorageEventLogSize =
$(BLOCK_SIZE)
+
+SET gSimicsX58PkgTokenSpaceGuid.PcdSimicsFlashNvStorageFtwWorkingBase
= gSimicsX58PkgTokenSpaceGuid.PcdSimicsFlashNvStorageEventLogBase +
gSimicsX58PkgTokenSpaceGuid.PcdSimicsFlashNvStorageEventLogSize
+SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize =
$(BLOCK_SIZE)
+
+SET gSimicsX58PkgTokenSpaceGuid.PcdSimicsFlashNvStorageFtwSpareBase =
gSimicsX58PkgTokenSpaceGuid.PcdSimicsFlashNvStorageFtwWorkingBase +
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize =
0x10000
+
+DEFINE MEMFD_BASE_ADDRESS = 0x800000
diff --git
a/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/SimicsX58PkgIa32X64.
dsc
b/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/SimicsX58PkgIa32X64.
dsc
new file mode 100644
index 0000000000..66ac16a940
--- /dev/null
+++
b/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/SimicsX58PkgIa32X64.
dsc
@@ -0,0 +1,244 @@
+## @file
+#
+# Copyright (c) 2018 Intel Corporation. All rights reserved. <BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+############################################################
####################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+############################################################
####################
+[Defines]
+ DEFINE PLATFORM_PACKAGE = MinPlatformPkg
+ DEFINE BOARD_NAME = BoardX58ICH10
+ DEFINE BOARD_PKG = SimicsOpenBoardPkg
+ DEFINE SKT_PKG = SimicsX58SktPkg
+ DEFINE PCH_PKG = SimicsICH10Pkg
+ DEFINE DXE_ARCH = X64
+ DEFINE PEI_ARCH = IA32
+
+ PLATFORM_NAME = SimicsX58
+ PLATFORM_GUID = EE8EBB5A-CC95-412f-9987-2AF70F88B69A
+ PLATFORM_VERSION = 0.1
+ DSC_SPECIFICATION = 0x00010005
+ OUTPUT_DIRECTORY = Build/SimicsX58Ia32X64
+ SUPPORTED_ARCHITECTURES = IA32|X64
+ BUILD_TARGETS = DEBUG|RELEASE|NOOPT
+ SKUID_IDENTIFIER = DEFAULT
+ FLASH_DEFINITION =
$(BOARD_PKG)/$(BOARD_NAME)/SimicsX58PkgIa32X64.fdf
+
+ DEFINE SMM_REQUIRE = TRUE
+
+ #
+ #PLATFORMX64_ENABLE is set to TRUE when PEI is IA32 and DXE is X64
platform
+ #
+ DEFINE PLATFORMX64_ENABLE = TRUE
+ DEFINE NETWORK_TLS_ENABLE = FALSE
+ DEFINE NETWORK_ISCSI_ENABLE = FALSE
+ DEFINE NETWORK_ALLOW_HTTP_CONNECTIONS = TRUE
+ !include NetworkPkg/NetworkDefines.dsc.inc
+############################################################
####################
+#
+# SKU Identification section - list of all SKU IDs supported by this Platform.
+#
+############################################################
####################
+[SkuIds]
+ 0|DEFAULT
+
+############################################################
####################
+#
+# Library Class section - list of all Library Classes needed by this Platform.
+#
+############################################################
####################
+
+[PcdsFeatureFlag]
+ #
+ # Platform On/Off features are defined here
+ #
+ !include $(BOARD_PKG)/$(BOARD_NAME)/PlatformPkgConfig.dsc
+ !include MinPlatformPkg/Include/Dsc/CoreCommonLib.dsc
+ !include $(PCH_PKG)/PchCommonLib.dsc
+
+[LibraryClasses]
+
ReportFvLib|MinPlatformPkg/PlatformInit/Library/PeiReportFvLib/PeiReportFv
Lib.inf
+ BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf
+ SerialPortLib|PcAtChipsetPkg/Library/SerialIoLib/SerialIoLib.inf
+ NvVarsFileLib|$(BOARD_PKG)/Library/NvVarsFileLib/NvVarsFileLib.inf
+
SerializeVariablesLib|$(BOARD_PKG)/Library/SerializeVariablesLib/SerializeVari
ablesLib.inf
+ LoadLinuxLib|$(BOARD_PKG)/Library/LoadLinuxLib/LoadLinuxLib.inf
+
CpuExceptionHandlerLib|MdeModulePkg/Library/CpuExceptionHandlerLibNull/
CpuExceptionHandlerLibNull.inf
+
+
TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLibNull/TestPoi
ntCheckLibNull.inf
+
BoardInitLib|MinPlatformPkg/PlatformInit/Library/BoardInitLibNull/BoardInitLi
bNull.inf
+
SiliconPolicyInitLib|$(BOARD_PKG)/Policy/Library/SiliconPolicyInitLib/SiliconPol
icyInitLib.inf
+
SiliconPolicyUpdateLib|$(BOARD_PKG)/Policy/Library/SiliconPolicyUpdateLib/S
iliconPolicyUpdateLib.inf
+
PciSegmentInfoLib|MinPlatformPkg/Pci/Library/PciSegmentInfoLibSimple/PciS
egmentInfoLibSimple.inf
+
+ !include MinPlatformPkg/Include/Dsc/CorePeiLib.dsc
+
+
S3BootScriptLib|MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScri
ptLib.inf
+
AslUpdateLib|MinPlatformPkg/Acpi/Library/DxeAslUpdateLib/DxeAslUpdateLib.
inf
+[LibraryClasses.common.SEC]
+
ExtractGuidedSectionLib|MdePkg/Library/BaseExtractGuidedSectionLib/BaseExt
ractGuidedSectionLib.inf
+
+[LibraryClasses.common.PEI_CORE]
+
+[LibraryClasses.common.PEIM]
+
PeiResourcePublicationLib|MdePkg/Library/PeiResourcePublicationLib/PeiReso
urcePublicationLib.inf
+ MpInitLib|UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf
+
+[LibraryClasses.IA32]
+!if $(TARGET) == DEBUG
+
TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLib/PeiTestPoi
ntCheckLib.inf
+!endif
+ TestPointLib|MinPlatformPkg/Test/Library/TestPointLib/PeiTestPointLib.inf
+
+ !include MinPlatformPkg/Include/Dsc/CoreDxeLib.dsc
+
+[LibraryClasses.common.DXE_CORE]
+
+[LibraryClasses.common.DXE_RUNTIME_DRIVER]
+
PciLib|$(BOARD_PKG)/Overrides/MdePkg/Library/BasePciLibCf8/DxePciLibX58
Ich10.inf
+
+[LibraryClasses.common.UEFI_DRIVER]
+
PciLib|$(BOARD_PKG)/Overrides/MdePkg/Library/BasePciLibCf8/DxePciLibX58
Ich10.inf
+
+[LibraryClasses.common.DXE_DRIVER]
+
PlatformBootManagerLib|$(BOARD_PKG)/Overrides/MdeModulePkg/Library/P
latformBootManagerLib/PlatformBootManagerLib.inf
+
PciLib|$(BOARD_PKG)/Overrides/MdePkg/Library/BasePciLibCf8/DxePciLibX58
Ich10.inf
+
+[LibraryClasses.common.UEFI_APPLICATION]
+
PciLib|$(BOARD_PKG)/Overrides/MdePkg/Library/BasePciLibCf8/DxePciLibX58
Ich10.inf
+
+[LibraryClasses.common.DXE_SMM_DRIVER]
+
PciLib|$(BOARD_PKG)/Overrides/MdePkg/Library/BasePciLibCf8/DxePciLibX58
Ich10.inf
+
SpiFlashCommonLib|$(PCH_PKG)/Library/SmmSpiFlashCommonLib/SmmSpiFla
shCommonLib.inf
+
+[LibraryClasses.common.SMM_CORE]
+
PciLib|$(BOARD_PKG)/Overrides/MdePkg/Library/BasePciLibCf8/DxePciLibX58
Ich10.inf
+
+ !include $(BOARD_PKG)/$(BOARD_NAME)/PlatformPkgPcd.dsc
+
+[Components.IA32]
+ !include $(SKT_PKG)/SktPei.dsc
+ !include MinPlatformPkg/Include/Dsc/CorePeiInclude.dsc
+
+ $(BOARD_PKG)/PlatformPei/PlatformPei.inf {
+ <LibraryClasses>
+ PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
+ }
+# S3 SMM driver
+# UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPei.inf
+ UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf {
+ <LibraryClasses>
+
LockBoxLib|MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxPeiLib.inf
+ }
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
+ $(SKT_PKG)/Smm/Access/SmmAccessPei.inf {
+ <LibraryClasses>
+ PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
+ }
+!endif
+ $(PLATFORM_PACKAGE)/PlatformInit/ReportFv/ReportFvPei.inf
+
+ MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf {
+ <LibraryClasses>
+
BoardInitLib|$(BOARD_PKG)/$(BOARD_NAME)/Library/BoardInitLib/PeiBoardI
nitPreMemLib.inf
+ }
+ MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf {
+ <LibraryClasses>
+
BoardInitLib|$(BOARD_PKG)/$(BOARD_NAME)/Library/BoardInitLib/PeiBoardI
nitPostMemLib.inf
+ }
+ MinPlatformPkg/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem.inf
+ MinPlatformPkg/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPostMem.inf
+
+[Components.X64]
+ !include MinPlatformPkg/Include/Dsc/CoreDxeInclude.dsc
+
$(BOARD_PKG)/Overrides/PcAtChipsetPkg/8259InterruptControllerDxe/8259.i
nf
+ !include AdvancedFeaturePkg/Include/Dsc/CoreAdvancedDxeInclude.dsc
+
+ MdeModulePkg/Universal/EbcDxe/EbcDxe.inf
+ $(BOARD_PKG)/Overrides/MdeModulePkg/Logo/LogoDxe.inf
+
+ MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
+ #
+ # ISA Support
+ #
+ $(BOARD_PKG)/LegacySioDxe/LegacySioDxe.inf
+ MdeModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2KeyboardDxe.inf
+
+ $(BOARD_PKG)/SmbiosPlatformDxe/SmbiosPlatformDxe.inf
+ $(BOARD_PKG)/AcpiTables/AcpiTables.inf
+ #
+ # Video support
+ #
+ $(BOARD_PKG)/Overrides/OvmfPkg/QemuVideoDxe/QemuVideoDxe.inf
+
+ MinPlatformPkg/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf
+ MinPlatformPkg/PlatformInit/PlatformInitSmm/PlatformInitSmm.inf
+ $(BOARD_PKG)/PlatformDxe/Platform.inf
+ MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf
+
MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.
inf
+
+ #
+ # Shell
+ #
+ ShellPkg/Application/Shell/Shell.inf {
+ <PcdsFixedAtBuild>
+ gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
+ <LibraryClasses>
+
NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2Command
sLib.inf
+
NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1Command
sLib.inf
+
NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3Command
sLib.inf
+
NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1Comma
ndsLib.inf
+
NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1Comman
dsLib.inf
+
NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1Comma
ndsLib.inf
+
NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1Co
mmandsLib.inf
+
NULL|ShellPkg/Library/UefiShellNetwork2CommandsLib/UefiShellNetwork2Co
mmandsLib.inf
+
ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLi
b.inf
+
HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.
inf
+
BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCo
mmandLib.inf
+ ShellCEntryLib|ShellPkg/Library/UefiShellCEntryLib/UefiShellCEntryLib.inf
+ ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
+ }
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
+ $(SKT_PKG)/Smm/Access/SmmAccess2Dxe.inf
+ $(PCH_PKG)/SmmControl/RuntimeDxe/SmmControl2Dxe.inf
+ UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf
+ $(PCH_PKG)/Spi/Smm/PchSpiSmm.inf
+ MinPlatformPkg/Flash/SpiFvbService/SpiFvbServiceSmm.inf
+ UefiCpuPkg/CpuS3DataDxe/CpuS3DataDxe.inf
+ MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf {
+ <LibraryClasses>
+
LockBoxLib|MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxSmmLib.inf
+ }
+!endif
+ MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+ MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+ MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf {
+ <LibraryClasses>
+
PciHostBridgeLib|$(BOARD_PKG)/Overrides/MdeModulePkg/Library/PciHostBr
idgeLib/PciHostBridgeLib.inf
+ }
+ MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
+
+ UefiCpuPkg/CpuDxe/CpuDxe.inf
+ MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+ MdeModulePkg/Universal/PrintDxe/PrintDxe.inf
+ MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
+ MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
+ #
+ # ACPI Support
+ #
+ MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
+ $(BOARD_PKG)/Overrides/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf
+
+!if gAdvancedFeaturePkgTokenSpaceGuid.PcdSmbiosEnable == TRUE
+ AdvancedFeaturePkg/Smbios/SmbiosBasicDxe/SmbiosBasicDxe.inf
+!endif
+
+ !include $(BOARD_PKG)/$(BOARD_NAME)/PlatformPkgBuildOption.dsc
diff --git
a/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/SimicsX58PkgIa32X64.f
df
b/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/SimicsX58PkgIa32X64.f
df
new file mode 100644
index 0000000000..d6c381a515
--- /dev/null
+++
b/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/SimicsX58PkgIa32X64.f
df
@@ -0,0 +1,303 @@
+## @file
+#
+# Copyright (c) 2018 Intel Corporation. All rights reserved. <BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+!include SimicsX58Pkg.fdf.inc
+
+#
+# Build the variable store and the firmware code as one unified flash device
+# image.
+#
+[FD.SIMICSX58IA32X64]
+BaseAddress = $(FW_BASE_ADDRESS)
+Size = $(FW_SIZE)
+ErasePolarity = 1
+BlockSize = $(BLOCK_SIZE)
+NumBlocks = $(FW_BLOCKS)
+
+!include VarStore.fdf.inc
+
+$(VARS_SIZE)|0x00002000
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfi
MdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+#NV_FTW_WORKING
+DATA = {
+ # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature =
gEdkiiWorkingBlockSignatureGuid =
+ # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b,
0x95 }}
+ 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49,
+ 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95,
+ # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved
+ 0xE2, 0x33, 0xF2, 0x03, 0xFE, 0xFF, 0xFF, 0xFF,
+ # WriteQueueSize: UINT64
+ 0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+0x00040000|0x00040000
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMd
eModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+#NV_FTW_SPARE
+
+0x00080000|0x0016C000
+FV = FVMAIN_COMPACT
+
+$(SECFV_OFFSET)|$(SECFV_SIZE)
+FV = FvTempMemorySilicon
+
+#
+# Build the variable store and the firmware code as separate flash device
+# images.
+#
+[FD.SIMICS_VARS]
+BaseAddress = $(FW_BASE_ADDRESS)
+Size = 0x80000
+ErasePolarity = 1
+BlockSize = $(BLOCK_SIZE)
+NumBlocks = 0x80
+
+!include VarStore.fdf.inc
+
+[FD.SIMICS_CODE]
+BaseAddress = $(CODE_BASE_ADDRESS)
+Size = $(CODE_SIZE)
+ErasePolarity = 1
+BlockSize = $(BLOCK_SIZE)
+NumBlocks = $(CODE_BLOCKS)
+
+0x00000000|0x0016C000
+FV = FVMAIN_COMPACT
+
+0x0016C000|$(SECFV_SIZE)
+FV = FvTempMemorySilicon
+
+[FD.MEMFD]
+BaseAddress = $(MEMFD_BASE_ADDRESS)
+Size = 0xB00000
+ErasePolarity = 1
+BlockSize = 0x10000
+NumBlocks = 0xB0
+
+0x000000|0x006000
+gSimicsX58PkgTokenSpaceGuid.PcdSimicsSecPageTablesBase|gSimicsX58PkgT
okenSpaceGuid.PcdSimicsSecPageTablesSize
+
+0x006000|0x001000
+gSimicsX58PkgTokenSpaceGuid.PcdSimicsLockBoxStorageBase|gSimicsX58Pkg
TokenSpaceGuid.PcdSimicsLockBoxStorageSize
+
+0x007000|0x001000
+gEfiMdePkgTokenSpaceGuid.PcdGuidedExtractHandlerTableAddress|gSimicsX
58PkgTokenSpaceGuid.PcdGuidedExtractHandlerTableSize
+
+0x010000|0x008000
+gSimicsX58PkgTokenSpaceGuid.PcdSimicsSecPeiTempRamBase|gSimicsX58Pk
gTokenSpaceGuid.PcdSimicsSecPeiTempRamSize
+
+0x020000|0x0E0000
+gSimicsX58PkgTokenSpaceGuid.PcdSimicsPeiMemFvBase|gSimicsX58PkgToke
nSpaceGuid.PcdSimicsPeiMemFvSize
+FV = FvPreMemory
+
+0x100000|0xA00000
+gSimicsX58PkgTokenSpaceGuid.PcdSimicsDxeMemFvBase|gSimicsX58PkgTok
enSpaceGuid.PcdSimicsDxeMemFvSize
+FV = DXEFV
+
+############################################################
####################
+
+[FV.FvTempMemorySilicon]
+FvAlignment = 16
+FvForceRebase = TRUE
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+FvNameGuid = 229EEDCE-8E76-4809-B233-EC36BFBF6989
+
+!include $(SKT_PKG)/SktSecInclude.fdf
+
+[FV.FvPreMemory]
+FvAlignment = 16
+FvForceRebase = TRUE
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+FvNameGuid = 6522280D-28F9-4131-ADC4-F40EBFA45864
+
+##
+# PEI Apriori file example, more PEIM module added later.
+##
+INF MdeModulePkg/Core/Pei/PeiMain.inf
+!include $(SKT_PKG)/SktPreMemoryInclude.fdf
+!include $(PCH_PKG)/PchPreMemoryInclude.fdf
+!include MinPlatformPkg/Include/Fdf/CorePreMemoryInclude.fdf
+INF MinPlatformPkg/PlatformInit/ReportFv/ReportFvPei.inf
+INF MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf
+INF MinPlatformPkg/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem.inf
+!include MinPlatformPkg/Include/Fdf/CoreSecurityPreMemoryInclude.fdf
+!include
AdvancedFeaturePkg/Include/Fdf/CoreAdvancedPreMemoryInclude.fdf
+INF $(BOARD_PKG)/PlatformPei/PlatformPei.inf
+!include $(SKT_PKG)/SktPostMemoryInclude.fdf
+!include $(PCH_PKG)/PchPostMemoryInclude.fdf
+!include MinPlatformPkg/Include/Fdf/CorePostMemoryInclude.fdf
+INF MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf
+INF
MinPlatformPkg/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPostMem.inf
+!include MinPlatformPkg/Include/Fdf/CoreSecurityPostMemoryInclude.fdf
+!include
AdvancedFeaturePkg/Include/Fdf/CoreAdvancedPostMemoryInclude.fdf
+
+INF UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf
+INF $(SKT_PKG)/Smm/Access/SmmAccessPei.inf
+# S3 SMM PEI driver
+#INF UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPei.inf
+
+[FV.DXEFV]
+FvNameGuid = EACAB9EA-C3C6-4438-8FD7-2270826DC0BB
+BlockSize = 0x10000
+FvAlignment = 16
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+!include MinPlatformPkg/Include/Fdf/CoreUefiBootInclude.fdf
+INF
$(BOARD_PKG)/Overrides/PcAtChipsetPkg/8259InterruptControllerDxe/8259.i
nf
+!include $(SKT_PKG)/SktUefiBootInclude.fdf
+!include $(PCH_PKG)/PchUefiBootInclude.fdf
+
+INF MdeModulePkg/Universal/EbcDxe/EbcDxe.inf
+INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
+INF UefiCpuPkg/CpuDxe/CpuDxe.inf
+
+!include MinPlatformPkg/Include/Fdf/CoreOsBootInclude.fdf
+INF MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf
+INF
MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.
inf
+INF UefiCpuPkg/CpuS3DataDxe/CpuS3DataDxe.inf
+INF MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf
+INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+INF MdeModulePkg/Universal/PrintDxe/PrintDxe.inf
+INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
+INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
+
+INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+INF MinPlatformPkg/Flash/SpiFvbService/SpiFvbServiceSmm.inf
+INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
+
+INF $(BOARD_PKG)/LegacySioDxe/LegacySioDxe.inf
+INF MdeModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2KeyboardDxe.inf
+
+INF $(BOARD_PKG)/SmbiosPlatformDxe/SmbiosPlatformDxe.inf
+
+INF MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
+INF
$(BOARD_PKG)/Overrides/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf
+INF RuleOverride=ACPITABLE $(BOARD_PKG)/AcpiTables/AcpiTables.inf
+
+INF $(BOARD_PKG)/Overrides/OvmfPkg/QemuVideoDxe/QemuVideoDxe.inf
+INF $(BOARD_PKG)/Overrides/MdeModulePkg/Logo/LogoDxe.inf
+INF MinPlatformPkg/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf
+INF MinPlatformPkg/PlatformInit/PlatformInitSmm/PlatformInitSmm.inf
+INF $(BOARD_PKG)/PlatformDxe/Platform.inf
+
+INF ShellPkg/Application/Shell/Shell.inf
+
+#
+# Network modules
+#
+FILE DRIVER = 5D695E11-9B3F-4b83-B25F-4A8D5D69BE07 {
+ SECTION PE32 = SimicsICH10SiliconBinPkg/UndiBinary/GigUndiDxe.efi
+ SECTION UI = "IntelIch10UNDI"
+}
+!include AdvancedFeaturePkg/Include/Fdf/CoreAdvancedLateInclude.fdf
+
+!if gAdvancedFeaturePkgTokenSpaceGuid.PcdSmbiosEnable == TRUE
+ INF AdvancedFeaturePkg/Smbios/SmbiosBasicDxe/SmbiosBasicDxe.inf
+!endif
+
+!include MinPlatformPkg/Include/Fdf/CoreSecurityLateInclude.fdf
+
+[FV.FVMAIN_COMPACT]
+FvNameGuid = 6189987A-DDA6-4060-B313-49168DA9BD46
+FvAlignment = 16
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF
PROCESSING_REQUIRED = TRUE {
+ #
+ # These firmware volumes will have files placed in them uncompressed,
+ # and then both firmware volumes will be compressed in a single
+ # compression operation in order to achieve better overall compression.
+ #
+ SECTION FV_IMAGE = FvPreMemory
+ SECTION FV_IMAGE = DXEFV
+ }
+}
+
+!include DecomprScratchEnd.fdf.inc
+
+
+############################################################
####################
+#
+# Rules are use with the [FV] section's module INF type to define
+# how an FFS file is created for a given INF file. The following Rule are the
default
+# rules for the different module type. User can add the customized rules to
define the
+# content of the FFS file.
+#
+############################################################
####################
+
+!include MinPlatformPkg/Include/Fdf/RuleInclude.fdf
+
+[Rule.Common.SEC.RESET_VECTOR]
+ FILE RAW = $(NAMED_GUID) {
+ RAW RAW |.raw
+ }
+
+[Rule.Common.SEC.RESET_SECMAIN]
+ FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
+ UI STRING="$(MODULE_NAME)" Optional
+ VERSION STRING="$(INF_VERSION)" Optional
BUILD_NUM=$(BUILD_NUMBER)
+ PE32 PE32 Align = 16 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ }
diff --git
a/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/VarStore.fdf.inc
b/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/VarStore.fdf.inc
new file mode 100644
index 0000000000..76c28e9efc
--- /dev/null
+++ b/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/VarStore.fdf.inc
@@ -0,0 +1,53 @@
+## @file
+# FDF include file with Layout Regions that define an empty variable store.
+#
+# Copyright (C) 2014, Red Hat, Inc.
+# Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+0x00000000|0x0003e000
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMde
ModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+#NV_VARIABLE_STORE
+DATA = {
+ ## This is the EFI_FIRMWARE_VOLUME_HEADER
+ # ZeroVector []
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ # FileSystemGuid: gEfiSystemNvDataFvGuid =
+ # { 0xFFF12B8D, 0x7696, 0x4C8B,
+ # { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }}
+ 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,
+ 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,
+ # FvLength: 0x80000
+ 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00,
+ #Signature "_FVH" #Attributes
+ 0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00,
+ #HeaderLength #CheckSum #ExtHeaderOffset #Reserved #Revision
+ 0x48, 0x00, 0x2A, 0x09, 0x00, 0x00, 0x00, 0x02,
+ #Blockmap[0]: 7 Blocks * 0x10000 Bytes / Block
+ 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
+ #Blockmap[1]: End
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ ## This is the VARIABLE_STORE_HEADER
+!if $(SECURE_BOOT_ENABLE) == TRUE
+ # Signature: gEfiAuthenticatedVariableGuid =
+ # { 0xaaf32c78, 0x947b, 0x439a,
+ # { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }}
+ 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43,
+ 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92,
+!else
+ #Signature: gEfiVariableGuid =
+ # { 0xddcf3616, 0x3275, 0x4164, { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe,
0x7d }}
+ 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41,
+ 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d,
+!endif
+ #Size: 0x3E000
(gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - 0x48
(size of EFI_FIRMWARE_VOLUME_HEADER) = 0x03DFB8
+ # This can speed up the Variable Dispatch a bit.
+ 0xB8, 0xDF, 0x03, 0x00,
+ # FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1:
UINT32
+ 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
diff --git a/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/bld.bat
b/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/bld.bat
new file mode 100644
index 0000000000..efce310dfe
--- /dev/null
+++ b/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/bld.bat
@@ -0,0 +1,139 @@
+@echo off
+@REM @file
+@REM Copyright (c) 2018 Intel Corporation. All rights reserved. <BR>
+@REM
+@REM SPDX-License-Identifier: BSD-2-Clause-Patent
+@REM
+
+@echo off
+
+REM Run setlocal to take a snapshot of the environment variables. endlocal is
called to restore the environment.
+setlocal
+set SCRIPT_ERROR=0
+
+REM ---- Do NOT use :: for comments Inside of code blocks() ----
+
+::***********************************************************
***********
+:: Initial Setup
+::***********************************************************
***********
+
+:parseCmdLine
+if "%1"=="" goto :argumentCheck
+
+if /I "%1"=="debug" set TARGET=DEBUG
+if /I "%1"=="release" set TARGET=RELEASE
+
+if /I "%1"=="cleantree" (
+ set BUILD_TYPE=cleantree
+ call :cleantree
+ goto :EOF
+)
+
+shift
+GOTO :parseCmdLine
+
+:argumentCheck:
+
+if /I "%TARGET%" == "" (
+ echo Info: debug/release argument is empty, use DEBUG as default
+ set TARGET=DEBUG
+)
+
+REM Art to notify which board you're working on
+echo.
+type logo.txt
+echo.
+
+::
+:: Build configuration
+::
+set BUILD_REPORT_FLAGS=
+set BUILD_CMD_LINE=
+set BUILD_LOG=%WORKSPACE%\Build\BuildSrc\build.log
+set BUILD_REPORT=%WORKSPACE%\Build\BuildSrc\BuildReport.txt
+
+del %BUILD_LOG% *.efi *.log 2>NUL
+
+echo --------------------------------------------------------------------------------------------
+echo.
+echo QSP Build Start
+echo.
+echo --------------------------------------------------------------------------------------------
+
+
+:doPreBuild
+echo.
+echo --------------------------------------------------------------------
+echo.
+echo Prebuild Start
+echo.
+echo --------------------------------------------------------------------
+call prebuild.bat
+if %SCRIPT_ERROR% NEQ 0 EXIT /b %ERRORLEVEL%
+
+echo --------------------------------------------------------------------
+echo.
+echo Prebuild End
+echo.
+echo --------------------------------------------------------------------
+if %ERRORLEVEL% NEQ 0 EXIT /b %ERRORLEVEL%
+timeout 1
+
+:buildBios
+set BUILD_CMD_LINE=%BUILD_CMD_LINE% -D
MAX_SOCKET=%MAX_SOCKET% -y %BUILD_REPORT%
+echo --------------------------------------------------------------------
+echo.
+echo Build Start
+echo.
+echo --------------------------------------------------------------------
+echo.
+echo build %BUILD_CMD_LINE% --log=%BUILD_LOG%
%BUILD_REPORT_FLAGS%
+call build %BUILD_CMD_LINE% --log=%BUILD_LOG%
%BUILD_REPORT_FLAGS%
+echo --------------------------------------------------------------------
+echo.
+echo Build End
+echo.
+echo --------------------------------------------------------------------
+if %ERRORLEVEL% NEQ 0 EXIT /b %ERRORLEVEL%
+timeout 1
+
+:postBuild
+
+echo --------------------------------------------------------------------
+echo.
+echo PostBuild Start
+echo.
+echo --------------------------------------------------------------------
+echo.
+REM call postbuild.bat
+if %ERRORLEVEL% NEQ 0 EXIT /b %ERRORLEVEL%
+timeout 1
+echo --------------------------------------------------------------------
+echo.
+echo PostBuild End
+echo.
+echo --------------------------------------------------------------------
+
+echo %date% %time%
+echo.
+
+echo --------------------------------------------------------------------------------------------
+echo.
+echo QSP Build End
+echo.
+echo --------------------------------------------------------------------------------------------
+
+:done
+endlocal & EXIT /b %SCRIPT_ERROR%
+
+::--------------------------------------------------------
+::-- Function section starts below here
+::--------------------------------------------------------
+:cleantree
+choice /t 3 /d y /m "Confirm: clean tree of intermediate files created in tree
during build"
+if %ERRORLEVEL% EQU 2 goto :EOF
+goto :EOF
+
+
+:ErrorHandler:
+echo Error handler
diff --git
a/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/build_config.cfg
b/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/build_config.cfg
new file mode 100644
index 0000000000..ad3ae229e8
--- /dev/null
+++ b/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/build_config.cfg
@@ -0,0 +1,31 @@
+# @ build_config.cfg
+# This is the BoardX58ICH10 board specific build settings
+#
+# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+
+[CONFIG]
+WORKSPACE_PLATFORM_BIN = WORKSPACE_PLATFORM_BIN
+EDK_SETUP_OPTION =
+openssl_path =
+PLATFORM_BOARD_PACKAGE = SimicsOpenBoardPkg
+PROJECT = SimicsOpenBoardPkg/BoardX58ICH10
+BOARD = BoardX58ICH10
+FLASH_MAP_FDF =
SimicsOpenBoardPkg/BoardX58ICH10/Include/Fdf/FlashMapInclude.fdf
+PROJECT_DSC =
SimicsOpenBoardPkg/BoardX58ICH10/SimicsX58PkgIa32X64.dsc
+BOARD_PKG_PCD_DSC =
SimicsOpenBoardPkg/BoardX58ICH10/PlatformPkgPcd.dsc
+PrepRELEASE = DEBUG
+SILENT_MODE = FALSE
+EXT_CONFIG_CLEAR =
+CapsuleBuild = FALSE
+EXT_BUILD_FLAGS =
+CAPSULE_BUILD = 0
+TARGET = DEBUG
+TARGET_SHORT = D
+PERFORMANCE_BUILD = FALSE
+FSP_WRAPPER_BUILD = FALSE
+FSP_BINARY_BUILD = FALSE
+FSP_TEST_RELEASE = FALSE
+SECURE_BOOT_ENABLE = FALSE
diff --git a/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/prebuild.bat
b/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/prebuild.bat
new file mode 100644
index 0000000000..666332e2d4
--- /dev/null
+++ b/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/prebuild.bat
@@ -0,0 +1,198 @@
+@echo off
+@REM @file
+@REM Copyright (c) 2018 Intel Corporation. All rights reserved. <BR>
+@REM
+@REM SPDX-License-Identifier: BSD-2-Clause-Patent
+@REM
+
+@set SCRIPT_ERROR=0
+
+set /a prebuildstep=0
+
+call :check_BuildTools
+if %SCRIPT_ERROR% NEQ 0 GOTO :done
+
+call :setBuildEnv
+if %SCRIPT_ERROR% NEQ 0 GOTO :done
+
+call :createTargetTxt
+if %SCRIPT_ERROR% NEQ 0 GOTO :done
+
+REM call :genPlatformOffsetHeaderFile
+REM if %SCRIPT_ERROR% NEQ 0 GOTO :done
+
+:prebuildFinish
+echo.
+echo ACTIVE_PLATFORM = %WORKSPACE%\edk2-
platforms\Platform\Intel\%BOARD_PKG%\%BOARD_NAME%\SimicsX58PkgIa3
2X64.dsc
+echo EDK_TOOLS_PATH = %EDK_TOOLS_PATH%
+echo TARGET = %TARGET%
+echo TARGET_ARCH = IA32 X64
+echo TOOL_CHAIN_TAG = %TOOL_CHAIN_TAG%
+echo WORKSPACE = %WORKSPACE%
+echo PACKAGES_PATH = %PACKAGES_PATH%
+echo MAX_CONCURRENT_THREAD_NUMBER =
%BUILD_MAX_CON_THREAD_NUM%
+echo.
+echo Build Path = %OUTPUT_DIR%
+echo.
+
+REM Remove environment variable because it's no longer needed.
+set BUILD_MAX_CON_THREAD_NUM=
+
+:done
+REM Use done label to exit batch file and run any final steps; GOTO :EOF
immediately exits.
+EXIT /B %SCRIPT_ERROR%
+
+::--------------------------------------------------------
+::-- Function section starts below here
+::--------------------------------------------------------
+
+:cleanup_check_VSTools
+set COMPILER_VERSION_STRING=
+del cloutput.txt > nul
+REM cleanup_check_VSTools is called below. When a label is called, 'GOTO
:EOF' is used to return to caller.
+GOTO :EOF
+
+:check_BuildTools
+echo PreBuild.%prebuildstep% check_BuildTools
+echo ..VSTools
+set /a prebuildstep=%prebuildstep%+1
+set TOOL_CHAIN_TAG=
+@if not defined TOOL_CHAIN_TAG (
+ echo.
+ echo Prebuild: TOOL_CHAIN_TAG is not set before
+ echo.
+
+ @if defined VS140COMNTOOLS (
+ echo.
+ echo Set the VS2015 environment.
+ echo.
+ set CL_SEL=VS2015
+ if /I "%VS140COMNTOOLS%" == "C:\Program Files\Microsoft Visual Studio
14.0\Common7\Tools\" (
+ set TOOL_CHAIN_TAG=VS2015
+ ) else (
+ set TOOL_CHAIN_TAG=VS2015x86
+ )
+ if /I "%PROCESSOR_ARCHITECTURE%" == "AMD64" (
+ set CL_CMDLINE="%VS140COMNTOOLS:~0,-14%VC\bin\amd64\cl.exe"
+ ) else (
+ set CL_CMDLINE="%VS140COMNTOOLS:~0,-14%VC\bin\cl.exe"
+ )
+ ) else if defined VS120COMNTOOLS (
+ echo.
+ echo Set the VS2013 environment.
+ echo.
+ set CL_SEL=VS2013
+ if /I "%VS120COMNTOOLS%" == "C:\Program Files\Microsoft Visual Studio
12.0\Common7\Tools\" (
+ set TOOL_CHAIN_TAG=VS2013
+ ) else (
+ set TOOL_CHAIN_TAG=VS2013x86
+ )
+ if /I "%PROCESSOR_ARCHITECTURE%" == "AMD64" (
+ set CL_CMDLINE="%VS120COMNTOOLS:~0,-14%VC\bin\amd64\cl.exe"
+ ) else (
+ set CL_CMDLINE="%VS120COMNTOOLS:~0,-14%VC\bin\cl.exe"
+ )
+ ) else (
+ echo.
+ echo !!! ERROR !!! VS2015 or VS2013 not installed correctly. !!!
+ echo.
+ goto :ErrorExit
+ )
+)
+
+echo ..iASL
+set CHECK_PATH_IASL=%IASL_PREFIX%
+if not exist %CHECK_PATH_IASL%\iasl.exe (
+ echo.
+ echo !!! ERROR !!! Could not find iASL compiler at
%CHECK_PATH_IASL%\iasl.exe. !!!
+ echo.
+ set SCRIPT_ERROR=1
+)
+set CHECK_PATH_IASL=
+
+echo ..NASM
+set CHECK_PATH_NASM=c:\NASM
+if not exist %CHECK_PATH_NASM%\nasm.exe (
+ echo.
+ echo !!! ERROR !!! Could not find NASM compiler at
%CHECK_PATH_NASM%\nasm.exe. !!!
+ echo.
+ set SCRIPT_ERROR=1
+)
+set CHECK_PATH_NASM=
+
+echo ..Python
+set CHECK_PATH_PYTHON=c:\Python27
+if not exist %CHECK_PATH_PYTHON%\python.exe (
+ echo.
+ echo !!! ERROR !!! Could not find Python at
%CHECK_PATH_PYTHON%\python.exe. !!!
+ echo.
+ set SCRIPT_ERROR=1
+)
+set CHECK_PATH_PYTHON=
+set PYTHON_HOME=C:\Python27
+
+GOTO :EOF
+
+:setBuildEnv
+echo PreBuild.%prebuildstep% SetBuildEnv
+set /a prebuildstep=%prebuildstep%+1
+
+@set BOARD_PKG=SimicsOpenBoardPkg
+@set BOARD_NAME=BoardX58ICH10
+@set MAX_SOCKET=2
+
+echo.
+echo BOARD_NAME=%BOARD_NAME%
+echo BOARD_PKG=%BOARD_PKG%
+echo MAX_SOCKET=%MAX_SOCKET%
+echo TARGET=%TARGET%
+
+@set
OUTPUT_DIR=%WORKSPACE%\Build\BuildSrc\%BOARD_PKG%\%BOARD_NAM
E%\%TARGET%_%TOOL_CHAIN_TAG%
+
+if not exist %OUTPUT_DIR% mkdir %OUTPUT_DIR%
+GOTO :EOF
+
+:createTargetTxt
+echo PreBuild.%prebuildstep% CreateTargetTxt
+set /a prebuildstep=%prebuildstep%+1
+set /a BUILD_MAX_CON_THREAD_NUM = %NUMBER_OF_PROCESSORS%-1
+@REM set /a BUILD_MAX_CON_THREAD_NUM = 1
+findstr /V "ACTIVE_PLATFORM TARGET TARGET_ARCH TOOL_CHAIN_TAG
BUILD_RULE_CONF MAX_CONCURRENT_THREAD_NUMBER"
%WORKSPACE%\Conf\target.txt > %OUTPUT_DIR%\target.txt 2>NUL
+echo ACTIVE_PLATFORM = %WORKSPACE%/edk2-
platforms/Platform/Intel/%BOARD_PKG%/%BOARD_NAME%/SimicsX58PkgIa3
2X64.dsc >> %OUTPUT_DIR%\target.txt
+echo TARGET = %TARGET% >>
%OUTPUT_DIR%\target.txt
+echo TARGET_ARCH = IA32 X64 >>
%OUTPUT_DIR%\target.txt
+echo TOOL_CHAIN_TAG = %TOOL_CHAIN_TAG% >>
%OUTPUT_DIR%\target.txt
+echo BUILD_RULE_CONF = Conf/build_rule.txt >>
%OUTPUT_DIR%\target.txt
+echo MAX_CONCURRENT_THREAD_NUMBER =
%BUILD_MAX_CON_THREAD_NUM% >> %OUTPUT_DIR%\target.txt
+if exist %WORKSPACE%\Conf\target.txt (
+ del /f %WORKSPACE%\Conf\target.txt
+)
+move /Y %OUTPUT_DIR%\target.txt %WORKSPACE%\Conf\ > nul
+if not exist %OUTPUT_DIR%\X64 mkdir %OUTPUT_DIR%\X64
+GOTO :EOF
+
+
+:genPlatformOffsetHeaderFile
+echo.
+echo PreBuild.%prebuildstep% GenPlatformOffsetHeaderFile
+set /a prebuildstep=%prebuildstep%+1
+
+echo Info: re-generating PlatformOffset header files
+
+set PRE_BUILD_CMD_LINE=%BUILD_CMD_LINE% -D
MAX_SOCKET=%MAX_SOCKET%
+set PRE_BUILD_LOG=%WORKSPACE%\Build\BuildSrc\prebuild.log
+set PRE_BUILD_REPORT=%WORKSPACE%\Build\BuildSrc\preBuildReport.txt
+
+echo build %PRE_BUILD_CMD_LINE% -m
%BOARD_PKG%\Acpi\BoardAcpiDxe\Dsdt.inf -y %PRE_BUILD_REPORT% --
log=%PRE_BUILD_LOG%
+call build %PRE_BUILD_CMD_LINE% -m
%BOARD_PKG%\Acpi\BoardAcpiDxe\Dsdt.inf -y %PRE_BUILD_REPORT% --
log=%PRE_BUILD_LOG%
+if %ERRORLEVEL% NEQ 0 EXIT /b %ERRORLEVEL%
+
+@REM PSYS == FIX0
+@REM MCTL == FIX8
+set AML_FILTER="\"PSYS\" .MCTL\" .FIX[0-9,A-Z]\""
+echo AML_FILTER=%AML_FILTER%
+%WORKSPACE%\edk2-
platforms\Platform\Intel\MinPlatformPkg\Tools\AmlGenOffset\AmlGenOffset.
py -d --aml_filter %AML_FILTER% -o %WORKSPACE%\edk2-
platforms\Platform\Intel\%BOARD_PKG%\Acpi\BoardAcpiDxe\AmlOffsetTable.
c
%OUTPUT_DIR%\X64\PurleyOpenBoardPkg\Acpi\BoardAcpiDxe\DSDT\OUTPU
T\Dsdt\WFPPlatform.offset.h
+echo.
+echo GenOffset done
+
+GOTO :EOF
--
2.16.2.windows.1

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