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I am not sure what do you mean - "You do not need a reset vector ...".
If so, where is the first instruction of the new CPU in the virtualization environment?
Please help me understand that at first. Then we can continue the discussion.
From: Paolo Bonzini [mailto:email@example.com]
Sent: Wednesday, August 14, 2019 10:05 PM
To: Yao, Jiewen <firstname.lastname@example.org>; Laszlo Ersek
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Subject: Re: CPU hotplug using SMM with QEMU+OVMF
On 14/08/19 15:20, Yao, Jiewen wrote:
- Does this part require a new branch somewhere in the OVMF SEC code?[Jiewen] I think this is blocked from hardware perspective, since the first
How do we determine whether the CPU executing SEC is BSP or
There are some hardware specific registers can be used to determine if theCPU is new added.
I don’t think this must be same as the real hardware.hot plug driver.
You are free to invent some registers in device model to be used in OVMF
Yes, this would be a new operation mode for QEMU, that only applies to
hot-plugged CPUs. In this mode the AP doesn't reply to INIT or SMI, in
fact it doesn't reply to anything at all.
You do not need a reset vector or INIT/SIPI/SIPI sequence at all in
- How do we tell the hot-plugged AP where to start execution? (I.e. that[Jiewen] Same real mode reset vector at FFFF:FFF0.
it should execute code at a particular pflash location.)
QEMU. The AP does not start execution at all when it is unplugged, so
no cache-as-RAM etc.
We only need to modify QEMU so that hot-plugged APIs do not reply to
I don’t think there is problem for real hardware, who always has CAR.Why is a CPU-specific region needed if every other processor is in SMM
Can QEMU provide some CPU specific space, such as MMIO region?
and thus trusted.
I can answer this: the SMM handler would interact with the hotplug
Does CPU hotplug apply only at the socket level? If the CPU is
multi-core, what is responsible for hot-plugging all cores present in
controller in the same way that ACPI DSDT does normally. This supports
multiple hotplugs already.
Writes to the hotplug controller from outside SMM would be ignored.
The QEMU DSDT could be modified (when secure boot is in effect) to OUT
(03) New CPU: (Flash) send board message to tell host CPU (GPIO->SCI)Maybe we can simplify this in QEMU by broadcasting an SMI to existent
-- I am waiting for hot-add message.
processors immediately upon plugging the new CPU.
to 0xB2 when hotplug happens. It could write a well-known value to
0xB2, to be read by an SMI handler in edk2.
(NOTE: Host CPU can
send[Jiewen] The new CPU does not enable SMI at reset.
instruction in SMM mode. -- The register is SMM only)Sorry, I don't follow -- what register are we talking about here, and
why is the BSP needed to send anything at all? What "instruction" do you
have in mind?
At some point of time later, the CPU need enable SMI, right?
The "instruction" here means, the host CPUs need tell to CPU to enable
Right, this would be a write to the CPU hotplug controller
(04) Host CPU: (OS) get message from board that a new CPU is added.I don't understand the OS involvement here. But, again, perhaps QEMU
(GPIO -> SCI)
(05) Host CPU: (OS) All CPUs enter SMM (SCI->SWSMI) (NOTE: New CPU
will not enter CPU because SMI is disabled)
in SMM environment.
force all existent CPUs into SMM immediately upon adding the new CPU.[Jiewen] OS here means the Host CPU running code in OS environment, not
[Jiewen] Right. That is the register to let host CPU tell new CPU to enable
(06) Host CPU: (SMM) Save 38000, Update 38000 -- fill simple SMMAha, so this is the SMM-only register you mention in step (03). Is the
(07) Host CPU: (SMM) Send message to New CPU to Enable SMI.
register specified in the Intel SDM?
It is platform specific register. Not defined in SDM.See above.
You may invent one in device model.
(10) New CPU: (SMM) Response first SMI at 38000, and rebase SMBASE
TSEG.What code does the new CPU execute after it completes step (10)? Does
So in our case we'd need an INIT/SIPI/SIPI sequence between (06) and (07).
halt?[Jiewen] The new CPU exits SMM and return to original place - where it is
interrupted to enter SMM - running code on the flash.
I'd rather avoid this and stay as close as possible to real hardware.
(11) Host CPU: (SMM) Restore 38000.These steps (i.e., (06) through (11)) don't appear RAS-specific. The
only platform-specific feature seems to be SMI masking register, which
could be extracted into a new SmmCpuFeaturesLib API.
Thus, would you please consider open sourcing firmware code for steps
(06) through (11)?
Alternatively -- and in particular because the stack for step (01)
concerns me --, we could approach this from a high-level, functional
perspective. The states that really matter are the relocated SMBASE for
the new CPU, and the state of the full system, right at the end of step
When the SMM setup quiesces during normal firmware boot, OVMF could
existent (finalized) SMBASE infomation to *pre-program* some virtual
QEMU hardware, with such state that would be expected, as "final" state,
of any new hotplugged CPU. Afterwards, if / when the hotplug actually
happens, QEMU could blanket-apply this state to the new CPU, and
broadcast a hardware SMI to all CPUs except the new one.